diff -r 74ca6c91a3fd -r fe3d1854af29 src/sim/ClockedObject.py
--- a/src/sim/ClockedObject.py	Fri Sep 21 17:07:25 2012 +0100
+++ b/src/sim/ClockedObject.py	Fri Sep 21 17:08:18 2012 +0100
@@ -37,9 +37,13 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
+from m5.proxy import *
 
 class ClockedObject(SimObject):
     type = 'ClockedObject'
     abstract = True
 
-    clock = Param.Clock('1t', "Clock speed")
+    # Clock period of this object, with the default value being the
+    # clock period of the parent object, unproxied at instantiation
+    # time
+    clock = Param.Clock(Parent.clock, "Clock period")
diff -r 74ca6c91a3fd -r fe3d1854af29 src/sim/System.py
--- a/src/sim/System.py	Fri Sep 21 17:07:25 2012 +0100
+++ b/src/sim/System.py	Fri Sep 21 17:08:18 2012 +0100
@@ -41,6 +41,10 @@
     type = 'System'
     system_port = MasterPort("System port")
 
+    # Override the clock from the MemObject which looks at the parent
+    # by default
+    clock = '1t'
+
     @classmethod
     def export_method_cxx_predecls(cls, code):
         code('#include "sim/system.hh"')