diff -r d42c8d6fd9a9 -r 3d5e3f0251ff tests/configs/twosys-tsunami-simple-atomic.py
--- a/tests/configs/twosys-tsunami-simple-atomic.py	Fri Sep 21 17:56:48 2012 +0100
+++ b/tests/configs/twosys-tsunami-simple-atomic.py	Fri Sep 21 17:56:49 2012 +0100
@@ -38,6 +38,7 @@
 # create the interrupt controller
 test_sys.cpu.createInterruptController()
 test_sys.cpu.connectAllPorts(test_sys.membus)
+test_sys.cpu.clock = '2GHz'
 # In contrast to the other (one-system) Tsunami configurations we do
 # not have an IO cache but instead rely on an IO bridge for accesses
 # from masters on the IO bus to the memory bus
@@ -51,6 +52,7 @@
 # create the interrupt controller
 drive_sys.cpu.createInterruptController()
 drive_sys.cpu.connectAllPorts(drive_sys.membus)
+drive_sys.cpu.clock = '4GHz'
 drive_sys.iobridge = Bridge(delay='50ns', ranges = [AddrRange(0, '8GB')])
 drive_sys.iobridge.slave = drive_sys.iobus.master
 drive_sys.iobridge.master = drive_sys.membus.slave