diff -r 0cc4775e3251 -r ef6840cfba82 tests/configs/memtest-ruby.py
--- a/tests/configs/memtest-ruby.py	Fri Sep 28 14:18:48 2012 +0100
+++ b/tests/configs/memtest-ruby.py	Fri Sep 28 14:20:26 2012 +0100
@@ -69,7 +69,7 @@
 nb_cores = 8
 
 # ruby does not support atomic, functional, or uncacheable accesses
-cpus = [ MemTest(atomic=False, percent_functional=50,
+cpus = [ MemTest(clock = '2GHz', atomic=False, percent_functional=50,
                  percent_uncacheable=0, suppress_func_warnings=True) \
          for i in xrange(nb_cores) ]
 
diff -r 0cc4775e3251 -r ef6840cfba82 tests/configs/memtest.py
--- a/tests/configs/memtest.py	Fri Sep 28 14:18:48 2012 +0100
+++ b/tests/configs/memtest.py	Fri Sep 28 14:20:26 2012 +0100
@@ -55,16 +55,16 @@
 
 #MAX CORES IS 8 with the fals sharing method
 nb_cores = 8
-cpus = [ MemTest() for i in xrange(nb_cores) ]
+cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ]
 
 # system simulated
 system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
                 funcbus = NoncoherentBus(),
                 physmem = SimpleMemory(),
-                membus = CoherentBus(clock="500GHz", width=16))
+                membus = CoherentBus(clock="1GHz", width=16))
 
 # l2cache & bus
-system.toL2Bus = CoherentBus(clock="500GHz", width=16)
+system.toL2Bus = CoherentBus(clock="2GHz", width=16)
 system.l2c = L2(size='64kB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master