diff -r d4be1972a2a9 -r c4f9c0ceb55d configs/common/Caches.py
--- a/configs/common/Caches.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/configs/common/Caches.py	Mon Oct 08 14:55:45 2012 +0100
@@ -1,3 +1,15 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -31,8 +43,8 @@
 class L1Cache(BaseCache):
     assoc = 2
     block_size = 64
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     mshrs = 10
     tgts_per_mshr = 20
     is_top_level = True
@@ -40,16 +52,16 @@
 class L2Cache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 20
     tgts_per_mshr = 12
 
 class PageTableWalkerCache(BaseCache):
     assoc = 2
     block_size = 64
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     mshrs = 10
     size = '1kB'
     tgts_per_mshr = 12
@@ -58,8 +70,8 @@
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
diff -r d4be1972a2a9 -r c4f9c0ceb55d configs/common/O3_ARM_v7a.py
--- a/configs/common/O3_ARM_v7a.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/configs/common/O3_ARM_v7a.py	Mon Oct 08 14:55:45 2012 +0100
@@ -145,10 +145,9 @@
     defer_registration= False
 
 # Instruction Cache
-# All latencys assume a 1GHz clock rate, with a faster clock they would be faster
 class O3_ARM_v7a_ICache(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 1
+    response_latency = 1
     block_size = 64
     mshrs = 2
     tgts_per_mshr = 8
@@ -157,10 +156,9 @@
     is_top_level = 'true'
 
 # Data Cache
-# All latencys assume a 1GHz clock rate, with a faster clock they would be faster
 class O3_ARM_v7a_DCache(BaseCache):
-    hit_latency = '2ns'
-    response_latency = '2ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 6
     tgts_per_mshr = 8
@@ -172,8 +170,8 @@
 # TLB Cache 
 # Use a cache as a L2 TLB
 class O3_ARM_v7aWalkCache(BaseCache):
-    hit_latency = '4ns'
-    response_latency = '4ns'
+    hit_latency = 4
+    response_latency = 4
     block_size = 64
     mshrs = 6
     tgts_per_mshr = 8
@@ -184,10 +182,9 @@
 
 
 # L2 Cache
-# All latencys assume a 1GHz clock rate, with a faster clock they would be faster
 class O3_ARM_v7aL2(BaseCache):
-    hit_latency = '12ns'
-    response_latency = '12ns'
+    hit_latency = 12
+    response_latency = 12
     block_size = 64
     mshrs = 16
     tgts_per_mshr = 8
@@ -196,5 +193,5 @@
     write_buffers = 8
     prefetch_on_access = 'true'
     # Simple stride prefetcher
-    prefetcher = StridePrefetcher(degree=8, latency='1.0ns')
+    prefetcher = StridePrefetcher(degree=8, latency = 1)
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/BaseCache.py
--- a/src/mem/cache/BaseCache.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/BaseCache.py	Mon Oct 08 14:55:45 2012 +0100
@@ -1,3 +1,15 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2005-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -36,8 +48,8 @@
     type = 'BaseCache'
     assoc = Param.Int("associativity")
     block_size = Param.Int("block size in bytes")
-    hit_latency = Param.Latency("The hit latency for this cache")
-    response_latency = Param.Latency(
+    hit_latency = Param.Cycles("The hit latency for this cache")
+    response_latency = Param.Cycles(
             "Additional cache latency for the return path to core on a miss");
     hash_delay = Param.Cycles(1, "time in cycles of hash access")
     max_miss_count = Param.Counter(0,
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/base.hh
--- a/src/mem/cache/base.hh	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/base.hh	Mon Oct 08 14:55:45 2012 +0100
@@ -229,7 +229,7 @@
     /**
      * The latency of a hit in this device.
      */
-    const Tick hitLatency;
+    const Cycles hitLatency;
 
     /**
      * The latency of sending reponse to its upper level cache/core on a
@@ -237,7 +237,7 @@
      * miss is much quicker that the hit latency. The responseLatency parameter
      * tries to capture this latency.
      */
-    const Tick responseLatency;
+    const Cycles responseLatency;
 
     /** The number of targets for each MSHR. */
     const int numTarget;
@@ -260,7 +260,7 @@
     uint64_t order;
 
     /** Stores time the cache blocked for statistics. */
-    Tick blockedCycle;
+    Cycles blockedCycle;
 
     /** Pointer to the MSHR that has no targets. */
     MSHR *noTargetMSHR;
@@ -492,7 +492,7 @@
         uint8_t flag = 1 << cause;
         if (blocked == 0) {
             blocked_causes[cause]++;
-            blockedCycle = curTick();
+            blockedCycle = curCycle();
             cpuSidePort->setBlocked();
         }
         blocked |= flag;
@@ -512,7 +512,7 @@
         blocked &= ~flag;
         DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
         if (blocked == 0) {
-            blocked_cycles[cause] += curTick() - blockedCycle;
+            blocked_cycles[cause] += curCycle() - blockedCycle;
             cpuSidePort->clearBlocked();
         }
     }
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/base.cc
--- a/src/mem/cache/base.cc	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/base.cc	Mon Oct 08 14:55:45 2012 +0100
@@ -81,6 +81,10 @@
       addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
       system(p->system)
 {
+    // ensure the clock is not running at an unreasonable clock speed
+    if (clock == 1)
+        panic("Cache %s has a cycle time of 1 tick. Specify a clock.\n",
+              name());
 }
 
 void
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/cache.hh
--- a/src/mem/cache/cache.hh	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/cache.hh	Mon Oct 08 14:55:45 2012 +0100
@@ -206,7 +206,7 @@
      * @return Boolean indicating whether the request was satisfied.
      */
     bool access(PacketPtr pkt, BlkType *&blk,
-                int &lat, PacketList &writebacks);
+                Cycles &lat, PacketList &writebacks);
 
     /**
      *Handle doing the Compare and Swap function for SPARC.
@@ -272,7 +272,7 @@
     /**
      * Performs the access specified by the request.
      * @param pkt The request to perform.
-     * @return The result of the access.
+     * @return The number of ticks required for the access.
      */
     Tick atomicAccess(PacketPtr pkt);
 
@@ -299,9 +299,9 @@
      * Snoop for the provided request in the cache and return the estimated
      * time of completion.
      * @param pkt The memory request to snoop
-     * @return The estimated completion time.
+     * @return The number of cycles required for the snoop.
      */
-    Tick snoopAtomic(PacketPtr pkt);
+    Cycles snoopAtomic(PacketPtr pkt);
 
     /**
      * Squash all requests associated with specified thread.
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/cache_impl.hh	Mon Oct 08 14:55:45 2012 +0100
@@ -275,7 +275,7 @@
 template<class TagStore>
 bool
 Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
-                        int &lat, PacketList &writebacks)
+                        Cycles &lat, PacketList &writebacks)
 {
     if (pkt->req->isUncacheable()) {
         if (pkt->req->isClearLL()) {
@@ -392,7 +392,7 @@
     pendingDelete.clear();
 
     // we charge hitLatency for doing just about anything here
-    Tick time =  curTick() + hitLatency;
+    Tick time = clockEdge(hitLatency);
 
     if (pkt->isResponse()) {
         // must be cache-to-cache response from upper to lower level
@@ -463,7 +463,7 @@
         return true;
     }
 
-    int lat = hitLatency;
+    Cycles lat = hitLatency;
     BlkType *blk = NULL;
     PacketList writebacks;
 
@@ -505,7 +505,7 @@
 
         if (needsResponse) {
             pkt->makeTimingResponse();
-            cpuSidePort->schedTimingResp(pkt, curTick()+lat);
+            cpuSidePort->schedTimingResp(pkt, clockEdge(lat));
         } else {
             /// @todo nominally we should just delete the packet here,
             /// however, until 4-phase stuff we can't because sending
@@ -637,7 +637,7 @@
 Tick
 Cache<TagStore>::atomicAccess(PacketPtr pkt)
 {
-    int lat = hitLatency;
+    Cycles lat = hitLatency;
 
     // @TODO: make this a parameter
     bool last_level_cache = false;
@@ -657,7 +657,7 @@
             if (!last_level_cache) {
                 DPRINTF(Cache, "forwarding mem-inhibited %s on 0x%x\n",
                         pkt->cmdString(), pkt->getAddr());
-                lat += memSidePort->sendAtomic(pkt);
+                lat += ticksToCycles(memSidePort->sendAtomic(pkt));
             }
         } else {
             DPRINTF(Cache, "rcvd mem-inhibited %s on 0x%x: not responding\n",
@@ -693,7 +693,7 @@
         CacheBlk::State old_state = blk ? blk->status : 0;
 #endif
 
-        lat += memSidePort->sendAtomic(bus_pkt);
+        lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt));
 
         DPRINTF(Cache, "Receive response: %s for addr %x in state %i\n",
                 bus_pkt->cmdString(), bus_pkt->getAddr(), old_state);
@@ -821,7 +821,7 @@
 void
 Cache<TagStore>::handleResponse(PacketPtr pkt)
 {
-    Tick time = curTick() + hitLatency;
+    Tick time = clockEdge(hitLatency);
     MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
     bool is_error = pkt->isError();
 
@@ -901,7 +901,7 @@
                 // responseLatency is the latency of the return path
                 // from lower level caches/memory to an upper level cache or
                 // the core.
-                completion_time = responseLatency +
+                completion_time = responseLatency * clock +
                     (transfer_offset ? pkt->finishTime : pkt->firstWordTime);
 
                 assert(!target->pkt->req->isUncacheable());
@@ -917,13 +917,13 @@
                 // responseLatency is the latency of the return path
                 // from lower level caches/memory to an upper level cache or
                 // the core.
-                completion_time = responseLatency + pkt->finishTime;
+                completion_time = responseLatency * clock + pkt->finishTime;
                 target->pkt->req->setExtraData(0);
             } else {
                 // not a cache fill, just forwarding response
                 // responseLatency is the latency of the return path
                 // from lower level cahces/memory to the core.
-                completion_time = responseLatency + pkt->finishTime;
+                completion_time = responseLatency * clock + pkt->finishTime;
                 if (pkt->isRead() && !is_error) {
                     target->pkt->setData(pkt->getPtr<uint8_t>());
                 }
@@ -1173,7 +1173,7 @@
         // invalidate it.
         pkt->cmd = MemCmd::ReadRespWithInvalidate;
     }
-    memSidePort->schedTimingSnoopResp(pkt, curTick() + hitLatency);
+    memSidePort->schedTimingSnoopResp(pkt, clockEdge(hitLatency));
 }
 
 template<class TagStore>
@@ -1366,7 +1366,7 @@
 }
 
 template<class TagStore>
-Tick
+Cycles
 Cache<TagStore>::snoopAtomic(PacketPtr pkt)
 {
     if (pkt->req->isUncacheable() || pkt->cmd == MemCmd::Writeback) {
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/prefetch/Prefetcher.py
--- a/src/mem/cache/prefetch/Prefetcher.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/prefetch/Prefetcher.py	Mon Oct 08 14:55:45 2012 +0100
@@ -1,8 +1,48 @@
-from m5.SimObject import SimObject
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+from ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
 
-class BasePrefetcher(SimObject):
+class BasePrefetcher(ClockedObject):
     type = 'BasePrefetcher'
     abstract = True
     size = Param.Int(100,
@@ -13,8 +53,7 @@
          "Squash prefetches with a later time on a subsequent miss")
     degree = Param.Int(1,
          "Degree of the prefetch depth")
-    latency = Param.Latency('10t',
-         "Latency of the prefetcher")
+    latency = Param.Cycles('1', "Latency of the prefetcher")
     use_master_id = Param.Bool(True,
          "Use the master id to separate calculations of prefetches")
     data_accesses_only = Param.Bool(False,
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/prefetch/base.hh
--- a/src/mem/cache/prefetch/base.hh	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/prefetch/base.hh	Mon Oct 08 14:55:45 2012 +0100
@@ -41,11 +41,11 @@
 #include "base/statistics.hh"
 #include "mem/packet.hh"
 #include "params/BaseCache.hh"
-#include "sim/sim_object.hh"
+#include "sim/clocked_object.hh"
 
 class BaseCache;
 
-class BasePrefetcher : public SimObject
+class BasePrefetcher : public ClockedObject
 {
   protected:
 
@@ -64,7 +64,7 @@
     int blkSize;
 
     /** The latency before a prefetch is issued */
-    Tick latency;
+    const Cycles latency;
 
     /** The number of prefetches to issue */
     unsigned degree;
@@ -133,7 +133,7 @@
 
     virtual void calculatePrefetch(PacketPtr &pkt,
                                    std::list<Addr> &addresses,
-                                   std::list<Tick> &delays) = 0;
+                                   std::list<Cycles> &delays) = 0;
 
     std::list<PacketPtr>::iterator inPrefetch(Addr address);
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/prefetch/base.cc
--- a/src/mem/cache/prefetch/base.cc	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/prefetch/base.cc	Mon Oct 08 14:55:45 2012 +0100
@@ -45,7 +45,7 @@
 #include "sim/system.hh"
 
 BasePrefetcher::BasePrefetcher(const Params *p)
-    : SimObject(p), size(p->size), latency(p->latency), degree(p->degree),
+    : ClockedObject(p), size(p->size), latency(p->latency), degree(p->degree),
       useMasterId(p->use_master_id), pageStop(!p->cross_pages),
       serialSquash(p->serial_squash), onlyData(p->data_accesses_only),
       system(p->sys), masterId(system->getMasterId(name()))
@@ -212,11 +212,11 @@
 
 
         std::list<Addr> addresses;
-        std::list<Tick> delays;
+        std::list<Cycles> delays;
         calculatePrefetch(pkt, addresses, delays);
 
         std::list<Addr>::iterator addrIter = addresses.begin();
-        std::list<Tick>::iterator delayIter = delays.begin();
+        std::list<Cycles>::iterator delayIter = delays.begin();
         for (; addrIter != addresses.end(); ++addrIter, ++delayIter) {
             Addr addr = *addrIter;
 
@@ -241,7 +241,7 @@
             prefetch->req->setThreadContext(pkt->req->contextId(),
                                             pkt->req->threadId());
 
-            prefetch->time = time + (*delayIter); // @todo ADD LATENCY HERE
+            prefetch->time = time + clock * *delayIter;
 
             // We just remove the head if we are full
             if (pf.size() == size) {
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/prefetch/ghb.hh
--- a/src/mem/cache/prefetch/ghb.hh	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/prefetch/ghb.hh	Mon Oct 08 14:55:45 2012 +0100
@@ -57,7 +57,7 @@
     ~GHBPrefetcher() {}
 
     void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
-                           std::list<Tick> &delays);
+                           std::list<Cycles> &delays);
 };
 
 #endif // __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/prefetch/ghb.cc
--- a/src/mem/cache/prefetch/ghb.cc	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/prefetch/ghb.cc	Mon Oct 08 14:55:45 2012 +0100
@@ -40,7 +40,7 @@
 
 void
 GHBPrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
-                                 std::list<Tick> &delays)
+                                 std::list<Cycles> &delays)
 {
     Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
     int master_id = useMasterId ? pkt->req->masterId() : 0;
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/prefetch/stride.hh
--- a/src/mem/cache/prefetch/stride.hh	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/prefetch/stride.hh	Mon Oct 08 14:55:45 2012 +0100
@@ -75,7 +75,7 @@
     ~StridePrefetcher() {}
 
     void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
-                           std::list<Tick> &delays);
+                           std::list<Cycles> &delays);
 };
 
 #endif // __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/prefetch/stride.cc
--- a/src/mem/cache/prefetch/stride.cc	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/prefetch/stride.cc	Mon Oct 08 14:55:45 2012 +0100
@@ -40,7 +40,7 @@
 
 void
 StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
-                                    std::list<Tick> &delays)
+                                    std::list<Cycles> &delays)
 {
     if (!pkt->req->hasPC()) {
         DPRINTF(HWPrefetch, "ignoring request with no PC");
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/prefetch/tagged.hh
--- a/src/mem/cache/prefetch/tagged.hh	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/prefetch/tagged.hh	Mon Oct 08 14:55:45 2012 +0100
@@ -49,7 +49,7 @@
     ~TaggedPrefetcher() {}
 
     void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
-                           std::list<Tick> &delays);
+                           std::list<Cycles> &delays);
 };
 
 #endif // __MEM_CACHE_PREFETCH_TAGGED_PREFETCHER_HH__
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/prefetch/tagged.cc
--- a/src/mem/cache/prefetch/tagged.cc	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/prefetch/tagged.cc	Mon Oct 08 14:55:45 2012 +0100
@@ -43,7 +43,7 @@
 void
 TaggedPrefetcher::
 calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
-                  std::list<Tick> &delays)
+                  std::list<Cycles> &delays)
 {
     Addr blkAddr = pkt->getAddr() & ~(Addr)(blkSize-1);
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/tags/fa_lru.hh
--- a/src/mem/cache/tags/fa_lru.hh	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/tags/fa_lru.hh	Mon Oct 08 14:55:45 2012 +0100
@@ -85,7 +85,7 @@
     /** The size of the cache. */
     const unsigned size;
     /** The hit latency of the cache. */
-    const unsigned hitLatency;
+    const Cycles hitLatency;
 
     /** Array of pointers to blocks at the cache size  boundaries. */
     FALRUBlk **cacheBoundaries;
@@ -155,7 +155,7 @@
      * @param size The size of the cache.
      * @param hit_latency The hit latency of the cache.
      */
-    FALRU(unsigned blkSize, unsigned size, unsigned hit_latency);
+    FALRU(unsigned blkSize, unsigned size, Cycles hit_latency);
     ~FALRU();
 
     /**
@@ -181,7 +181,7 @@
      * @param inCache The FALRUBlk::inCache flags.
      * @return Pointer to the cache block.
      */
-    FALRUBlk* accessBlock(Addr addr, int &lat, int context_src, int *inCache = 0);
+    FALRUBlk* accessBlock(Addr addr, Cycles &lat, int context_src, int *inCache = 0);
 
     /**
      * Find the block in the cache, do not update the replacement data.
@@ -205,7 +205,7 @@
      * Return the hit latency of this cache.
      * @return The hit latency.
      */
-    int getHitLatency() const
+    Cycles getHitLatency() const
     {
         return hitLatency;
     }
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/tags/fa_lru.cc
--- a/src/mem/cache/tags/fa_lru.cc	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/tags/fa_lru.cc	Mon Oct 08 14:55:45 2012 +0100
@@ -42,7 +42,7 @@
 
 using namespace std;
 
-FALRU::FALRU(unsigned _blkSize, unsigned _size, unsigned hit_latency)
+FALRU::FALRU(unsigned _blkSize, unsigned _size, Cycles hit_latency)
     : blkSize(_blkSize), size(_size), hitLatency(hit_latency)
 {
     if (!isPowerOf2(blkSize))
@@ -159,7 +159,7 @@
 }
 
 FALRUBlk*
-FALRU::accessBlock(Addr addr, int &lat, int context_src, int *inCache)
+FALRU::accessBlock(Addr addr, Cycles &lat, int context_src, int *inCache)
 {
     accesses++;
     int tmp_in_cache = 0;
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/tags/iic.hh
--- a/src/mem/cache/tags/iic.hh	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/tags/iic.hh	Mon Oct 08 14:55:45 2012 +0100
@@ -176,7 +176,7 @@
     /** The associativity of the primary table. */
     const unsigned assoc;
     /** The base hit latency. */
-    const unsigned hitLatency;
+    const Cycles hitLatency;
     /** The subblock size, used for compression. */
     const unsigned subSize;
 
@@ -278,9 +278,9 @@
         /** The associativity of the primary table. */
         unsigned assoc;
         /** The number of cycles for each hash lookup. */
-        unsigned hashDelay;
+        Cycles hashDelay;
         /** The number of cycles to read the data. */
-        unsigned hitLatency;
+        Cycles hitLatency;
         /** The replacement policy. */
         Repl *rp;
         /** The subblock size in bytes. */
@@ -420,7 +420,7 @@
      * @param lat The access latency.
      * @return A pointer to the block found, if any.
      */
-    IICTag* accessBlock(Addr addr, int &lat, int context_src);
+    IICTag* accessBlock(Addr addr, Cycles &lat, int context_src);
 
     /**
      * Find the block, do not update the replacement data.
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/tags/iic.cc
--- a/src/mem/cache/tags/iic.cc	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/tags/iic.cc	Mon Oct 08 14:55:45 2012 +0100
@@ -220,11 +220,11 @@
 
 
 IICTag*
-IIC::accessBlock(Addr addr, int &lat, int context_src)
+IIC::accessBlock(Addr addr, Cycles &lat, int context_src)
 {
     Addr tag = extractTag(addr);
     unsigned set = hash(addr);
-    int set_lat;
+    Cycles set_lat;
 
     unsigned long chain_ptr = tagNull;
 
@@ -232,11 +232,11 @@
         setAccess.sample(set);
 
     IICTag *tag_ptr = sets[set].findTag(tag, chain_ptr);
-    set_lat = 1;
+    set_lat = Cycles(1);
     if (tag_ptr == NULL && chain_ptr != tagNull) {
         int secondary_depth;
         tag_ptr = secondaryChain(tag, chain_ptr, &secondary_depth);
-        set_lat += secondary_depth;
+        set_lat += Cycles(secondary_depth);
         // set depth for statistics fix this later!!! egh
         sets[set].depth = set_lat;
 
@@ -250,9 +250,7 @@
         }
 
     }
-    // @todo: is hashDelay is really cycles, then
-    // multiply with period
-    set_lat = set_lat * hashDelay + hitLatency;
+    set_lat = Cycles(set_lat * hashDelay + hitLatency);
     if (tag_ptr != NULL) {
         // IIC replacement: if this is not the first element of
         //   list, reorder
@@ -263,8 +261,9 @@
         hitDepthTotal += sets[set].depth;
         tag_ptr->status |= BlkReferenced;
         lat = set_lat;
-        if (tag_ptr->whenReady > curTick() && tag_ptr->whenReady - curTick() > set_lat) {
-            lat = tag_ptr->whenReady - curTick();
+        if (tag_ptr->whenReady > curTick() &&
+            cache->ticksToCycles(tag_ptr->whenReady - curTick()) > set_lat) {
+            lat = cache->ticksToCycles(tag_ptr->whenReady - curTick());
         }
 
         tag_ptr->refCount += 1;
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/tags/lru.hh
--- a/src/mem/cache/tags/lru.hh	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/tags/lru.hh	Mon Oct 08 14:55:45 2012 +0100
@@ -68,7 +68,7 @@
     /** The associativity of the cache. */
     const unsigned assoc;
     /** The hit latency. */
-    const unsigned hitLatency;
+    const Cycles hitLatency;
 
     /** The cache sets. */
     CacheSet *sets;
@@ -139,7 +139,7 @@
      * @param lat The access latency.
      * @return Pointer to the cache block if found.
      */
-    BlkType* accessBlock(Addr addr, int &lat, int context_src);
+    BlkType* accessBlock(Addr addr, Cycles &lat, int context_src);
 
     /**
      * Finds the given address in the cache, do not update replacement data.
@@ -221,7 +221,7 @@
      * Return the hit latency.
      * @return the hit latency.
      */
-    int getHitLatency() const
+    Cycles getHitLatency() const
     {
         return hitLatency;
     }
diff -r d4be1972a2a9 -r c4f9c0ceb55d src/mem/cache/tags/lru.cc
--- a/src/mem/cache/tags/lru.cc	Mon Oct 08 14:37:23 2012 +0100
+++ b/src/mem/cache/tags/lru.cc	Mon Oct 08 14:55:45 2012 +0100
@@ -116,7 +116,7 @@
 }
 
 LRU::BlkType*
-LRU::accessBlock(Addr addr, int &lat, int master_id)
+LRU::accessBlock(Addr addr, Cycles &lat, int master_id)
 {
     Addr tag = extractTag(addr);
     unsigned set = extractSet(addr);
@@ -128,8 +128,8 @@
         DPRINTF(CacheRepl, "set %x: moving blk %x to MRU\n",
                 set, regenerateBlkAddr(tag, set));
         if (blk->whenReady > curTick()
-            && blk->whenReady - curTick() > hitLatency) {
-            lat = blk->whenReady - curTick();
+            && cache->ticksToCycles(blk->whenReady - curTick()) > hitLatency) {
+            lat = cache->ticksToCycles(blk->whenReady - curTick());
         }
         blk->refCount += 1;
     }
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/inorder-timing.py
--- a/tests/configs/inorder-timing.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/inorder-timing.py	Mon Oct 08 14:55:45 2012 +0100
@@ -33,8 +33,8 @@
 class MyCache(BaseCache):
     assoc = 2
     block_size = 64
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     mshrs = 10
     tgts_per_mshr = 5
 
@@ -44,8 +44,8 @@
 cpu = InOrderCPU(cpu_id=0)
 cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
                               MyL1Cache(size = '256kB'),
-                              MyCache(size = '2MB', hit_latency='10ns',
-                                      response_latency='10ns'))
+                              MyCache(size = '2MB', hit_latency = 20,
+                                      response_latency = 20))
 
 cpu.clock = '2GHz'
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/memtest.py
--- a/tests/configs/memtest.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/memtest.py	Mon Oct 08 14:55:45 2012 +0100
@@ -34,8 +34,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 12
     tgts_per_mshr = 8
@@ -47,8 +47,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -65,7 +65,7 @@
 
 # l2cache & bus
 system.toL2Bus = CoherentBus(clock="2GHz", width=16)
-system.l2c = L2(size='64kB', assoc=8)
+system.l2c = L2(clock = '2GHz', size='64kB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 
 # connect l2c to membus
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/o3-timing-checker.py
--- a/tests/configs/o3-timing-checker.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/o3-timing-checker.py	Mon Oct 08 14:55:45 2012 +0100
@@ -42,8 +42,8 @@
 class MyCache(BaseCache):
     assoc = 2
     block_size = 64
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     mshrs = 10
     tgts_per_mshr = 5
 
@@ -57,6 +57,9 @@
 cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
                               MyL1Cache(size = '256kB'),
                               MyCache(size = '2MB'))
+# @todo Note that the L2 latency here is unmodified and 2 cycles,
+# should set hit latency and response latency to 20 cycles as for
+# other scripts
 cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/o3-timing-mp.py
--- a/tests/configs/o3-timing-mp.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/o3-timing-mp.py	Mon Oct 08 14:55:45 2012 +0100
@@ -35,8 +35,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 20
@@ -48,8 +48,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -61,8 +61,8 @@
 system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
 
 # l2cache & bus
-system.toL2Bus = CoherentBus()
-system.l2c = L2(size='4MB', assoc=8)
+system.toL2Bus = CoherentBus(clock = '2GHz')
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 
 # connect l2c to membus
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/o3-timing.py
--- a/tests/configs/o3-timing.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/o3-timing.py	Mon Oct 08 14:55:45 2012 +0100
@@ -33,8 +33,8 @@
 class MyCache(BaseCache):
     assoc = 2
     block_size = 64
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     mshrs = 10
     tgts_per_mshr = 5
 
@@ -46,6 +46,9 @@
 cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
                               MyL1Cache(size = '256kB'),
                               MyCache(size = '2MB'))
+# @todo Note that the L2 latency here is unmodified and 2 cycles,
+# should set hit latency and response latency to 20 cycles as for
+# other scripts
 cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/pc-o3-timing.py
--- a/tests/configs/pc-o3-timing.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/pc-o3-timing.py	Mon Oct 08 14:55:45 2012 +0100
@@ -39,8 +39,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 20
@@ -52,8 +52,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -64,8 +64,8 @@
 class PageTableWalkerCache(BaseCache):
     assoc = 2
     block_size = 64
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     mshrs = 10
     size = '1kB'
     tgts_per_mshr = 12
@@ -76,8 +76,8 @@
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '50ns'
-    response_latency = '50ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
@@ -94,7 +94,7 @@
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/pc-simple-atomic.py
--- a/tests/configs/pc-simple-atomic.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/pc-simple-atomic.py	Mon Oct 08 14:55:45 2012 +0100
@@ -39,8 +39,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
@@ -52,8 +52,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -64,8 +64,8 @@
 class PageTableWalkerCache(BaseCache):
     assoc = 2
     block_size = 64
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     mshrs = 10
     size = '1kB'
     tgts_per_mshr = 12
@@ -77,8 +77,8 @@
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '50ns'
-    response_latency = '50ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
@@ -96,7 +96,7 @@
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/pc-simple-timing.py
--- a/tests/configs/pc-simple-timing.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/pc-simple-timing.py	Mon Oct 08 14:55:45 2012 +0100
@@ -40,8 +40,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
@@ -53,8 +53,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -65,8 +65,8 @@
 class PageTableWalkerCache(BaseCache):
     assoc = 2
     block_size = 64
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     mshrs = 10
     size = '1kB'
     tgts_per_mshr = 12
@@ -77,8 +77,8 @@
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '50ns'
-    response_latency = '50ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
@@ -95,7 +95,7 @@
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/realview-o3-checker.py
--- a/tests/configs/realview-o3-checker.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/realview-o3-checker.py	Mon Oct 08 14:55:45 2012 +0100
@@ -46,8 +46,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 20
@@ -59,8 +59,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -71,8 +71,8 @@
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '50ns'
-    response_latency = '50ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
@@ -89,7 +89,7 @@
 cpu.addCheckerCpu()
 
 #create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/realview-o3-dual.py
--- a/tests/configs/realview-o3-dual.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/realview-o3-dual.py	Mon Oct 08 14:55:45 2012 +0100
@@ -37,8 +37,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 20
@@ -50,8 +50,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -62,8 +62,8 @@
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '50ns'
-    response_latency = '50ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
@@ -74,16 +74,16 @@
 cpus = [DerivO3CPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
 system.cpu = cpus
 #create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+system.toL2Bus = CoherentBus(clock = '2GHz')
 
 #connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 system.l2c.mem_side = system.membus.slave
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/realview-o3.py
--- a/tests/configs/realview-o3.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/realview-o3.py	Mon Oct 08 14:55:45 2012 +0100
@@ -37,8 +37,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 20
@@ -50,8 +50,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -62,8 +62,8 @@
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '50ns'
-    response_latency = '50ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
@@ -78,7 +78,7 @@
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/realview-simple-atomic-dual.py
--- a/tests/configs/realview-simple-atomic-dual.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/realview-simple-atomic-dual.py	Mon Oct 08 14:55:45 2012 +0100
@@ -37,8 +37,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
@@ -50,8 +50,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -62,8 +62,8 @@
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '50ns'
-    response_latency = '50ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
@@ -74,16 +74,16 @@
 cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
 system.cpu = cpus
 #create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+system.toL2Bus = CoherentBus(clock = '2GHz')
 
 #connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 system.l2c.mem_side = system.membus.slave
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/realview-simple-atomic.py
--- a/tests/configs/realview-simple-atomic.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/realview-simple-atomic.py	Mon Oct 08 14:55:45 2012 +0100
@@ -36,8 +36,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
@@ -49,8 +49,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -61,8 +61,8 @@
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '50ns'
-    response_latency = '50ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
@@ -77,7 +77,7 @@
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/realview-simple-timing-dual.py
--- a/tests/configs/realview-simple-timing-dual.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/realview-simple-timing-dual.py	Mon Oct 08 14:55:45 2012 +0100
@@ -37,8 +37,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
@@ -50,8 +50,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -62,8 +62,8 @@
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '50ns'
-    response_latency = '50ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
@@ -74,16 +74,16 @@
 cpus = [TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
 system.cpu = cpus
 #create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+system.toL2Bus = CoherentBus(clock = '2GHz')
 
 #connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 system.l2c.mem_side = system.membus.slave
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/realview-simple-timing.py
--- a/tests/configs/realview-simple-timing.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/realview-simple-timing.py	Mon Oct 08 14:55:45 2012 +0100
@@ -37,8 +37,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
@@ -50,8 +50,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -62,8 +62,8 @@
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '50ns'
-    response_latency = '50ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
@@ -78,7 +78,7 @@
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/simple-atomic-mp.py
--- a/tests/configs/simple-atomic-mp.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/simple-atomic-mp.py	Mon Oct 08 14:55:45 2012 +0100
@@ -34,8 +34,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
@@ -47,8 +47,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -62,8 +62,8 @@
                 membus = CoherentBus())
 
 # l2cache & bus
-system.toL2Bus = CoherentBus()
-system.l2c = L2(size='4MB', assoc=8)
+system.toL2Bus = CoherentBus(clock = '2GHz')
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 
 # connect l2c to membus
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/simple-timing-mp.py
--- a/tests/configs/simple-timing-mp.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/simple-timing-mp.py	Mon Oct 08 14:55:45 2012 +0100
@@ -34,8 +34,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
@@ -47,8 +47,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -60,8 +60,8 @@
 system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
 
 # l2cache & bus
-system.toL2Bus = CoherentBus()
-system.l2c = L2(size='4MB', assoc=8)
+system.toL2Bus = CoherentBus(clock = '2GHz')
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 
 # connect l2c to membus
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/simple-timing.py
--- a/tests/configs/simple-timing.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/simple-timing.py	Mon Oct 08 14:55:45 2012 +0100
@@ -32,8 +32,8 @@
 class MyCache(BaseCache):
     assoc = 2
     block_size = 64
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     mshrs = 10
     tgts_per_mshr = 5
 
@@ -43,7 +43,8 @@
 cpu = TimingSimpleCPU(cpu_id=0)
 cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
                               MyL1Cache(size = '256kB'),
-                              MyCache(size = '2MB', hit_latency='10ns', response_latency ='10ns'))
+                              MyCache(size = '2MB', hit_latency= 20,
+                                      response_latency = 20))
 system = System(cpu = cpu,
                 physmem = SimpleMemory(),
                 membus = CoherentBus())
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/tsunami-inorder.py
--- a/tests/configs/tsunami-inorder.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/tsunami-inorder.py	Mon Oct 08 14:55:45 2012 +0100
@@ -37,8 +37,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
@@ -50,8 +50,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -62,8 +62,8 @@
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '50ns'
-    response_latency = '50ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
@@ -82,7 +82,7 @@
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/tsunami-o3-dual.py
--- a/tests/configs/tsunami-o3-dual.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/tsunami-o3-dual.py	Mon Oct 08 14:55:45 2012 +0100
@@ -37,8 +37,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 20
@@ -50,8 +50,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -62,8 +62,8 @@
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '50ns'
-    response_latency = '50ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
@@ -78,14 +78,14 @@
 
 system.cpu = cpus
 #create the l1/l2 bus
-system.toL2Bus = CoherentBus()
-system.iocache = IOCache()
+system.toL2Bus = CoherentBus(clock = '2GHz')
+system.iocache = IOCache(clock = '1GHz')
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
 
 #connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 system.l2c.mem_side = system.membus.slave
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/tsunami-o3.py
--- a/tests/configs/tsunami-o3.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/tsunami-o3.py	Mon Oct 08 14:55:45 2012 +0100
@@ -37,8 +37,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 20
@@ -50,8 +50,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -62,8 +62,8 @@
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '50ns'
-    response_latency = '50ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
@@ -79,7 +79,7 @@
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock - '1GHz')
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/tsunami-simple-atomic-dual.py
--- a/tests/configs/tsunami-simple-atomic-dual.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/tsunami-simple-atomic-dual.py	Mon Oct 08 14:55:45 2012 +0100
@@ -36,8 +36,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
@@ -49,8 +49,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -61,8 +61,8 @@
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '50ns'
-    response_latency = '50ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
@@ -74,16 +74,16 @@
 cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeLinuxAlphaSystem('atomic')
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
 system.cpu = cpus
 #create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+system.toL2Bus = CoherentBus(clock = '2GHz')
 
 #connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 system.l2c.mem_side = system.membus.slave
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/tsunami-simple-atomic.py
--- a/tests/configs/tsunami-simple-atomic.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/tsunami-simple-atomic.py	Mon Oct 08 14:55:45 2012 +0100
@@ -36,8 +36,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
@@ -49,8 +49,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -61,8 +61,8 @@
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '50ns'
-    response_latency = '50ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
@@ -78,7 +78,7 @@
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/tsunami-simple-timing-dual.py
--- a/tests/configs/tsunami-simple-timing-dual.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/tsunami-simple-timing-dual.py	Mon Oct 08 14:55:45 2012 +0100
@@ -36,8 +36,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
@@ -49,8 +49,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -61,8 +61,8 @@
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '50ns'
-    response_latency = '50ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
@@ -74,16 +74,16 @@
 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeLinuxAlphaSystem('timing')
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
 system.cpu = cpus
 #create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+system.toL2Bus = CoherentBus(clock = '2GHz')
 
 #connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 system.l2c.mem_side = system.membus.slave
 
diff -r d4be1972a2a9 -r c4f9c0ceb55d tests/configs/tsunami-simple-timing.py
--- a/tests/configs/tsunami-simple-timing.py	Mon Oct 08 14:37:23 2012 +0100
+++ b/tests/configs/tsunami-simple-timing.py	Mon Oct 08 14:55:45 2012 +0100
@@ -37,8 +37,8 @@
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
@@ -50,8 +50,8 @@
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -62,8 +62,8 @@
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '50ns'
-    response_latency = '50ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
@@ -79,7 +79,7 @@
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave