diff -r f634a34f2f0b -r 4bbc82359d8b configs/common/CacheConfig.py --- a/configs/common/CacheConfig.py Tue Oct 23 04:49:48 2012 -0400 +++ b/configs/common/CacheConfig.py Tue Oct 23 20:20:23 2012 +0200 @@ -44,11 +44,13 @@ system.l2 = O3_ARM_v7aL2(clock = options.clock, size = options.l2_size, assoc = options.l2_assoc, + latency = options.l2_latency, block_size=options.cacheline_size) else: system.l2 = L2Cache(clock = options.clock, size = options.l2_size, assoc = options.l2_assoc, + latency = options.l2_latency, block_size = options.cacheline_size) system.tol2bus = CoherentBus(clock = options.clock, width = 32) @@ -60,16 +62,20 @@ if options.cpu_type == "arm_detailed": icache = O3_ARM_v7a_ICache(size = options.l1i_size, assoc = options.l1i_assoc, + latency = options.l1i_latency, block_size=options.cacheline_size) dcache = O3_ARM_v7a_DCache(size = options.l1d_size, assoc = options.l1d_assoc, + latency = options.l1d_latency, block_size=options.cacheline_size) else: icache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, + latency = options.l1i_latency, block_size=options.cacheline_size) dcache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, + latency = options.l1d_latency, block_size=options.cacheline_size) # When connecting the caches, the clock is also inherited diff -r f634a34f2f0b -r 4bbc82359d8b configs/common/Options.py --- a/configs/common/Options.py Tue Oct 23 04:49:48 2012 -0400 +++ b/configs/common/Options.py Tue Oct 23 20:20:23 2012 +0200 @@ -54,6 +54,10 @@ parser.add_option("--l1i_assoc", type="int", default=2) parser.add_option("--l2_assoc", type="int", default=8) parser.add_option("--l3_assoc", type="int", default=16) + parser.add_option("--l1d_latency", type="int", default="3") + parser.add_option("--l1i_latency", type="int", default="3") + parser.add_option("--l2_latency", type="int", default="15") + parser.add_option("--l3_latency", type="int", default="17") parser.add_option("--cacheline_size", type="int", default=64) parser.add_option("--ruby", action="store_true") parser.add_option("--smt", action="store_true", default=False, diff -r f634a34f2f0b -r 4bbc82359d8b configs/ruby/MESI_CMP_directory.py --- a/configs/ruby/MESI_CMP_directory.py Tue Oct 23 04:49:48 2012 -0400 +++ b/configs/ruby/MESI_CMP_directory.py Tue Oct 23 20:20:23 2012 +0200 @@ -37,13 +37,13 @@ # Note: the L1 Cache latency is only used by the sequencer on fast path hits # class L1Cache(RubyCache): - latency = 3 + pass # # Note: the L2 Cache latency is not currently used # class L2Cache(RubyCache): - latency = 15 + pass def define_options(parser): return @@ -80,9 +80,11 @@ # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, + latency = options.l1i_latency, start_index_bit = block_size_bits) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, + latency = options.l1d_latency, start_index_bit = block_size_bits) l1_cntrl = L1Cache_Controller(version = i, @@ -122,6 +124,7 @@ # l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, + latency = options.l2_latency, start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, diff -r f634a34f2f0b -r 4bbc82359d8b configs/ruby/MI_example.py --- a/configs/ruby/MI_example.py Tue Oct 23 04:49:48 2012 -0400 +++ b/configs/ruby/MI_example.py Tue Oct 23 20:20:23 2012 +0200 @@ -37,7 +37,7 @@ # Note: the cache latency is only used by the sequencer on fast path hits # class Cache(RubyCache): - latency = 3 + pass def define_options(parser): return @@ -74,6 +74,7 @@ # cache = Cache(size = options.l1d_size, assoc = options.l1d_assoc, + latency = options.l1d_latency, start_index_bit = block_size_bits) # diff -r f634a34f2f0b -r 4bbc82359d8b configs/ruby/MOESI_CMP_directory.py --- a/configs/ruby/MOESI_CMP_directory.py Tue Oct 23 04:49:48 2012 -0400 +++ b/configs/ruby/MOESI_CMP_directory.py Tue Oct 23 20:20:23 2012 +0200 @@ -37,13 +37,13 @@ # Note: the L1 Cache latency is only used by the sequencer on fast path hits # class L1Cache(RubyCache): - latency = 3 + pass # # Note: the L2 Cache latency is not currently used # class L2Cache(RubyCache): - latency = 15 + pass def define_options(parser): return @@ -80,9 +80,11 @@ # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, + latency = options.l1i_latency, start_index_bit = block_size_bits) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, + latency = options.l1d_latency, start_index_bit = block_size_bits) l1_cntrl = L1Cache_Controller(version = i, @@ -121,6 +123,7 @@ # l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, + latency = options.l2_latency, start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, diff -r f634a34f2f0b -r 4bbc82359d8b configs/ruby/MOESI_CMP_token.py --- a/configs/ruby/MOESI_CMP_token.py Tue Oct 23 04:49:48 2012 -0400 +++ b/configs/ruby/MOESI_CMP_token.py Tue Oct 23 20:20:23 2012 +0200 @@ -37,13 +37,13 @@ # Note: the L1 Cache latency is only used by the sequencer on fast path hits # class L1Cache(RubyCache): - latency = 2 + pass # # Note: the L2 Cache latency is not currently used # class L2Cache(RubyCache): - latency = 10 + pass def define_options(parser): parser.add_option("--l1-retries", type="int", default=1, @@ -93,9 +93,11 @@ # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, + latency = options.l1i_latency, start_index_bit = block_size_bits) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, + latency = options.l1d_latency, start_index_bit = block_size_bits) l1_cntrl = L1Cache_Controller(version = i, @@ -143,6 +145,7 @@ # l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, + latency = options.l2_latency, start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, diff -r f634a34f2f0b -r 4bbc82359d8b configs/ruby/MOESI_hammer.py --- a/configs/ruby/MOESI_hammer.py Tue Oct 23 04:49:48 2012 -0400 +++ b/configs/ruby/MOESI_hammer.py Tue Oct 23 20:20:23 2012 +0200 @@ -37,13 +37,13 @@ # Note: the L1 Cache latency is only used by the sequencer on fast path hits # class L1Cache(RubyCache): - latency = 2 + pass # # Note: the L2 Cache latency is not currently used # class L2Cache(RubyCache): - latency = 10 + pass # # Probe filter is a cache, latency is not used @@ -89,13 +89,16 @@ # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, + latency = options.l1i_latency, start_index_bit = block_size_bits, is_icache = True) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, + latency = options.l1d_latency, start_index_bit = block_size_bits) l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, + latency = options.l2_latency, start_index_bit = block_size_bits) l1_cntrl = L1Cache_Controller(version = i, diff -r f634a34f2f0b -r 4bbc82359d8b configs/ruby/Network_test.py --- a/configs/ruby/Network_test.py Tue Oct 23 04:49:48 2012 -0400 +++ b/configs/ruby/Network_test.py Tue Oct 23 20:20:23 2012 +0200 @@ -37,7 +37,7 @@ # Note: the cache latency is only used by the sequencer on fast path hits # class Cache(RubyCache): - latency = 3 + pass def define_options(parser): return @@ -77,7 +77,8 @@ # config parameters. # cache = Cache(size = options.l1d_size, - assoc = options.l1d_assoc) + assoc = options.l1d_assoc, + latency = options.l1d_latency) # # Only one unified L1 cache exists. Can cache instructions and data.