diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
@@ -683,15 +683,27 @@
     wakeUpBuffers(address);
   }
 
+  action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
+    peek(mandatoryQueue_in, RubyRequest) {
+        L1IcacheMemory.profileMiss(in_msg, CacheAccessType:HIT);
+    }
+  }
+
   action(uu_profileInstMiss, "\ui", desc="Profile the demand miss") {
     peek(mandatoryQueue_in, RubyRequest) {
-        L1IcacheMemory.profileMiss(in_msg);
+        L1IcacheMemory.profileMiss(in_msg, CacheAccessType:MISS);
+    }
+  }
+
+  action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
+    peek(mandatoryQueue_in, RubyRequest) {
+        L1DcacheMemory.profileMiss(in_msg, CacheAccessType:HIT);
     }
   }
 
   action(uu_profileDataMiss, "\ud", desc="Profile the demand miss") {
     peek(mandatoryQueue_in, RubyRequest) {
-        L1DcacheMemory.profileMiss(in_msg);
+        L1DcacheMemory.profileMiss(in_msg, CacheAccessType:MISS);
     }
   }
 
@@ -739,8 +751,15 @@
   }
 
   // Transitions from Shared
-  transition(S, {Load,Ifetch}) {
+  transition(S, Ifetch) {
     h_load_hit;
+    uu_profileInstHit;
+    k_popMandatoryQueue;
+  }
+
+  transition(S, Load) {
+    h_load_hit;
+    uu_profileDataHit;
     k_popMandatoryQueue;
   }
 
@@ -764,13 +783,21 @@
 
   // Transitions from Exclusive
 
-  transition(E, {Load, Ifetch}) {
+  transition(E, Ifetch) {
     h_load_hit;
+    uu_profileInstHit;
+    k_popMandatoryQueue;
+  }
+
+  transition(E, Load) {
+    h_load_hit;
+    uu_profileDataHit;
     k_popMandatoryQueue;
   }
 
   transition(E, Store, M) {
     hh_store_hit;
+    uu_profileDataHit;
     k_popMandatoryQueue;
   }
 
@@ -802,13 +829,21 @@
   }
 
   // Transitions from Modified
-  transition(M, {Load, Ifetch}) {
+  transition(M, Ifetch) {
     h_load_hit;
+    uu_profileInstHit;
+    k_popMandatoryQueue;
+  }
+
+  transition(M, Load) {
+    h_load_hit;
+    uu_profileDataHit;
     k_popMandatoryQueue;
   }
 
   transition(M, Store) {
     hh_store_hit;
+    uu_profileDataHit;
     k_popMandatoryQueue;
   }
 
diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
@@ -731,10 +731,19 @@
     }
   }
 
+  action(uu_profileHit, "\uH", desc="Profile the demand hit") {
+    peek(L1RequestIntraChipL2Network_in, RequestMsg) {
+      L2cacheMemory.profileGenericRequest(convertToGenericType(in_msg.Type),
+                                       in_msg.AccessMode, in_msg.Prefetch,
+                                       CacheAccessType:HIT);
+    }
+  }
+
   action(uu_profileMiss, "\u", desc="Profile the demand miss") {
     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
       L2cacheMemory.profileGenericRequest(convertToGenericType(in_msg.Type),
-                                       in_msg.AccessMode, in_msg.Prefetch);
+                                       in_msg.AccessMode, in_msg.Prefetch,
+				       CacheAccessType:MISS);
     }
   }
 
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -848,9 +848,27 @@
     }
   }
 
-  action(uu_profileMiss, "\u", desc="Profile the demand miss") {
+  action(uu_profileDataHit, "\uDH", desc="Profile the Data demand Access") {
     peek(mandatoryQueue_in, RubyRequest) {
-      //      profile_miss(in_msg);
+      L1DcacheMemory.profileMiss(in_msg, CacheAccessType:HIT);
+    }
+  }
+
+  action(uu_profileDataMiss, "\uDM", desc="Profile the Data demand Access") {
+    peek(mandatoryQueue_in, RubyRequest) {
+      L1DcacheMemory.profileMiss(in_msg, CacheAccessType:MISS);
+    }
+  }
+
+  action(uu_profileInstHit, "\uIH", desc="Profile the Inst demand Access") {
+    peek(mandatoryQueue_in, RubyRequest) {
+      L1IcacheMemory.profileMiss(in_msg, CacheAccessType:HIT);
+    }
+  }
+
+  action(uu_profileInstMiss, "\uIM", desc="Profile the Inst demand Access") {
+    peek(mandatoryQueue_in, RubyRequest) {
+      L1IcacheMemory.profileMiss(in_msg, CacheAccessType:MISS);
     }
   }
 
@@ -888,7 +906,7 @@
     ii_allocateL1DCacheBlock;
     i_allocateTBE;
     a_issueGETS;
-    // uu_profileMiss;
+    uu_profileDataMiss;
     k_popMandatoryQueue;
   }
 
@@ -896,7 +914,7 @@
     jj_allocateL1ICacheBlock;
     i_allocateTBE;
     a_issueGETS;
-    // uu_profileMiss;
+    uu_profileInstMiss;
     k_popMandatoryQueue;
   }
 
@@ -904,7 +922,7 @@
     ii_allocateL1DCacheBlock;
     i_allocateTBE;
     b_issueGETX;
-    // uu_profileMiss;
+    uu_profileDataMiss;
     k_popMandatoryQueue;
   }
 
@@ -920,13 +938,14 @@
   // Transitions from Shared
   transition({S, SM}, {Load, Ifetch}) {
     h_load_hit;
+    uu_profileDataHit;
     k_popMandatoryQueue;
   }
 
   transition(S, Store, SM) {
     i_allocateTBE;
     b_issueGETX;
-    // uu_profileMiss;
+    uu_profileDataMiss;
     k_popMandatoryQueue;
   }
 
@@ -955,15 +974,22 @@
   }
 
   // Transitions from Owned
-  transition({O, OM}, {Load, Ifetch}) {
+  transition({O, OM}, Ifetch) {
     h_load_hit;
+    uu_profileInstHit;
+    k_popMandatoryQueue;
+  }
+
+  transition({O, OM}, Load) {
+    h_load_hit;
+    uu_profileDataHit;
     k_popMandatoryQueue;
   }
 
   transition(O, Store, OM) {
     i_allocateTBE;
     b_issueGETX;
-    // uu_profileMiss;
+    uu_profileDataMiss;
     k_popMandatoryQueue;
   }
 
@@ -992,13 +1018,21 @@
   }
 
   // Transitions from MM
-  transition({MM, MM_W}, {Load, Ifetch}) {
+  transition({MM, MM_W}, Ifetch) {
     h_load_hit;
+    uu_profileInstHit;
+    k_popMandatoryQueue;
+  }
+
+  transition({MM, MM_W}, Load) {
+    h_load_hit;
+    uu_profileDataHit;
     k_popMandatoryQueue;
   }
 
   transition({MM, MM_W}, Store) {
     hh_store_hit;
+    uu_profileDataHit;
     k_popMandatoryQueue;
   }
 
@@ -1028,18 +1062,27 @@
   }
 
   // Transitions from M
-  transition({M, M_W}, {Load, Ifetch}) {
+  transition({M, M_W}, Ifetch) {
     h_load_hit;
+    uu_profileInstHit;
+    k_popMandatoryQueue;
+  }
+
+  transition({M, M_W}, Load) {
+    h_load_hit;
+    uu_profileDataHit;
     k_popMandatoryQueue;
   }
 
   transition(M, Store, MM) {
     hh_store_hit;
+    uu_profileDataHit;
     k_popMandatoryQueue;
   }
 
   transition(M_W, Store, MM_W) {
     hh_store_hit;
+    uu_profileDataHit;
     k_popMandatoryQueue;
   }
 
diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -531,6 +531,22 @@
     return getCacheEntry(addr).DataBlk;
   }
 
+
+  GenericRequestType convertToGenericType(CoherenceRequestType type) {
+    if(type == CoherenceRequestType:GETS) {
+      return GenericRequestType:GETS;
+    } else if(type == CoherenceRequestType:GETX) {
+      return GenericRequestType:GETX;
+    } else if(type == CoherenceRequestType:PUTX) {
+      return GenericRequestType:PUTX;
+    } else if(type == CoherenceRequestType:GETS) {
+      return GenericRequestType:GETS;
+    } else {
+      DPRINTF(RubySlicc, "%s\n", type);
+      error("Invalid CoherenceRequestType\n");
+    }
+  }
+
   MessageBuffer triggerQueue, ordered="true";
 
   out_port(globalRequestNetwork_out, RequestMsg, GlobalRequestFromL2Cache);
@@ -1476,8 +1492,15 @@
 
   action(uu_profileMiss, "\u", desc="Profile the demand miss") {
     peek(L1requestNetwork_in, RequestMsg) {
-      // AccessModeType not implemented
-      //      profile_L2Cache_miss(convertToGenericType(in_msg.Type), in_msg.AccessMode, MessageSizeTypeToInt(in_msg.MessageSize),  in_msg.Prefetch, machineIDToNodeID(in_msg.Requestor));
+      L2cacheMemory.profileGenericRequest(convertToGenericType(in_msg.Type),
+                                       in_msg.AccessMode, in_msg.Prefetch, CacheAccessType:MISS);
+    }
+  }
+
+  action(uu_profileHit, "\uh", desc="Profile the demand hit") {
+    peek(L1requestNetwork_in, RequestMsg) {
+      L2cacheMemory.profileGenericRequest(convertToGenericType(in_msg.Type),
+                                       in_msg.AccessMode, in_msg.Prefetch, CacheAccessType:HIT);
     }
   }
 
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/protocol/RubySlicc_Exports.sm
@@ -255,6 +255,12 @@
   L2_HW, desc="This is a L2 hardware prefetch";
 }
 
+// Cache Access Type
+enumeration(CacheAccessType, default="HIT", desc="...") {
+  HIT,  desc="demand hits";
+  MISS, desc="demand miss";
+}
+
 // CacheMsg
 structure(SequencerMsg, desc="...", interface="Message") {
   Address LineAddress,       desc="Line address for this request";
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -147,11 +147,12 @@
   void deallocate(Address);
   AbstractCacheEntry lookup(Address);
   bool isTagPresent(Address);
-  void profileMiss(RubyRequest);
+  void profileMiss(RubyRequest, CacheAccessType);
 
   void profileGenericRequest(GenericRequestType,
                              RubyAccessMode,
-                             PrefetchBit);
+                             PrefetchBit,
+			     CacheAccessType);
 
   void setMRU(Address);
   void recordRequestType(CacheRequestType);
diff --git a/src/mem/ruby/profiler/CacheProfiler.hh b/src/mem/ruby/profiler/CacheProfiler.hh
--- a/src/mem/ruby/profiler/CacheProfiler.hh
+++ b/src/mem/ruby/profiler/CacheProfiler.hh
@@ -33,6 +33,7 @@
 #include <string>
 #include <vector>
 
+#include "mem/protocol/CacheAccessType.hh"
 #include "mem/protocol/GenericRequestType.hh"
 #include "mem/protocol/PrefetchBit.hh"
 #include "mem/protocol/RubyAccessMode.hh"
@@ -51,11 +52,13 @@
 
     void addCacheStatSample(RubyRequestType requestType,
                             RubyAccessMode type,
-                            PrefetchBit pfBit);
+                            PrefetchBit pfBit,
+                            CacheAccessType cacheAccess);
 
     void addGenericStatSample(GenericRequestType requestType, 
                               RubyAccessMode type,
-                              PrefetchBit pfBit);
+                              PrefetchBit pfBit,
+                              CacheAccessType cacheAccess);
 
     void print(std::ostream& out) const;
 
@@ -63,9 +66,14 @@
     // Private copy constructor and assignment operator
     CacheProfiler(const CacheProfiler& obj);
     CacheProfiler& operator=(const CacheProfiler& obj);
-    void addStatSample(RubyAccessMode type, PrefetchBit pfBit);
+    void addStatSample(RubyAccessMode type, PrefetchBit pfBit,
+                       CacheAccessType cacheAccess);
 
     std::string m_description;
+    int64 m_accesses;
+    int64 m_demand_accesses;
+    int64 m_hits;
+    int64 m_demand_hits;
     int64 m_misses;
     int64 m_demand_misses;
     int64 m_prefetches;
diff --git a/src/mem/ruby/profiler/CacheProfiler.cc b/src/mem/ruby/profiler/CacheProfiler.cc
--- a/src/mem/ruby/profiler/CacheProfiler.cc
+++ b/src/mem/ruby/profiler/CacheProfiler.cc
@@ -50,11 +50,19 @@
     out << "Cache Stats: " << m_description << endl;
     string description = "  " + m_description;
 
+    out << description << "_total_accesses: " << m_accesses << endl;
+    out << description << "_total_demand_accesses: " << m_demand_accesses
+        << endl;
+    out << description << "_total_hits: " << m_hits << endl;
+    out << description << "_total_demand_hits: " << m_demand_hits << endl;
     out << description << "_total_misses: " << m_misses << endl;
     out << description << "_total_demand_misses: " << m_demand_misses << endl;
     out << description << "_total_prefetches: " << m_prefetches << endl;
     out << description << "_total_sw_prefetches: " << m_sw_prefetches << endl;
     out << description << "_total_hw_prefetches: " << m_hw_prefetches << endl;
+    out << description << "_miss_rate: " <<  100.0 * m_misses / m_accesses
+        << "%" << endl;
+    out << description << "_demand_miss_rate: " <<  100.0 * m_demand_misses / m_demand_accesses << "%" << endl;
     out << endl;
 
     int requests = 0;
@@ -67,7 +75,7 @@
         requests += m_genericRequestType[i];
     }
 
-    assert(m_misses == requests);
+    assert(m_accesses == requests);
 
     if (requests > 0) {
         for (int i = 0; i < int(RubyRequestType_NUM); i++) {
@@ -117,6 +125,10 @@
     for (int i = 0; i < int(GenericRequestType_NUM); i++) {
         m_genericRequestType[i] = 0;
     }
+    m_accesses = 0;
+    m_demand_accesses = 0;
+    m_hits = 0;
+    m_demand_hits = 0;
     m_misses = 0;
     m_demand_misses = 0;
     m_prefetches = 0;
@@ -130,33 +142,47 @@
 void
 CacheProfiler::addCacheStatSample(RubyRequestType requestType,
                                   RubyAccessMode accessType,
-                                  PrefetchBit pfBit)
+                                  PrefetchBit pfBit,
+                                  CacheAccessType cacheAccess)
 {
     m_cacheRequestType[requestType]++;
-    addStatSample(accessType, pfBit);
+    addStatSample(accessType, pfBit, cacheAccess);
 }
 
 void
 CacheProfiler::addGenericStatSample(GenericRequestType requestType,
                                     RubyAccessMode accessType,
-                                    PrefetchBit pfBit)
+                                    PrefetchBit pfBit,
+                                    CacheAccessType cacheAccess)
 {
     m_genericRequestType[requestType]++;
-    addStatSample(accessType, pfBit);
+    addStatSample(accessType, pfBit, cacheAccess);
 }
 
 void
 CacheProfiler::addStatSample(RubyAccessMode accessType,
-                             PrefetchBit pfBit)
+                             PrefetchBit pfBit,
+                             CacheAccessType cacheAccess)
 {
-    m_misses++;
+    m_accesses++;
 
     m_accessModeTypeHistogram[accessType]++;
-    if (pfBit == PrefetchBit_No) {
+    if(pfBit == PrefetchBit_No && cacheAccess == CacheAccessType_MISS) {
+        m_demand_accesses++;
         m_demand_misses++;
-    } else if (pfBit == PrefetchBit_Yes) {
+        m_misses++;
+    } else if(pfBit == PrefetchBit_No && cacheAccess == CacheAccessType_HIT) {
+       m_demand_accesses++;
+       m_demand_hits++;
+       m_hits++;
+    } else if(pfBit == PrefetchBit_Yes && cacheAccess == CacheAccessType_MISS) {
+        m_misses++;
         m_prefetches++;
         m_sw_prefetches++;
+    } else if (pfBit == PrefetchBit_Yes && cacheAccess == CacheAccessType_HIT) {
+      m_hits++;
+      m_prefetches++;
+      m_sw_prefetches++;
     } else {
         // must be L1_HW || L2_HW prefetch
         m_prefetches++;
diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -34,6 +34,7 @@
 
 #include "base/hashmap.hh"
 #include "base/statistics.hh"
+#include "mem/protocol/CacheAccessType.hh"
 #include "mem/protocol/CacheResourceType.hh"
 #include "mem/protocol/CacheRequestType.hh"
 #include "mem/protocol/GenericRequestType.hh"
@@ -100,11 +101,12 @@
     // Set this address to most recently used
     void setMRU(const Address& address);
 
-    void profileMiss(const RubyRequest & msg);
+    void profileMiss(const RubyRequest & msg, CacheAccessType cacheAccess);
 
     void profileGenericRequest(GenericRequestType requestType,
                                RubyAccessMode accessType,
-                               PrefetchBit pfBit);
+                               PrefetchBit pfBit,
+                               CacheAccessType cacheAccess);
 
     void setLocked (const Address& addr, int context);
     void clearLocked (const Address& addr);
diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc
--- a/src/mem/ruby/system/CacheMemory.cc
+++ b/src/mem/ruby/system/CacheMemory.cc
@@ -325,21 +325,24 @@
 }
 
 void
-CacheMemory::profileMiss(const RubyRequest& msg)
+CacheMemory::profileMiss(const RubyRequest& msg, CacheAccessType cacheAccess)
 {
     m_profiler_ptr->addCacheStatSample(msg.getType(), 
                                        msg.getAccessMode(),
-                                       msg.getPrefetch());
+                                       msg.getPrefetch(),
+                                       cacheAccess);
 }
 
 void
 CacheMemory::profileGenericRequest(GenericRequestType requestType,
                                    RubyAccessMode accessType,
-                                   PrefetchBit pfBit)
+                                   PrefetchBit pfBit,
+                                   CacheAccessType cacheAccess)
 {
     m_profiler_ptr->addGenericStatSample(requestType, 
                                          accessType, 
-                                         pfBit);
+                                         pfBit,
+                                         cacheAccess);
 }
 
 void