diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -260,9 +260,6 @@
     /** The number of misses to trigger an exit event. */
     Counter missCount;
 
-    /** The drain event. */
-    Event *drainEvent;
-
     /**
      * The address range to which the cache responds on the CPU side.
      * Normally this is all possible memory addresses. */
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -76,7 +76,6 @@
       blocked(0),
       noTargetMSHR(NULL),
       missCount(p->max_miss_count),
-      drainEvent(NULL),
       addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
       system(p->system)
 {
@@ -750,8 +749,6 @@
 
     // Set status
     if (count != 0) {
-        drainEvent = de;
-
         changeState(SimObject::Draining);
         DPRINTF(Drain, "Cache not drained\n");
         return count;