diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/SConscript --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/SConscript Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,58 @@ +# -*- mode:python -*- + +# Copyright (c) 2004-2005 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black +# Steve Reinhardt + +Import('*') + +if env['TARGET_ISA'] == 'trips': + Source('isa.cc') + Source('regredir.cc') + Source('tlb.cc') + Source('utility.cc') + #Source('stacktrace.cc') + #Source('vtophys.cc') + Source('faults.cc') + Source('pagetable.cc') + + TraceFlag('TripsFault'); + + SimObject('TripsTLB.py') + + Source('process.cc') + + Source('linux/linux.cc') + Source('linux/process.cc') + + # Add in files generated by the ISA description. + isa_desc_files = env.ISADesc('isa/main.isa') + # Only non-header files need to be compiled. + for f in isa_desc_files: + if not f.path.endswith('.hh'): + Source(f) diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/SConsopts --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/SConsopts Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,33 @@ +# -*- mode:python -*- + +# Copyright (c) 2004-2005 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +Import('*') + +all_isa_list.append('trips') diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/TripsTLB.py --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/TripsTLB.py Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,43 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * + +from BaseTLB import BaseTLB + +class TripsTLB(BaseTLB): + type = 'TripsTLB' + cxx_class = 'TripsISA::TLB' + size = Param.Int("TLB size") + +class TripsDTB(TripsTLB): + size = 64 + +class TripsITB(TripsTLB): + size = 48 diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/constants.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/constants.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __ARCH_TRIPS_CONST_HH__ +#define __ARCH_TRIPS_CONST_HH__ + +#include "base/bitunion.hh" + +namespace TripsISA { + BitUnion16(ConsumerBitfield) + Bitfield<8, 7> type; + Bitfield<6, 5> subtype; + Bitfield<6, 0> id; + Bitfield<4, 0> write_id; + EndBitUnion(ConsumerBitfield) + +}//_ARCH_TRIPS_CONST_HH + +#endif + diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/faults.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/faults.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + * Kevin Lim + */ + +#ifndef __ARCH_TRIPS_FAULTS_HH__ +#define __ARCH_TRIPS_FAULTS_HH__ + +#include "arch/trips/pagetable.hh" +#include "config/full_system.hh" +#include "sim/faults.hh" + +// The design of the "name" and "vect" functions is in sim/faults.hh + +namespace TripsISA { + +typedef const Addr FaultVect; + +class TripsFault : public FaultBase +{ + protected: + virtual bool skipFaultingInstruction() {return false;} + virtual bool setRestartAddress() {return true;} + public: + virtual void invoke(ThreadContext * tc); +private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; + public: + FaultName name() const {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} + bool isTripsFault() {return true;} +}; + +class TripsSyscallFault : public TripsFault +{ + public: + void invoke(ThreadContext * tc); +private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; + public: + FaultName name() const {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} + + void returnFromSyscall(ThreadContext * tc ); + + bool isTripsSyscallFault() {return true;} +}; + +static inline Fault genMachineCheckFault() +{ + return new TripsFault; +} + +static inline Fault genSyscallFault() +{ + return new TripsSyscallFault; +} + +} // namespace TripsISA + +#endif // __ARCH_TRIPS_FAULTS_HH__ diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/faults.cc --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/faults.cc Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + * Kevin Lim + */ + +#include "arch/trips/faults.hh" +#include "arch/trips/tlb.hh" +#include "cpu/thread_context.hh" +#include "cpu/base.hh" +#include "base/trace.hh" +#if !FULL_SYSTEM +#include "sim/process.hh" +#include "mem/page_table.hh" +#endif + +namespace TripsISA { +FaultName TripsFault::_name = "Trips fault"; +FaultVect TripsFault::_vect = 0x0; // No handler vector in SE mode +FaultStat TripsFault::_count; + +FaultName TripsSyscallFault::_name = "Trips syscall fault"; +FaultVect TripsSyscallFault::_vect = 0x0; // No handler vector in SE mode +FaultStat TripsSyscallFault::_count; + +#if !FULL_SYSTEM + + +void +TripsFault::invoke(ThreadContext * tc) { + DPRINTF (TripsFault, "Invoking fault\n" ); + panic("Trips fault unimplemented.\n"); +} + +void +TripsSyscallFault::returnFromSyscall(ThreadContext * tc ) { + // For trips syscall, PC after syscall will be redirect according to + // global regfile r2 + + IntReg reg = tc->readIntReg( ReturnAddressReg ); + + DPRINTF (TripsFault, "Trips syscall fault return, return address is %#x\n", reg ); + + tc->setBlockPC( reg ); +} + +void +TripsSyscallFault::invoke(ThreadContext * tc ) { + + IntReg callnum = tc->readIntReg( SyscallNumReg ); + DPRINTF(TripsFault, "Invoking trips syscall fault, call number %i\n", callnum); + tc->syscall(callnum); + returnFromSyscall(tc); +} + +#endif + + +} // namespace TripsISA + diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2009 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_TRIPS_ISA_HH__ +#define __ARCH_TRIPS_ISA_HH__ + +#include +#include + +#include "arch/trips/registers.hh" +#include "arch/trips/types.hh" +#include "base/types.hh" + +class BaseCPU; +class Checkpoint; +class EventManager; +class ThreadContext; + +namespace TripsISA +{ + class ISA + { + public: + typedef uint64_t InternalProcReg; + + protected: + uint64_t fpcr; // floating point condition codes + uint64_t uniq; // process-unique register + bool lock_flag; // lock flag for LL/SC + Addr lock_addr; // lock address for LL/SC + int intr_flag; + + InternalProcReg ipr[1]; // Fix me + + protected: + InternalProcReg readIpr(int idx, ThreadContext *tc); + void setIpr(int idx, InternalProcReg val, ThreadContext *tc); + + public: + + MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0); + MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); + + void setMiscRegNoEffect(int misc_reg, const MiscReg &val, + ThreadID tid = 0); + void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, + ThreadID tid = 0); + + void + clear() + { + fpcr = 0; + uniq = 0; + lock_flag = 0; + lock_addr = 0; + intr_flag = 0; + } + + void serialize(EventManager *em, std::ostream &os); + void unserialize(EventManager *em, Checkpoint *cp, + const std::string §ion); + + void reset(std::string core_name, ThreadID num_threads, + unsigned num_vpes, BaseCPU *_cpu) + { } + + + void expandForMultithreading(ThreadID num_threads, unsigned num_vpes) + { } + + int + flattenIntIndex(int reg) + { + return reg; + } + + int + flattenFloatIndex(int reg) + { + return reg; + } + + ISA() + { + clear(); + } + }; +} + +#endif diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa.cc --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa.cc Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2009 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/trips/isa.hh" +#include "base/misc.hh" +#include "cpu/thread_context.hh" + +namespace TripsISA +{ + +void +ISA::serialize(EventManager *em, std::ostream &os) +{ + SERIALIZE_SCALAR(fpcr); + SERIALIZE_SCALAR(uniq); + SERIALIZE_SCALAR(lock_flag); + SERIALIZE_SCALAR(lock_addr); +} + +void +ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion) +{ + UNSERIALIZE_SCALAR(fpcr); + UNSERIALIZE_SCALAR(uniq); + UNSERIALIZE_SCALAR(lock_flag); + UNSERIALIZE_SCALAR(lock_addr); +} + + +MiscReg +ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) +{ + panic("ISA::readMiscRegNoEffect unimplemented yet!\n"); +} + +MiscReg +ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) +{ + panic("ISA::readMiscReg unimplemented yet!\n"); +} + +void +ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) +{ + panic("ISA::setMiscRegNoEffect unimplemented yet!\n"); +} + +void +ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, + ThreadID tid) +{ + panic("ISA::setMiscReg unimplemented yet!\n"); +} + +} diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa/base.isa --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa/base.isa Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,123 @@ +// -*- mode:c++ -*- +// +// 2009-2010 HIT Microelectronic center all rights reserved +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Date: Dec. 2009 +// Authors: Gou Pengfei + +//////////////////////////////////////////////////////////////////// +// +// Base class for TRIPS instructions, and some support functions +// + +//Outputs to decoder.hh +output header {{ + + using namespace TripsISA; + + /** + * Base class for all TRIPS static instructions. + */ + class TRIPSStaticInst : public EDGEStaticInst + { + protected: + + // Constructor + TRIPSStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass) + : EDGEStaticInst(mnem, _machInst, __opClass) + { + } + + /// + void printConsumer(std::ostream &os, int id) const; + std::string printConsumer(int id) const; + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; + +}}; + +//Ouputs to decoder.cc +output decoder {{ + + void TRIPSStaticInst::printConsumer(std::ostream &os, int id) const + { + uint32_t slot = bits(_consumerID[id], 8, 7); + + ccprintf(os, "t%d", id); + if ( slot == 0 && bits(_consumerID[id], 6, 5) == 1) + ccprintf(os, "[w%d] ", bits(_consumerID[id], 4, 0 )); + else + ccprintf(os, "[%d,", bits(_consumerID[id], 6, 0 )); + if ( slot == 1 ) ccprintf(os, "p] "); + else if ( slot == 2 ) ccprintf(os, "op0] "); + else if ( slot == 3 ) ccprintf(os, "op1] "); + else + ccprintf(os, "0] "); + } + + std::string TRIPSStaticInst::printConsumer( int id) const + { + std::stringstream ss; + + uint32_t slot = bits(_consumerID[id], 8, 7); + + ccprintf(ss, "t%d", id); + if ( slot == 0 && bits(_consumerID[id], 6, 5) == 1) + ccprintf(ss, "[w%d] ", bits(_consumerID[id], 4, 0 )); + else + ccprintf(ss, "[%d,", bits(_consumerID[id], 6, 0 )); + if ( slot == 1 ) ccprintf(ss, "p] "); + else if ( slot == 2 ) ccprintf(ss, "op0] "); + else if ( slot == 3 ) ccprintf(ss, "op1] "); + else + ccprintf(ss, "0] "); + return ss.str(); + } + + std::string TRIPSStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + std::stringstream ss; + + ccprintf(ss, "%-10s ", mnemonic); + + if (strcmp(mnemonic, "syscall") != 0) { + + if(_numConsumers > 0) { + printConsumer(ss, 0); + } + + if(_numConsumers > 1) { + ss << ", "; + printConsumer(ss, 1); + } + } + + return ss.str(); + } + +}}; + diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa/bitfields.isa --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa/bitfields.isa Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,67 @@ +// -*- mode:c++ -*- +// +// 2009-2010 HIT Microelectronic Center all rights reserved +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Date: Dec. 2009 +// Authors: Gou pengfei + +//////////////////////////////////////////////////////////////////// +// +// Bitfield definitions of TRIPS ISA. +// For more details please refer to TRIPS processor reference +// + +def bitfield OPCODE <31:25>; // OP +def bitfield XOPCODE <22:18>; // XOP +def bitfield LSID <22:18>; // LSID for load/store inst. +def bitfield PR <24:23>; // Predication bits. +def bitfield EXIT <22:20>; // EXIT for branch inst. + +def bitfield T0 <8:0>; // ID of consumer 0 +def bitfield T1 <17:9>; // ID of consumer 1 +def bitfield IMM <17:9>; // Instants + +def bitfield BRANCH_OFFSET <19:0>; // Branch target offset of branch inst. +def bitfield CONSTANT <24:9>; // Constant for const inst. +def bitfield M3TX <22:21>; // M3TX for move3 inst., providing upper 2 bits of the three move targets +def bitfield M3T0 <20:14>; // M3T0 for move3 inst. +def bitfield M3T1 <13:7>; // M3T1 for move3 inst. +def bitfield M3T2 <6:0>; // M3T2 for move3 inst. +def bitfield M4TX <23:20>; // M4TX for move4 inst., providing upper 4 bits of the four move targets +def bitfield M4T0 <19:15>; // M4T0 for move4 inst. +def bitfield M4T1 <14:10>; // M4T1 for move4 inst. +def bitfield M4T2 <9:5>; // M4T2 for move4 inst. +def bitfield M4T3 <4:0>; // M4T3 for move4 inst. + +def bitfield HEAD_NIBBLE<31:28>; // Nibble bit for header chunk +def bitfield HEAD_BODY<27:0>; // Body bit for header chunk +def bitfield V_R <27>; // Valid bit for read inst. +def bitfield GR_R <26:22>; // General register ID for read inst. +def bitfield T0_R <21:14>; // Consumer 0 for read inst. +def bitfield T1_R <13:6>; // Consumer 1 for read inst. +def bitfield V_W <5>; // Valid bit for write inst. +def bitfield GR_W <4:0>; // General register ID for write inst. + diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa/decoder.isa --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa/decoder.isa Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,253 @@ +// -*- mode:c++ -*- +// +// 2009-2010 HIT Microelectronic Center all rights reserved +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// +// Date: Dec. 2009 +// Authors: Gou Pengfei + +decode BLOCKSTATUS default Unknown::unknown() { + +format WROp{ +0x0: write_read ({{ + if ( !write_true ) + RESULT.ud = Gr_r.ud; + else + Gr_w.ud = Op0.ud; + + }}, IsGRegWR); +} + +0x1: decode OPCODE default Unknown::unknown() { + format COp { + 0x0: nop ({{ }}, IsNop); + 0x1: gens ({{RESULT.sd = sext<16>(CONSTANT);}}); + 0x2: genu ({{RESULT.ud = CONSTANT;}}); + 0x4: app ({{RESULT.ud = (Op0.ud << 16) | CONSTANT;}}); + } + + format M3Op { + 0x6: m3 ({{RESULT.ud = Op0.ud;}}, IsMove); + } + + format M4Op { + 0x7: m4 ({{RESULT.ud = Op0.ud;}}, IsMove); + } + + format BwithOffset { + 0x8: bro ({{NextBlockPC = xc->getBlockPC() + (sext<20>(BRANCH_OFFSET) << 7);}}); + 0x9: callo ({{NextBlockPC = xc->getBlockPC() + (sext<20>(BRANCH_OFFSET) << 7);}}, IsCall); + } + + + + format syscall { + 0xa: scall ({{xc->setFault(NoFault);}}, IsSyscall); // Set fault as NoFault because syscall will be handled in execute stage , not in this inst + } + + format BwithoutOffset{ + 0xc: br ({{NextBlockPC = Op0.ud;}}); + 0xd: call ({{NextBlockPC = Op0.ud;}}, IsCall); + 0xe: ret ({{NextBlockPC = Op0.ud;}}, IsReturn); + } + + 0x10: decode XOPCODE { + format GOp { + 0x0: nullify ({{ + xc->setDataflowTokenType( TheISA::Nullification ); + xc->setIntResult(0); // Set it for consistency + }}); + } + } + + 0x12: decode XOPCODE { + format GOp { + 0x0: fitod ({{FRESULT.df = static_cast(Op0.sd);}}); + 0x1: fdtoi ({{RESULT.sd = static_cast(FOp0.df);}}); + 0x2: fstod ({{FRESULT.df = static_cast(FOp0.sf);}}); + 0x3: fdtos ({{FRESULT.sf = static_cast(FOp0.df);}}); + } + } + + 0x13: decode XOPCODE { + format GOp { + 0x0: mov ({{RESULT.ud = Op0.ud;}}); + 0x1: extsb ({{RESULT.sd = sext<8>(bits(Op0.ud,7, 0));}}); + 0x2: extsh ({{RESULT.sd = sext<16>(bits(Op0.ud, 15, 0));}}); + 0x3: extsw ({{RESULT.sd = sext<32>(bits(Op0.ud, 31, 0));}}); + 0x4: extub ({{RESULT.ud = bits(Op0.ud, 7, 0);}}); + 0x5: extuh ({{RESULT.ud = bits(Op0.ud, 15, 0);}}); + 0x6: extuw ({{RESULT.ud = bits(Op0.ud, 31, 0);}}); + } + } + + 0x16: decode XOPCODE { + format GOp { + 0x0: fadd ({{FRESULT.df = FOp0.df + FOp1.df;}}); + 0x1: fsub ({{FRESULT.df = FOp0.df - FOp1.df;}}); + 0x2: fmul ({{FRESULT.df = FOp0.df * FOp1.df;}}, FloatMultOp); + 0x3: fdiv ({{ + double temp = FOp1.df; + if ( temp == 0 ){ + warn("Dividing zero.\n"); + FRESULT.df = 0; + } else { + FRESULT.df = FOp0.df / temp; + } + }}, FloatDivOp); + 0x4: feq ({{RESULT.ud = (FOp0.df == FOp1.df) ? 1 : 0;}}); + 0x5: fle ({{RESULT.ud = (FOp0.df <= FOp1.df) ? 1 : 0;}}); + 0x6: flt ({{RESULT.ud = (FOp0.df < FOp1.df) ? 1 : 0;}}); + 0x7: fne ({{RESULT.ud = (FOp0.df != FOp1.df) ? 1 : 0;}}); + 0x8: fgt ({{RESULT.ud = (FOp0.df > FOp1.df) ? 1: 0;}}); + 0x9: fge ({{RESULT.ud = (FOp0.df >= FOp1.df) ? 1 : 0;}}); + } + } + + 0x17: decode XOPCODE { + format GOp { + 0x0: add ({{RESULT.ud = Op0.ud + Op1.ud;}}); + 0x1: sub ({{RESULT.ud = Op0.ud - Op1.ud;}}); + 0x2: mul ({{RESULT.ud = Op0.ud * Op1.ud;}}, IntMultOp); + 0x3: divs ({{ + int64_t temp = Op1.sd; + if ( temp == 0 ){ + warn("Dividing zero.\n"); + RESULT.sd = 0; + } else { + RESULT.sd = Op0.sd / temp; + } + }}, IntDivOp); + 0x4: divu ({{ + uint64_t temp = Op1.ud; + if ( temp == 0 ){ + warn("Dividing zero.\n"); + RESULT.ud = 0; + } else { + RESULT.ud = Op0.ud / temp; + } + }}, IntDivOp); + + 0x8: and ({{RESULT.ud = Op0.ud & Op1.ud;}}); + 0x9: or ({{RESULT.ud = Op0.ud | Op1.ud;}}); + 0xa: xor ({{RESULT.ud = Op0.ud ^ Op1.ud;}}); + + 0xc: sll ({{RESULT.ud = Op0.ud << ((Op1.ud)&0x3f);}}); + 0xd: srl ({{RESULT.ud = Op0.ud >> ((Op1.ud)&0x3f);}}); + 0xe: sra ({{RESULT.sd = Op0.sd >> ((Op1.ud)&0x3f);}}); // Is this safe enough? Maybe we should take a more safe sign handling method + + 0x10: teq ({{RESULT.ud = (Op0.ud == Op1.ud) ? 1 : 0;}}); + 0x11: tle ({{RESULT.ud = (Op0.sd <= Op1.sd) ? 1 : 0;}}); + 0x12: tlt ({{RESULT.ud = (Op0.sd < Op1.sd) ? 1 : 0;}}); + 0x13: tleu ({{RESULT.ud = (Op0.ud <= Op1.ud) ? 1 : 0;}}); + 0x14: tltu ({{RESULT.ud = (Op0.ud < Op1.ud) ? 1 : 0;}}); + 0x15: tne ({{RESULT.ud = (Op0.ud != Op1.ud) ? 1 : 0;}}); + 0x16: tgt ({{RESULT.ud = (Op0.sd > Op1.sd) ? 1 : 0;}}); + 0x17: tge ({{RESULT.ud = (Op0.sd >= Op1.sd) ? 1 : 0;}}); + 0x18: tgtu ({{RESULT.ud = (Op0.ud > Op1.ud) ? 1 : 0;}}); + 0x19: tgeu ({{RESULT.ud = (Op0.ud >= Op1.ud) ? 1 : 0;}}); + + } + } + + 0x18: decode XOPCODE { + format IOp { + 0x0: movi ({{RESULT.sd = sext<9>(IMM);}}); + 0x1: mfpc ({{RESULT.ud = xc->readPC();}}); + } + } + + 0x1f: decode XOPCODE { + format IOp { + 0x0: addi ({{RESULT.ud = Op0.ud + sext<9>(IMM);}}); + 0x1: subi ({{RESULT.ud = Op0.ud - sext<9>(IMM);}}); + 0x2: muli ({{RESULT.ud = Op0.ud * sext<9>(IMM);}}, IntMultOp); + 0x3: divsi ({{ + int64_t temp = sext<9>(IMM); + if ( temp == 0 ){ + warn("Dividing zero.\n"); + RESULT.sd = 0; + }else{ + RESULT.sd = Op0.sd / temp; + } + }}, IntDivOp); + 0x4: divui ({{ + uint64_t temp = static_cast(sext<9>(IMM)); + if ( temp == 0 ){ + warn("Dividing zero.\n"); + RESULT.ud = 0; + }else{ + RESULT.ud = Op0.ud / temp; + } + }}, IntDivOp); + + 0x8: andi ({{RESULT.ud = Op0.ud & sext<9>(IMM);}}); + 0x9: ori ({{RESULT.ud = Op0.ud | sext<9>(IMM);}}); + 0xa: xori ({{RESULT.ud = Op0.ud ^ sext<9>(IMM);}}); + + 0xc: slli ({{RESULT.ud = Op0.ud << ((sext<9>(IMM))&0x3f);}}); + 0xd: srli ({{RESULT.ud = Op0.ud >> ((sext<9>(IMM))&0x3f);}}); + 0xe: srai ({{RESULT.sd = Op0.sd >> ((sext<9>(IMM))&0x3f);}}); // Is this safe enough? Maybe we should take a more safe sign handling method + + 0x10: teqi ({{RESULT.ud = (Op0.sd == sext<9>(IMM)) ? 1 : 0;}}); + 0x11: tlei ({{RESULT.ud = (Op0.sd <= sext<9>(IMM)) ? 1 : 0;}}); + 0x12: tlti ({{RESULT.ud = (Op0.sd < sext<9>(IMM)) ? 1 : 0;}}); + 0x13: tleui ({{RESULT.ud = (Op0.ud <= static_cast(sext<9>(IMM))) ? 1 : 0;}}); + 0x14: tltui ({{RESULT.ud = (Op0.ud < static_cast(sext<9>(IMM))) ? 1 : 0;}}); + 0x15: tnei ({{RESULT.ud = (Op0.ud != sext<9>(IMM)) ? 1 : 0;}}); + 0x16: tgti ({{RESULT.ud = (Op0.sd > sext<9>(IMM)) ? 1 : 0;}}); + 0x17: tgei ({{RESULT.ud = (Op0.sd >= sext<9>(IMM)) ? 1 : 0;}}); + 0x18: tgtui ({{RESULT.ud = (Op0.ud > static_cast(sext<9>(IMM))) ? 1 : 0;}}); + 0x19: tgeui ({{RESULT.ud = (Op0.ud >= static_cast(sext<9>(IMM))) ? 1 : 0;}}); + + } + } + + format LoadMemory { + 0x20: lb ({{RESULT.ub = Mem.ub;}}, mem_flags=NO_ALIGN_FAULT); + 0x21: lh ({{RESULT.uh = Mem.uh;}}, mem_flags=NO_HALF_WORD_ALIGN_FAULT ); + 0x22: lw ({{RESULT.uw = Mem.uw;}}); + 0x23: ld ({{RESULT.ud = Mem.ud;}}); + 0x24: lbs ({{RESULT.sb = Mem.sb;}}, mem_flags=NO_ALIGN_FAULT); + 0x25: lhs ({{RESULT.sh = Mem.sh;}}, mem_flags=NO_HALF_WORD_ALIGN_FAULT); + 0x26: lws ({{RESULT.sw = Mem.sw;}}); + 0x27: lock ({{RESULT.ud = Mem.ub; }}, mem_flags=LLSC); //What mem_flags should this inst have? Actually, i need fix this instruction due to the syn operation it needs... In arca, the swap inst that a bit like this is a really dirty implemtation... + } + + format StoreMemory { + 0x28: sb ({{Mem.ub = Op1.ub;}}, mem_flags=NO_ALIGN_FAULT); + 0x29: sh ({{Mem.uh = Op1.uh;}}, mem_flags=NO_HALF_WORD_ALIGN_FAULT); + 0x2a: sw ({{Mem.uw = Op1.uw;}}); + 0x2b: sd ({{Mem.ud = Op1.ud;}}); + } + + +} + +} + + + diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa/formats/b.isa --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa/formats/b.isa Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,227 @@ +// -*- mode:c++ -*- +// +// 2009-2010 HIT Microelectronic Center all rights reserved +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// +// Date: Dec. 2009 +// Authors: Gou Pengfei + +output header {{ + +#include + using namespace std; + + /** + * Base class for instructions whose disassembly is not purely a + * function of the machine instruction (i.e., it depends on the + * PC). This class overrides the disassemble() method to check + * the PC and symbol table values before re-using a cached + * disassembly string. This is necessary for branches and jumps, + * where the disassembly string includes the target address (which + * may depend on the PC and/or symbol table). + */ + class PCDependentDisassembly : public TRIPSStaticInst + { + protected: + /// Cached program counter from last disassembly + mutable Addr cachedPC; + + /// Cached symbol table pointer from last disassembly + mutable const SymbolTable *cachedSymtab; + + /// Constructor + PCDependentDisassembly(const char *mnem, MachInst _machInst, + OpClass __opClass) + : TRIPSStaticInst(mnem, _machInst, __opClass), + cachedPC(0), cachedSymtab(0) + { + } + + const std::string & + disassemble(Addr pc, const SymbolTable *symtab) const; + }; + + /** + * Base class for branches or calls (PC-relative control transfers) in TRIPS + * PC in TRIPS ISA representes the block address which must be 128-bytes aligned. + */ + class BwithOffset : public PCDependentDisassembly + { + protected: + /// target address (signed) Displacement . + int64_t _offset; + + /// predication bit + uint8_t pr; + + /// Constructor. + BwithOffset(const char *mnem, MachInst _machInst, OpClass __opClass) + : PCDependentDisassembly(mnem, _machInst, __opClass), + _offset(sext<20>(BRANCH_OFFSET) << 7 ), pr(PR) + { + // Init _exitID + _exitID =EXIT; + switch(pr){ + case 0x0:_predication = Disable;break; + case 0x2:_predication = PredUponFalse;break; + case 0x3:_predication = PredUponTrue;break; + default: _predication = Reserved; + } + } + + Addr branchTarget(ThreadContext *tc) const; + + std::string + generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; + + /** + * Base class for jumps (register-indirect control transfers). In + * the Mips ISA, these are always unconditional. + */ + class BwithoutOffset : public PCDependentDisassembly + { + protected: + + /// predication bit + uint8_t pr; + + public: + /// Constructor + BwithoutOffset(const char *mnem, MachInst _machInst, OpClass __opClass) + : PCDependentDisassembly(mnem, _machInst, __opClass), pr(PR) + { + // Init _exitID + _exitID = EXIT; + switch(pr){ + case 0x0:_predication = Disable;break; + case 0x2:_predication = PredUponFalse;break; + case 0x3:_predication = PredUponTrue;break; + default: _predication = Reserved; + } + } + + Addr branchTarget() const; + + std::string + generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + Addr + BwithOffset::branchTarget(ThreadContext *tc) const + { + Addr NextBlockPC = tc->getBlockPC(); + return NextBlockPC + _offset; + } + + const std::string & + PCDependentDisassembly::disassemble(Addr pc, + const SymbolTable *symtab) const + { + if (!cachedDisassembly || + pc != cachedPC || symtab != cachedSymtab) + { + if (cachedDisassembly) + delete cachedDisassembly; + + cachedDisassembly = + new std::string(generateDisassembly(pc, symtab)); + cachedPC = pc; + cachedSymtab = symtab; + } + + return *cachedDisassembly; + } + + std::string + BwithOffset::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + std::stringstream ss; + + ccprintf(ss, "%-10s ", mnemonic); + + ss<<""; + ccprintf(ss, "PR[%d]", pr); + ss<<","; + ccprintf(ss, "EXIT[%d]", _exitID); + + Addr target = pc + _offset; + + std::string str; + if (symtab && symtab->findSymbol(target, str)) + ss << str; + else + ccprintf(ss, "0x%x", target); + + return ss.str(); + } + + std::string + BwithoutOffset::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + std::stringstream ss; + + ccprintf(ss, "%-10s ", mnemonic); + + ss<<""; + ccprintf(ss, "PR[%d] ", pr); + ss<<","; + ccprintf(ss, "EXIT[%d] ", _exitID);; + + ccprintf(ss, "target[Op0]"); + + return ss.str(); + } +}}; + +def format BwithOffset(code, *opt_flags) {{ + opt_flags+=('IQOPerands', 'IsEDGE', 'IsControl',{'numConsumer':0},) + iop = InstObjParams(name, Name, 'BwithOffset', code, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; + +def format BwithoutOffset(code, *opt_flags) {{ + opt_flags+=('IQOPerands', 'IsEDGE', 'IsControl',{'numConsumer':0},) + iop = InstObjParams(name, Name, 'BwithoutOffset', code, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; + +def format syscall(code, *opt_flags) {{ + opt_flags+=('IsEDGE', 'IsControl','IQOPerands', {'numConsumer':0},) + iop = InstObjParams(name, Name, 'BwithoutOffset', code, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; \ No newline at end of file diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa/formats/basic.isa --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa/formats/basic.isa Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,96 @@ +// -*- mode:c++ -*- +// +// 2009-2010 HIT Microelectronic Center all rights reserved +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// +// Date: Dec. 2009 +// Authors: Gou Pengfei + +// Declarations for execute() methods. +def template BasicExecDeclare {{ + Fault execute(%(CPU_exec_context)s *, Trace::EdgeInstRecord *) const; +}}; + +// Basic instruction class declaration template. +def template BasicDeclare {{ + /** + * Static instruction class for "%(mnemonic)s". + */ + class %(class_name)s : public %(base_class)s + { + public: + /// Constructor. + %(class_name)s(MachInst machInst); + %(BasicExecDeclare)s + }; +}}; + +// Basic instruction class constructor template. +def template BasicConstructor {{ + inline %(class_name)s::%(class_name)s(MachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) + { + %(constructor)s; + } +}}; + + +// Basic instruction class execute method template. +def template BasicExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::EdgeInstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + if(fault == NoFault) + { + %(code)s; + if(fault == NoFault){ + %(op_wb)s; + } + } + return fault; + } +}}; + +// Basic decode template. +def template BasicDecode {{ + return new %(class_name)s(machInst); +}}; + +// Basic decode template, passing mnemonic in as string arg to constructor. +def template BasicDecodeWithMnemonic {{ + return new %(class_name)s("%(mnemonic)s", machInst); +}}; + +// The most basic instruction format... +def format BasicOp(code, *flags) {{ + iop = InstObjParams(name, Name, 'TRIPSStaticInst', code, flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa/formats/c.isa --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa/formats/c.isa Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,76 @@ +// -*- mode:c++ -*- +// +// 2009-2010 HIT Microelectronic Center all rights reserved +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// +// Date: Dec. 2009 +// Authors: Gou Pengfei + +output header {{ + class COp:public TRIPSStaticInst + { + protected: + + /// 16 bit constants + uint64_t _constant; + + /// Constructors for TRIPS G format instructions + COp(const char* mnem, MachInst _machInst, OpClass __opClass): + TRIPSStaticInst(mnem, _machInst, __opClass), _constant(CONSTANT) + { + _predication = Disable; + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symTab) const; + }; + +}}; + +output decoder {{ + std::string COp::generateDisassembly(Addr pc, const SymbolTable* symtab) const { + std::stringstream ss; + ccprintf(ss, "%-10s",mnemonic); + ccprintf(ss, " CONST(0x%x),", _constant); + ss<<","; + printConsumer(ss, 0); + return ss.str(); + } +}}; + +def format COp(code,*opt_flags) {{ + + # + # Please refer to g.isa for some cautions of the following statments + # + + opt_flags+=('IsEDGE','IQOPerands', {'numConsumer':1},) + iop = InstObjParams(name,Name,'COp',code,opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; + diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa/formats/formats.isa --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa/formats/formats.isa Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,49 @@ +// -*- mode:c++ -*- +// +// 2009-2010 HIT Microelectronic Center all rights reserved +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// +// Date: Dec. 2009 +// Authors: Gou Pengfei + +##include "basic.isa" + +##include "unknown.isa" + +##include "g.isa" + +##include "i.isa" + +##include "ls.isa" + +##include "b.isa" + +##include "c.isa" + +##include "m.isa" + +##include "wr.isa" + diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa/formats/g.isa --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa/formats/g.isa Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,92 @@ +// -*- mode:c++ -*- +// +// 2009-2010 HIT Microelectronic Center all rights reserved +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// +// Date: Dec. 2009 +// Authors: Gou Pengfei + +output header {{ + class GOp:public TRIPSStaticInst + { + protected: + + /// Predication bits + uint8_t pr; + + /// Constructors for TRIPS G format instructions + GOp(const char* mnem, MachInst _machInst, OpClass __opClass): + TRIPSStaticInst(mnem, _machInst, __opClass),pr(PR) + { + switch(pr){ + case 0x0:_predication = Disable;break; + case 0x2:_predication = PredUponFalse;break; + case 0x3:_predication = PredUponTrue;break; + default: _predication = Reserved; + } + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symTab) const; + }; + +}}; + +output decoder {{ + std::string GOp::generateDisassembly(Addr pc, const SymbolTable* symtab) const { + std::stringstream ss; + ccprintf(ss, "%-10s",mnemonic); + ss<<""; + ccprintf(ss, "PR[%d]", pr); + ss<<","; + printConsumer(ss, 0); + printConsumer(ss, 1); + return ss.str(); + } +}}; + +def format GOp(code,*opt_flags) {{ + + # + # The following opt_flags is necessary for TRIPS ISA among which + # 'IQOPerands' indicates the operands come from IQ rather than global regs, + # 'IsEDGE' indicates this is an instruction format for EDGE CPU model, + # and finally the dictionary structure indicates how many consumers this + # instruction format has. + # + # Caution: the dictionary struction must be put in the last of this opt_flags, + # if not, problems will be invoked from the isa_parser.py. + # + # If you do have questions about how this works, come and have a conversion with me. + # I'm Gou Pengfei, by the way. + # + + opt_flags+=('IQOPerands','IsEDGE',{'numConsumer':2},) + iop = InstObjParams(name,Name,'GOp',code,opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa/formats/i.isa --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa/formats/i.isa Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,80 @@ +// -*- mode:c++ -*- +// +// 2009-2010 HIT Microelectronic Center all rights reserved +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// +// Date: Dec. 2009 +// Authors: Gou Pengfei + +output header {{ + class IOp:public TRIPSStaticInst + { + protected: + + /// Predication bits + uint8_t pr; + + /// Constructors for TRIPS G format instructions + IOp(const char* mnem, MachInst _machInst, OpClass __opClass): + TRIPSStaticInst(mnem, _machInst, __opClass),pr(PR) + { + switch(pr){ + case 0x0:_predication = Disable;break; + case 0x2:_predication = PredUponFalse;break; + case 0x3:_predication = PredUponTrue;break; + default: _predication = Reserved; + } + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symTab) const; + }; + +}}; + +output decoder {{ + std::string IOp::generateDisassembly(Addr pc, const SymbolTable* symtab) const { + std::stringstream ss; + ccprintf(ss, "%-10s",mnemonic); + ss<<","; + printConsumer(ss, 0); + return ss.str(); + } +}}; + +def format IOp(code,*opt_flags) {{ + + # + # Please refer to g.isa for some cautions of the following statments + # + + opt_flags+=('IQOPerands','IsEDGE',{'numConsumer':1},) + iop = InstObjParams(name,Name,'IOp',code,opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; + diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa/formats/ls.isa --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa/formats/ls.isa Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,456 @@ +// -*- mode:c++ -*- +// +// 2009-2010 HIT Microelectronic Center all rights reserved +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// +// Date: Dec. 2009 +// Authors: Gou Pengfei + +//////////////////////////////////////////////////////////////////// +// +// Memory-format instructions of TRIPS +// + +output header {{ + + /** + * Base class for general TRIPS memory-format instructions. + */ + class Memory : public TRIPSStaticInst + { + protected: + /// Memory request flags. See mem/request.hh + Request::Flags memAccessFlags; + + /// offset of TRIPS memory access instructions + int64_t _offset; + + /// Predication bits + uint32_t pr; + + /// Constructor + Memory(const char *mnem, MachInst _machInst, OpClass __opClass) + : TRIPSStaticInst(mnem, _machInst, __opClass), + _offset(sext<9>(IMM)), pr(PR) + { + // Initial the _lsID; + _lsID = LSID; + switch(pr){ + case 0x0:_predication = Disable;break; + case 0x2:_predication = PredUponFalse;break; + case 0x3:_predication = PredUponTrue;break; + default: _predication = Reserved; + } + } + }; + + class Load : public Memory + { + protected: + + /// Constructor + Load(const char *mnem, MachInst _machInst, OpClass __opClass) + : Memory(mnem, _machInst, __opClass) + { + } + + std::string + generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; + + class Store : public Memory + { + protected: + + /// Constructor + Store(const char *mnem, MachInst _machInst, OpClass __opClass) + : Memory(mnem, _machInst, __opClass) + { + } + + std::string + generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; + +}}; + + +output decoder {{ + + std::string + Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return csprintf("%-10s lsid[%d], offset[0x%x], %s", mnemonic, _lsID, _offset, printConsumer(0)); + } + + std::string + Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return csprintf("%-10s lsid[%d], offset[0x%x]", mnemonic, _lsID, _offset); + } + +}}; + +output exec {{ + /** return data in cases where there the size of data is only + known in the packet + */ + uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet) { + switch (packet->getSize()) + { + case 1: + return packet->get(); + + case 2: + return packet->get(); + + case 4: + return packet->get(); + + case 8: + return packet->get(); + + default: + std::cerr << "bad store data size = " << packet->getSize() << std::endl; + + assert(0); + return 0; + } + } + + +}}; + +def template LoadStoreDeclare {{ + /** + * Static instruction class for "%(mnemonic)s". + */ + class %(class_name)s : public %(base_class)s + { + public: + + /// Constructor. + %(class_name)s(ExtMachInst machInst); + + %(BasicExecDeclare)s + + %(EACompDeclare)s + + %(InitiateAccDeclare)s + + %(CompleteAccDeclare)s + }; +}}; + +def template EACompDeclare {{ + Fault eaComp(%(CPU_exec_context)s *, Trace::EdgeInstRecord *) const; +}}; + +def template InitiateAccDeclare {{ + Fault initiateAcc(%(CPU_exec_context)s *, Trace::EdgeInstRecord *) const; +}}; + + +def template CompleteAccDeclare {{ + Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::EdgeInstRecord *) const; +}}; + +def template LoadStoreConstructor {{ + inline %(class_name)s::%(class_name)s(ExtMachInst machInst) + : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) + { + %(constructor)s; + } +}}; + + +def template EACompExecute {{ + Fault + %(class_name)s::eaComp(%(CPU_exec_context)s *xc, + Trace::EdgeInstRecord *traceData) const + { + Addr EA; + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + + // NOTE: Trace Data is written using execute or completeAcc templates + if (fault == NoFault) { + xc->setEA(EA); + } + + return fault; + } +}}; + +def template LoadExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Trace::EdgeInstRecord *traceData) const + { + Addr EA; + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + + if (fault == NoFault) { + fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); + %(memacc_code)s; + } + + if (fault == NoFault) { + %(op_wb)s; + } + + return fault; + } +}}; + + +def template LoadInitiateAcc {{ + Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, + Trace::EdgeInstRecord *traceData) const + { + Addr EA; + Fault fault = NoFault; + + %(op_src_decl)s; + %(op_rd)s; + %(ea_code)s; + + if (fault == NoFault) { + fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); + } + + return fault; + } +}}; + +def template LoadCompleteAcc {{ + Fault %(class_name)s::completeAcc(Packet *pkt, + %(CPU_exec_context)s *xc, + Trace::EdgeInstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + + Mem = pkt->get(); + + if (fault == NoFault) { + %(memacc_code)s; + } + + if (fault == NoFault) { + %(op_wb)s; + } + + return fault; + } +}}; + +def template StoreExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Trace::EdgeInstRecord *traceData) const + { + Addr EA; + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + + if (fault == NoFault) { + %(memacc_code)s; + } + + if (fault == NoFault) { + fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + memAccessFlags, NULL); + if (traceData) { traceData->setData(Mem); } + } + + if (fault == NoFault) { + %(postacc_code)s; + } + + if (fault == NoFault) { + %(op_wb)s; + } + + return fault; + } +}}; + +def template StoreInitiateAcc {{ + Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, + Trace::EdgeInstRecord *traceData) const + { + Addr EA; + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + + if (fault == NoFault) { + %(memacc_code)s; + } + + if (fault == NoFault) { + fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + memAccessFlags, NULL); + if (traceData) { traceData->setData(Mem); } + } + + return fault; + } +}}; + + +def template StoreCompleteAcc {{ + Fault %(class_name)s::completeAcc(Packet *pkt, + %(CPU_exec_context)s *xc, + Trace::EdgeInstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_dest_decl)s; + + if (fault == NoFault) { + %(postacc_code)s; + } + + if (fault == NoFault) { + %(op_wb)s; + + if (traceData) { traceData->setData(getMemData(xc, pkt)); } + } + + return fault; + } +}}; + +let {{ +def MemoryBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, + postacc_code = '', base_class = 'Memory', + decode_template = BasicDecode, exec_template_base = ''): + # Make sure flags are in lists (convert to lists if not). + + mem_flags = makeList(mem_flags) + inst_flags = makeList(inst_flags) + + # add hook to get effective addresses into execution trace output. + ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n' + + # Some CPU models execute the memory operation as an atomic unit, + # while others want to separate them into an effective address + # computation and a memory access operation. As a result, we need + # to generate three StaticInst objects. Note that the latter two + # are nested inside the larger "atomic" one. + + # Generate InstObjParams for each of the three objects. Note that + # they differ only in the set of code objects contained (which in + # turn affects the object's overall operand list). + iop = InstObjParams(name, Name, base_class, + { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code }, + inst_flags) + + if mem_flags: + mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] + s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' + iop.constructor += s + + # select templates + + # The InitiateAcc template is the same for StoreCond templates as the + # corresponding Store template.. + StoreCondInitiateAcc = StoreInitiateAcc + + fullExecTemplate = eval(exec_template_base + 'Execute') + initiateAccTemplate = eval(exec_template_base + 'InitiateAcc') + completeAccTemplate = eval(exec_template_base + 'CompleteAcc') + + # (header_output, decoder_output, decode_block, exec_output) + return (LoadStoreDeclare.subst(iop), + LoadStoreConstructor.subst(iop), + decode_template.subst(iop), + fullExecTemplate.subst(iop) + + EACompExecute.subst(iop) + + initiateAccTemplate.subst(iop) + + completeAccTemplate.subst(iop)) +}}; + +output header {{ + std::string inst2string(MachInst machInst); +}}; + +output decoder {{ + +std::string inst2string(MachInst machInst) +{ + string str = ""; + uint32_t mask = 0x80000000; + + for(int i=0; i < 32; i++) { + if ((machInst & mask) == 0) { + str += "0"; + } else { + str += "1"; + } + + mask = mask >> 1; + } + + return str; +} + +}}; + +def format LoadMemory(memacc_code, ea_code = {{ EA = Op0.ud + _offset; }}, + mem_flags = [], inst_flags = []) {{ + + inst_flags+=['IQOPerands','IsEDGE',{'numConsumer':1}] + (header_output, decoder_output, decode_block, exec_output) = \ + MemoryBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, base_class='Load', + exec_template_base = 'Load') +}}; + +def format StoreMemory(memacc_code, ea_code = {{EA = Op0.ud + _offset; }}, + mem_flags = [], inst_flags = []) {{ + + inst_flags+=['IQOPerands','IsEDGE',{'numConsumer':0}] + (header_output, decoder_output, decode_block, exec_output) = \ + MemoryBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, base_class='Store', + exec_template_base = 'Store') +}}; + + + diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa/formats/m.isa --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa/formats/m.isa Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,128 @@ +// -*- mode:c++ -*- +// +// 2009-2010 HIT Microelectronic Center all rights reserved +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// +// Date: Dec. 2009 +// Authors: Gou Pengfei + +output header {{ + class M3Op:public TRIPSStaticInst + { + protected: + + /// Predication bits + uint8_t pr; + + /// Constructors for TRIPS G format instructions + M3Op(const char* mnem, MachInst _machInst, OpClass __opClass): + TRIPSStaticInst(mnem, _machInst, __opClass),pr(PR) + { + switch(pr){ + case 0x0:_predication = Disable;break; + case 0x2:_predication = PredUponFalse;break; + case 0x3:_predication = PredUponTrue;break; + default: _predication = Reserved; + } + // This is explicitly statments of consumers due to the special coding format of m3 instruction + _numConsumers = 3; + _consumerID[0] = ( M3TX << 7 ) | M3T0; + _consumerID[1] = ( M3TX << 7 ) | M3T1; + _consumerID[2] = ( M3TX << 7 ) | M3T2; + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symTab) const; + }; + class M4Op:public TRIPSStaticInst + { + protected: + + /// Constructors for TRIPS G format instructions + M4Op(const char* mnem, MachInst _machInst, OpClass __opClass): + TRIPSStaticInst(mnem, _machInst, __opClass) + { + // This is explicitly statments of consumers due to the special coding format of m4 instruction + _numConsumers = 4; + _consumerID[0] = ( M4TX << 5 ) | M4T0; + _consumerID[1] = ( M4TX << 5 ) | M4T1; + _consumerID[2] = ( M4TX << 5 ) | M4T2; + _consumerID[3] = ( M4TX << 5 ) | M4T3; + _predication =Disable; + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symTab) const; + }; + +}}; + +output decoder {{ + std::string M3Op::generateDisassembly(Addr pc, const SymbolTable* symtab) const { + std::stringstream ss; + ccprintf(ss, "%-10s",mnemonic); + ss<<" "; + ccprintf(ss, "PR[%d]", pr); + ss<<","; + printConsumer(ss, 0); + printConsumer(ss, 1); + printConsumer(ss, 2); + return ss.str(); + } + std::string M4Op::generateDisassembly(Addr pc, const SymbolTable* symtab) const { + std::stringstream ss; + ccprintf(ss, "%-10s",mnemonic); + ss<<" "; + printConsumer(ss, 0); + printConsumer(ss, 1); + printConsumer(ss, 2); + printConsumer(ss, 3); + return ss.str(); + } +}}; + +// +// Dec. 2009, Gou Pengfei +// Since M3 and M4 is different in consumer encoding than any other instructions, +// so I put the consumers statement codes directyly into constructors of its parent class. +// This is not good enough right now. Maybe some one can figure out a better way to +// represent an arbitrary consumer ID encoding. +// +def format M3Op(code,*opt_flags) {{ + opt_flags+=('IQOPerands',) + iop = InstObjParams(name,Name,'M3Op',code,opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; + +def format M4Op(code,*opt_flags) {{ + opt_flags+=('IQOPerands',) + iop = InstObjParams(name,Name,'M4Op',code,opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa/formats/unknown.isa --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa/formats/unknown.isa Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,83 @@ +// -*- mode:c++ -*- +// +// 2009-2010 HIT Microelectronic Center all rights reserved +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// +// Date: Dec. 2009 +// Authors: Gou Pengfei + +//////////////////////////////////////////////////////////////////// +// +// Unknown instructions +// + +output header {{ + /** + * Static instruction class for unknown (illegal) instructions. + * These cause simulator termination if they are executed in a + * non-speculative mode. This is a leaf class. + */ + class Unknown : public TRIPSStaticInst + { + public: + /// Constructor + Unknown(MachInst _machInst) + : TRIPSStaticInst("unknown", _machInst, No_OpClass) + { + // don't call execute() (which panics) if we're on a + // speculative path + flags[IsNonSpeculative] = true; + } + + %(BasicExecDeclare)s + + std::string + generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string + Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)", + "unknown", machInst, OPCODE, inst2string(machInst)); + } +}}; + +output exec {{ + Fault + Unknown::execute(%(CPU_exec_context)s *xc, + Trace::EdgeInstRecord *traceData) const + { + return new TripsFault; + } +}}; + +def format Unknown() {{ + decode_block = 'return new Unknown(machInst);\n' +}}; + diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa/formats/wr.isa --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa/formats/wr.isa Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,161 @@ +// -*- mode:c++ -*- +// +// 2009-2010 HIT Microelectronic Center all rights reserved +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// +// Date: Dec. 2009 +// Authors: Gou Pengfei + +output header {{ + class WROp:public TRIPSStaticInst + { + protected: + + /// Constructors for TRIPS G format instructions + WROp(const char* mnem, MachInst _machInst, OpClass __opClass): + TRIPSStaticInst(mnem, _machInst, __opClass) + { + + // This is explicitly statments of consumers due to the special coding format of read/write instruction + if (T0_R != T1_R ) { + _numConsumers = 2; + _consumerID[0] = ( 0x1 << 8 ) | T0_R; + _consumerID[1] = ( 0x1 << 8 ) | T1_R; + } else { + _numConsumers = 1; + _consumerID[0] = ( 0x1 << 8 ) | T0_R; + } + + if ( V_R ) flags[IsGRegReadValid] = true; + if ( V_W ) flags[IsGRegWriteValid] = true; + + _predication = Disable; + + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symTab) const; + }; + +}}; + +output decoder {{ + std::string WROp::generateDisassembly(Addr pc, const SymbolTable* symtab) const { + std::stringstream ss; + ccprintf(ss, "%-10s",mnemonic); + ss<<" "; + ccprintf(ss, "gr[%d]", GR_R); + printConsumer(ss,0); + if (_numConsumers > 1) printConsumer(ss, 1); + ss<<" "; + ccprintf(ss, "gw[%d]", GR_W); + return ss.str(); + } +}}; + +// Declarations for execute() methods. +def template WRExecDeclare {{ + Fault execute(%(CPU_exec_context)s *, Trace::EdgeInstRecord * ) const; +}}; + +// Basic instruction class declaration template. +def template WRDeclare {{ + /** + * Static instruction class for "%(mnemonic)s". + */ + class %(class_name)s : public %(base_class)s + { + public: + /// Constructor. + %(class_name)s(MachInst machInst); + %(WRExecDeclare)s + }; +}}; + + +// Basic instruction class execute method template. +def template WRExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::EdgeInstRecord *traceData) const + { + Fault fault = NoFault; + bool write, read; + + write = xc->isExecutingWriteReg(); + read = xc->isExecutingReadReg(); + + %(op_decl)s; + + bool write_true; + + assert( write ^ read ); + + if ( write ) assert( isGRegWriteValid() ); + if ( read ) assert( isGRegReadValid() ); + + if ( write ) write_true = true; + else if ( read ) write_true = false; + else panic("Flags panic when execute write_read inst!\n"); + + if (write_true ) Op0 = xc->getIntIQOperand(0); + else Gr_r = xc->readIntRegOperand(this, 0); + + if(fault == NoFault) + { + %(code)s; + if(fault == NoFault){ + if ( !write_true ) + { + uint64_t final_val = RESULT; + xc->setIntResult(final_val); + if (traceData) { traceData->setData(final_val); } + } + else + { + uint64_t final_val = Gr_w; + xc->setIntRegOperand(this, 0, final_val); + if (traceData) { traceData->setData(final_val); } + } + + } + } + return fault; + } +}}; + +// There're nop insts in header, cope with it. +def template BasicDecode {{ + if ( HEAD_BODY == 0 ) return new Nop(machInst); + else return new %(class_name)s(machInst); +}}; + +def format WROp(code,*opt_flags) {{ + opt_flags+=('IQOPerands',) + iop = InstObjParams(name,Name,'WROp',code,opt_flags) + header_output = WRDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = WRExecute.subst(iop) +}}; + diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa/includes.isa --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa/includes.isa Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,80 @@ +// -*- mode:c++ -*- + +// Copyright (c) 2007 MIPS Technologies, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Korey Sewell + +//////////////////////////////////////////////////////////////////// +// +// Output include file directives. +// + +output header {{ +#include +#include +#include + +#include "arch/trips/isa_traits.hh" +#include "cpu/edge/static_inst.hh" +#include "mem/packet.hh" +}}; + +output decoder {{ +#include "arch/trips/isa_traits.hh" +#include "base/cprintf.hh" +#include "base/loader/symtab.hh" +#include "cpu/edge/thread_context.hh" +#include "arch/trips/isa_traits.hh" +#include "mem/packet.hh" + +#include +#if defined(linux) +#include +#endif + +using namespace TripsISA; +}}; + +output exec {{ +#include +#if defined(linux) +#include +#endif + +#include "cpu/base.hh" +#include "cpu/edge/exetrace.hh" + +#include "mem/packet.hh" +#include "mem/packet_access.hh" + +#include "sim/sim_exit.hh" +#include "sim/eventq.hh" +#include "sim/sim_events.hh" + +using namespace TripsISA; +}}; + diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa/main.isa --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa/main.isa Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,63 @@ +// -*- mode:c++ -*- +// +// 2009-2010 HIT Microelectronic Center all rights reserved +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// +// Date: Dec. 2009 +// Authors: Gou Pengfei + +//////////////////////////////////////////////////////////////////// +// +// TRIPS ISA description file. +// +//////////////////////////////////////////////////////////////////// + +//Include the C++ include directives +##include "includes.isa" + +//////////////////////////////////////////////////////////////////// +// +// Namespace statement. Everything below this line will be in the +// TripsISAInst namespace. +// + +namespace TripsISA; + +//Include the bitfield definitions +##include "bitfields.isa" + +//Include the operand_types and operand definitions +##include "operands.isa" + +//Include the base class for mips instructions, and some support code +##include "base.isa" + +//Include the definitions for the instruction formats +##include "formats/formats.isa" + +//Include the decoder definition +##include "decoder.isa" + diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa/operands.isa --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa/operands.isa Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,70 @@ +// -*- mode:c++ -*- +// +// 2009-2010 HIT Microelectronic Center all rights reserved +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// +// Date: Dec. 2009 +// Authors: Gou Pengfei + + +def operand_types {{ + 'sb' : ('signed int', 8), + 'ub' : ('unsigned int', 8), + 'sh' : ('signed int', 16), + 'uh' : ('unsigned int', 16), + 'sw' : ('signed int', 32), + 'uw' : ('unsigned int', 32), + 'sd' : ('signed int', 64), + 'ud' : ('unsigned int', 64), + 'sf' : ('float', 32), + 'df' : ('float', 64), +}}; + +// Operands of TRIPS ISA are explicitly embedded into the EDGEStaticInst class. +// As a result, they ought to be read from EDGEStaticInst rather than from regs. +// An exceptin of operand is Global read/write instrutions of TRIPS ISA which +// operate the global registers between Hyperblocks. +def operands {{ + + 'Gr_w': ('IntReg', 'ud', 'GR_W', 'IsInteger', 1), + 'Gr_r': ('IntReg', 'ud', 'GR_R', 'IsInteger', 1 ), + + 'Op0': ('IntIQ', 'ud', '0', 'IsInteger', 1), + 'Op1': ('IntIQ', 'ud', '1', 'IsInteger', 2), + + 'FOp0': ('FloatIQ', 'df', '0', 'IsFloating', 1), + 'FOp1': ('FloatIQ', 'df', '1', 'IsFloating', 2), + + 'RESULT': ('IntIQ', 'ud', None, 'IsInteger', 1), + 'FRESULT': ('FloatIQ', 'df', None, 'IsFloating', 1), + + 'Mem':('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 1), + 'NPC':('NPC', 'ud', None, 'IsControl', 1), + 'NextBlockPC': ('NextBlockPC', 'ud', None, 'IsControl', 1), + + 'R0':('IntReg', 'ud', '0', 'IsInteger', 1), +}}; + diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/isa_traits.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/isa_traits.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + * Gabe Black + */ + +#ifndef __ARCH_TRIPS_ISA_TRAITS_HH__ +#define __ARCH_TRIPS_ISA_TRAITS_HH__ + +//Trips is big-endian +namespace BigEndianGuest {} +#include + +#include "arch/trips/types.hh" +#include "base/types.hh" +#include "config/full_system.hh" +#include "arch/trips/constants.hh" + + +class EDGEStaticInstPtr; +class StaticInstPtr; + +namespace TripsISA { + +using namespace BigEndianGuest; + +/// Operand of TRIPS is 64-bit +typedef uint64_t OpSize; +/// Size of consumer ID +typedef uint16_t ConsumerID; + +/// Block ID +typedef uint32_t BlockID; +/// Chunk ID +typedef uint32_t ChunkID; +/// Inst ID +typedef uint32_t InstID; + +/// Load/Store ID +typedef int LsID; +/// Exit ID +typedef uint32_t ExitID; + +typedef std::vector HeaderInfo; + +EDGEStaticInstPtr decodeInst(ExtMachInst, uint8_t); +StaticInstPtr decodeInst(ExtMachInst); + +/// TRIPS instruction format related definitions +const uint32_t ChunkSize = 128; // In bytes +const uint32_t ChunkSizeInWords = 32; // In words +const Addr ChunkOffset = ChunkSize - 1; +const Addr ChunkMask = ~(ChunkSize - 1); +const uint32_t MaxBlockSize = 5; // In chunks +const uint8_t HeaderInfoSize = 4; // In Words +const uint32_t StoreMaskNum = 32; // In bits + +// Trips Does NOT have a delay slot +#define ISA_HAS_DELAY_SLOT 0 + +const Addr PageShift = 12; +const Addr PageBytes = ULL(1) << PageShift; +const Addr PageMask = ~(PageBytes - 1); +const Addr PageOffset = PageBytes - 1; + +//////////////////////////////////////////////////////////////////////// +// +// Translation stuff +// + +const Addr PteShift = 3; +const Addr NPtePageShift = PageShift - PteShift; +const Addr NPtePage = ULL(1) << NPtePageShift; +const Addr PteMask = NPtePage - 1; + +// User Virtual +const Addr USegBase = ULL(0x0); +const Addr USegEnd = ULL(0x000003ffffffffff); + +// Kernel Direct Mapped +const Addr K0SegBase = ULL(0xfffffc0000000000); +const Addr K0SegEnd = ULL(0xfffffdffffffffff); + +// Kernel Virtual +const Addr K1SegBase = ULL(0xfffffe0000000000); +const Addr K1SegEnd = ULL(0xffffffffffffffff); + +// For loading... XXX This maybe could be USegEnd?? --ali +const Addr LoadAddrMask = ULL(0xffffffffff); + +//////////////////////////////////////////////////////////////////////// +// +// Interrupt levels +// +enum InterruptLevels +{ + INTLEVEL_SOFTWARE_MIN = 4, + INTLEVEL_SOFTWARE_MAX = 19, + + INTLEVEL_EXTERNAL_MIN = 20, + INTLEVEL_EXTERNAL_MAX = 34, + + INTLEVEL_IRQ0 = 20, + INTLEVEL_IRQ1 = 21, + INTINDEX_ETHERNET = 0, + INTINDEX_SCSI = 1, + INTLEVEL_IRQ2 = 22, + INTLEVEL_IRQ3 = 23, + + INTLEVEL_SERIAL = 33, + + NumInterruptLevels = INTLEVEL_EXTERNAL_MAX +}; + +enum mode_type +{ + mode_kernel = 0, // kernel + mode_executive = 1, // executive (unused by unix) + mode_supervisor = 2, // supervisor (unused by unix) + mode_user = 3, // user mode + mode_number // number of modes +}; + +// Constants Related to the number of registers + +enum { + LogVMPageSize = 12, // 4K bytes + VMPageSize = (1 << LogVMPageSize), + + BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned + + MachineBytes = 8, + WordBytes = 4, + HalfwordBytes = 2, + ByteBytes = 1, +}; + +enum BlockStatus{ + Head = 0, + Normal = 1, +}; + +enum WriteReadFlag{ + Write = 0, + Read = 1 +}; + +/// Dataflow token type generated by this intruction +enum DataflowTokenType { + General, + Nullification, + Exception +}; + +enum PredStatus{ + PredTrue, + PredFalse, + NoPred +}; + +enum ConsumerType { + WriteSlotOrNoTarget = 0, + PredSlot, + Operand0, + Operand1, + InvalidType +}; + +enum ConsumerSubType { + NoTarget = 0, + WriteSlot, + InvalidSubType +}; + +enum Predication { + Disable = 0, + PredUponFalse = 2, + PredUponTrue = 3, + Reserved +}; + +enum ExitType { + seq, + branch, + call, + ret, + ibranch +}; +// return a no-op instruction... used for instruction fetch faults +// Alpha UNOP (ldq_u r31,0(r0)) +//const ExtMachInst NoopMachInst = 0x2ffe0000; + +} // namespace AlphaISA + +#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/linux/linux.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/linux/linux.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Korey Sewell + */ + +#ifndef __TRIPS_TRIPS_LINUX_LINUX_HH__ +#define __TRIPS_TRIPS_LINUX_LINUX_HH__ + +#include "kern/linux/linux.hh" + +/* TripsLinux class contains static constants/definitions/misc. + * structures which are specific to the Linux OS AND the Trips + * architecture + * + * These params comes from trips tool-chain dir. + * ttools2/include/fcntl.h + * ttools2/include/sys/ioctl.h + * ttools2/include/sys/ppc-ioctl.h + * ttools2/include/sys/stat.h + * ttools2/include/sys/types.h + * + * For file open, trips is much more like x86 + * For ioctl, trips is much more like ppc + */ +class TripsLinux : public Linux +{ + public: + typedef int64_t time_t; + + typedef struct { + uint32_t st_dev; + uint32_t __pad1; + uint64_t st_ino; + uint32_t st_mode; + uint16_t st_nlink; + uint32_t st_uid; + uint32_t st_gid; + uint32_t st_rdev; + uint32_t __pad2; + uint64_t st_size; + uint64_t st_blksize; + uint64_t st_blocks; + uint64_t st_atimeX; + uint64_t __unused1; + uint64_t st_mtimeX; + uint64_t __unused2; + uint64_t st_ctimeX; + uint64_t __unused3; + uint64_t __unused4; + uint64_t __unused5; + } tgt_stat; + /// This table maps the target open() flags to the corresponding + /// host open() flags. + static OpenFlagTransTable openFlagTable[]; + + /// Number of entries in openFlagTable[]. + static const int NUM_OPEN_FLAGS; + + //@{ + /// open(2) flag values. + static const int TGT_O_RDONLY = 00000000; //!< O_RDONLY + static const int TGT_O_WRONLY = 00000001; //!< O_WRONLY + static const int TGT_O_RDWR = 00000002; //!< O_RDWR + static const int TGT_O_CREAT = 00000100; //!< O_CREAT + static const int TGT_O_EXCL = 00000200; //!< O_EXCL + static const int TGT_O_NOCTTY = 00000400; //!< O_NOCTTY + static const int TGT_O_TRUNC = 00001000; //!< O_TRUNC + static const int TGT_O_APPEND = 00002000; //!< O_APPEND + static const int TGT_O_NONBLOCK = 00004000; //!< O_NONBLOCK + static const int TGT_O_NDELAY = 000040000; //!< O_NDELAY + static const int TGT_O_SYNC = 00010000; //!< O_SYNC + static const int TGT_O_LARGEFILE = 00100000; //!< O_LARGEFILE + static const int TGT_O_DIRECTORY = 00200000; //!< O_DIRECTORY + static const int TGT_O_NOFOLLOW = 00400000; //!< O_NOFOLLOW + //@} + + /// For mmap(). + static const unsigned TGT_MAP_ANONYMOUS = 0x20; + + //@{ + /// For getrusage(). + static const int TGT_RUSAGE_SELF = 0; + static const int TGT_RUSAGE_CHILDREN = -1; + static const int TGT_RUSAGE_BOTH = -2; + //@} + + //@{ + /// ioctl() command codes. + + /// I havn't change these yet because + /// these params take no effect as far as I know + static const unsigned TIOCGETP_ = 0x40067408; + static const unsigned TIOCSETP_ = 0x80067409; + static const unsigned TIOCSETN_ = 0x8006740a; + static const unsigned TIOCSETC_ = 0x80067411; + static const unsigned TIOCGETC_ = 0x40067412; + static const unsigned FIONREAD_ = 0x4004667f; + static const unsigned TIOCISATTY_ = 0x2000745e; + static const unsigned TIOCGETS_ = 0x402c7413; + static const unsigned TIOCGETA_ = 0x40127417; + static const unsigned TCSETAW_ = 0x80127419; // ??? + + static const unsigned TCGETA_ = 0x40117417; + + //@} + + /// For table(). + static const int TBL_SYSINFO = 12; + + /// Resource enumeration for getrlimit(). + enum rlimit_resources { + TGT_RLIMIT_CPU = 0, + TGT_RLIMIT_FSIZE = 1, + TGT_RLIMIT_DATA = 2, + TGT_RLIMIT_STACK = 3, + TGT_RLIMIT_CORE = 4, + TGT_RLIMIT_RSS = 5, + TGT_RLIMIT_NPROC= 6, + TGT_RLIMIT_NOFILE = 7, + TGT_RLIMIT_MEMLOCK = 8, + TGT_RLIMIT_AS = 9, + TGT_RLIMIT_LOCKS = 10 + }; + + typedef struct { + int64_t uptime; /* Seconds since boot */ + uint64_t loads[3]; /* 1, 5, and 15 minute load averages */ + uint64_t totalram; /* Total usable main memory size */ + uint64_t freeram; /* Available memory size */ + uint64_t sharedram; /* Amount of shared memory */ + uint64_t bufferram; /* Memory used by buffers */ + uint64_t totalswap; /* Total swap space size */ + uint64_t freeswap; /* swap space still available */ + uint16_t procs; /* Number of current processes */ + uint16_t pad; /* Explicitly padding*/ + uint64_t totalhigh; /* Total high memory size */ + uint64_t freehigh; /* Available high memory size */ + uint32_t mem_unit; /* Memory unit size in bytes */ + int8_t _f[20-2*sizeof(uint64_t)-sizeof(uint32_t)]; + } tgt_sysinfo; +}; + +#endif // __TRIPS_TRIPS_LINUX_LINUX_HH__ diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/linux/linux.cc --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/linux/linux.cc Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Korey Sewell + */ + +#include + +#include "arch/trips/linux/linux.hh" + +// open(2) flags translation table +OpenFlagTransTable TripsLinux::openFlagTable[] = { +#ifdef _MSC_VER + { TripsLinux::TGT_O_RDONLY, _O_RDONLY }, + { TripsLinux::TGT_O_WRONLY, _O_WRONLY }, + { TripsLinux::TGT_O_RDWR, _O_RDWR }, + { TripsLinux::TGT_O_APPEND, _O_APPEND }, + { TripsLinux::TGT_O_CREAT, _O_CREAT }, + { TripsLinux::TGT_O_TRUNC, _O_TRUNC }, + { TripsLinux::TGT_O_EXCL, _O_EXCL }, +#ifdef _O_NONBLOCK + { TripsLinux::TGT_O_NONBLOCK, _O_NONBLOCK }, +#endif +#ifdef _O_NOCTTY + { TripsLinux::TGT_O_NOCTTY, _O_NOCTTY }, +#endif +#ifdef _O_SYNC + { TripsLinux::TGT_O_SYNC, _O_SYNC }, +#endif +#else /* !_MSC_VER */ + { TripsLinux::TGT_O_RDONLY, O_RDONLY }, + { TripsLinux::TGT_O_WRONLY, O_WRONLY }, + { TripsLinux::TGT_O_RDWR, O_RDWR }, + { TripsLinux::TGT_O_APPEND, O_APPEND }, + { TripsLinux::TGT_O_CREAT, O_CREAT }, + { TripsLinux::TGT_O_TRUNC, O_TRUNC }, + { TripsLinux::TGT_O_EXCL, O_EXCL }, + { TripsLinux::TGT_O_NONBLOCK, O_NONBLOCK }, + { TripsLinux::TGT_O_NOCTTY, O_NOCTTY }, +#ifdef O_SYNC + { TripsLinux::TGT_O_SYNC, O_SYNC }, +#endif +#endif /* _MSC_VER */ +}; + +const int TripsLinux::NUM_OPEN_FLAGS = + (sizeof(TripsLinux::openFlagTable)/sizeof(TripsLinux::openFlagTable[0])); diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/linux/process.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/linux/process.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + */ + +#ifndef __TRIPS_LINUX_PROCESS_HH__ +#define __TRIPS_LINUX_PROCESS_HH__ + +#include "arch/trips/process.hh" + +namespace TripsISA { + +/// A process with emulated Trips/Linux syscalls. +class TripsLinuxProcess : public TripsLiveProcess +{ + public: + /// Constructor. + TripsLinuxProcess(LiveProcessParams * params, ObjectFile *objFile); + + virtual SyscallDesc* getDesc(int callnum); + + /// Array of syscall descriptors, indexed by call number. + static SyscallDesc syscallDescs[]; + + const int Num_Syscall_Descs; +}; + +} // namespace TripsISA + +#endif // __TRIPS_LINUX_PROCESS_HH__ diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/linux/process.cc --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/linux/process.cc Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,314 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + * Ali Saidi + */ + +#include "arch/trips/linux/linux.hh" +#include "arch/trips/linux/process.hh" +#include "arch/trips/isa_traits.hh" + +#include "base/trace.hh" +#include "cpu/thread_context.hh" +#include "kern/linux/linux.hh" + +#include "sim/process.hh" +#include "sim/syscall_emul.hh" + +using namespace std; +using namespace TripsISA; + +/// Target uname() handler. +static SyscallReturn +unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process, + ThreadContext *tc) +{ + int index = 0; + TypedBufferArg name(process->getSyscallArg(tc, index)); + + strcpy(name->sysname, "Linux"); + strcpy(name->nodename, "m5.eecs.umich.edu"); + strcpy(name->release, "2.6.26"); + strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003"); + strcpy(name->machine, "trips"); + + name.copyOut(tc->getMemPort()); + return 0; +} + +SyscallDesc TripsLinuxProcess::syscallDescs[] = { + /* 0 */ SyscallDesc("osf_syscall", unimplementedFunc), + /* 1 */ SyscallDesc("exit", exitFunc), + /* 2 */ SyscallDesc("fork", unimplementedFunc), + /* 3 */ SyscallDesc("read", readFunc), + /* 4 */ SyscallDesc("write", writeFunc), + /* 5 */ SyscallDesc("open", openFunc), + /* 6 */ SyscallDesc("close", closeFunc), + /* 7 */ SyscallDesc("waitpid", unimplementedFunc), + /* 8 */ SyscallDesc("creat", unimplementedFunc), + /* 9 */ SyscallDesc("link", unimplementedFunc), + /* 10 */ SyscallDesc("unlink", unlinkFunc), + /* 11 */ SyscallDesc("execve", unimplementedFunc), + /* 12 */ SyscallDesc("chdir", unimplementedFunc), + /* 13 */ SyscallDesc("time", timeFunc), + /* 14 */ SyscallDesc("mknod", unimplementedFunc), + /* 15 */ SyscallDesc("chmod", chmodFunc), + /* 16 */ SyscallDesc("lchown", unimplementedFunc), + /* 17 */ SyscallDesc("break", unimplementedFunc), + /* 18 */ SyscallDesc("oldstat", unimplementedFunc), + /* 19 */ SyscallDesc("lseek", lseekFunc), + /* 20 */ SyscallDesc("getpid", getpidFunc), + /* 21 */ SyscallDesc("mount", unimplementedFunc), + /* 22 */ SyscallDesc("umount", unimplementedFunc), + /* 23 */ SyscallDesc("setuid", setuidFunc), + /* 24 */ SyscallDesc("getuid", getuidFunc), + /* 25 */ SyscallDesc("stime", unimplementedFunc), + /* 26 */ SyscallDesc("ptrace", unimplementedFunc), + /* 27 */ SyscallDesc("alarm", unimplementedFunc), + /* 28 */ SyscallDesc("oldfstat", unimplementedFunc), + /* 29 */ SyscallDesc("pause", unimplementedFunc), + /* 30 */ SyscallDesc("utime", unimplementedFunc), + /* 31 */ SyscallDesc("stty", unimplementedFunc), + /* 32 */ SyscallDesc("gtty", unimplementedFunc), + /* 33 */ SyscallDesc("access", unimplementedFunc), + /* 34 */ SyscallDesc("nice", unimplementedFunc), + /* 35 */ SyscallDesc("ftime", unimplementedFunc), + /* 36 */ SyscallDesc("sync", unimplementedFunc), + /* 37 */ SyscallDesc("kill", unimplementedFunc), + /* 38 */ SyscallDesc("rename", renameFunc), + /* 39 */ SyscallDesc("mkdir", unimplementedFunc), + /* 40 */ SyscallDesc("rmdir", unimplementedFunc), + /* 41 */ SyscallDesc("dup", dupFunc), + /* 42 */ SyscallDesc("pipe", pipePseudoFunc), + /* 43 */ SyscallDesc("times", unimplementedFunc), + /* 44 */ SyscallDesc("prof", unimplementedFunc), + /* 45 */ SyscallDesc("brk", brkFunc), + /* 46 */ SyscallDesc("setgid", unimplementedFunc), + /* 47 */ SyscallDesc("getgid", getgidFunc), + /* 48 */ SyscallDesc("signal", unimplementedFunc), + /* 49 */ SyscallDesc("geteuid", geteuidFunc), + /* 50 */ SyscallDesc("getegid", getegidFunc), + /* 51 */ SyscallDesc("acct", unimplementedFunc), + /* 52 */ SyscallDesc("umount2", unimplementedFunc), + /* 53 */ SyscallDesc("lock", unimplementedFunc), + /* 54 */ SyscallDesc("ioctl", ioctlFunc), + /* 55 */ SyscallDesc("fcntl", fcntlFunc), + /* 56 */ SyscallDesc("mpx", unimplementedFunc), + /* 57 */ SyscallDesc("setpgid", unimplementedFunc), + /* 58 */ SyscallDesc("ulimit", unimplementedFunc), + /* 59 */ SyscallDesc("oldolduname", unimplementedFunc), + /* 60 */ SyscallDesc("umask", umaskFunc), + /* 61 */ SyscallDesc("chroot", unimplementedFunc), + /* 62 */ SyscallDesc("ustat", unimplementedFunc), + /* 63 */ SyscallDesc("dup2", unimplementedFunc), + /* 64 */ SyscallDesc("getppid", getppidFunc), + /* 65 */ SyscallDesc("getpgrp", unimplementedFunc), + /* 66 */ SyscallDesc("setsid", unimplementedFunc), + /* 67 */ SyscallDesc("sigaction", unimplementedFunc), + /* 68 */ SyscallDesc("sgetmask", unimplementedFunc), + /* 69 */ SyscallDesc("ssetmask", unimplementedFunc), + /* 70 */ SyscallDesc("setreuid", unimplementedFunc), + /* 71 */ SyscallDesc("setregid", unimplementedFunc), + /* 72 */ SyscallDesc("sigsuspend", unimplementedFunc), + /* 73 */ SyscallDesc("sigpending", unimplementedFunc), + /* 74 */ SyscallDesc("sethostname", unimplementedFunc), + /* 75 */ SyscallDesc("setrlimit", unimplementedFunc), + /* 76 */ SyscallDesc("getrlimit", unimplementedFunc), + /* 77 */ SyscallDesc("getrusage", unimplementedFunc), + /* 78 */ SyscallDesc("gettimeofday", gettimeofdayFunc), + /* 79 */ SyscallDesc("settimeofday", unimplementedFunc), + /* 80 */ SyscallDesc("getgroups", unimplementedFunc), + /* 81 */ SyscallDesc("setgroups", unimplementedFunc), + /* 82 */ SyscallDesc("select", unimplementedFunc), + /* 83 */ SyscallDesc("symlink", unimplementedFunc), + /* 84 */ SyscallDesc("oldlstat", unimplementedFunc), + /* 85 */ SyscallDesc("readlink", readlinkFunc), + /* 86 */ SyscallDesc("uselib", unimplementedFunc), + /* 87 */ SyscallDesc("swapon", unimplementedFunc), + /* 88 */ SyscallDesc("reboot", unimplementedFunc), + /* 89 */ SyscallDesc("readdir", unimplementedFunc), + /* 90 */ SyscallDesc("mmap", mmapFunc), + /* 91 */ SyscallDesc("munmap", munmapFunc), + /* 92 */ SyscallDesc("truncate", truncateFunc), + /* 93 */ SyscallDesc("ftruncate", ftruncateFunc), + /* 94 */ SyscallDesc("fchmod", unimplementedFunc), + /* 95 */ SyscallDesc("fchown", unimplementedFunc), + /* 96 */ SyscallDesc("getpriority", unimplementedFunc), + /* 97 */ SyscallDesc("setpriority", unimplementedFunc), + /* 98 */ SyscallDesc("profil", unimplementedFunc), + /* 99 */ SyscallDesc("statfs", unimplementedFunc), + /* 100 */ SyscallDesc("fstatfs", unimplementedFunc), + /* 101 */ SyscallDesc("ioperm", unimplementedFunc), + /* 102 */ SyscallDesc("socketcall", unimplementedFunc), + /* 103 */ SyscallDesc("syslog", unimplementedFunc), + /* 104 */ SyscallDesc("setitimer", unimplementedFunc), + /* 105 */ SyscallDesc("getitimer", unimplementedFunc), + /* 106 */ SyscallDesc("stat", statFunc), + /* 107 */ SyscallDesc("lstat", lstatFunc), + /* 108 */ SyscallDesc("fstat", fstatFunc), + /* 109 */ SyscallDesc("olduname", unimplementedFunc), + /* 110 */ SyscallDesc("iopl", unimplementedFunc), + /* 111 */ SyscallDesc("vhangup", unimplementedFunc), + /* 112 */ SyscallDesc("idle", ignoreFunc), + /* 113 */ SyscallDesc("vm86", unimplementedFunc), + /* 114 */ SyscallDesc("wait4", unimplementedFunc), + /* 115 */ SyscallDesc("swapoff", unimplementedFunc), + /* 116 */ SyscallDesc("sysinfo", sysinfoFunc), + /* 117 */ SyscallDesc("ipc", unimplementedFunc), + /* 118 */ SyscallDesc("fsync", unimplementedFunc), + /* 119 */ SyscallDesc("sigreturn", unimplementedFunc), + /* 120 */ SyscallDesc("clone", unimplementedFunc), + /* 121 */ SyscallDesc("setdomainname", unimplementedFunc), + /* 122 */ SyscallDesc("uname", unameFunc), + /* 123 */ SyscallDesc("modify_ldt", unimplementedFunc), + /* 124 */ SyscallDesc("adjtimex", unimplementedFunc), + /* 125 */ SyscallDesc("mprotect", unimplementedFunc), + /* 126 */ SyscallDesc("sigprocmask", unimplementedFunc), + /* 127 */ SyscallDesc("create_module", unimplementedFunc), + /* 128 */ SyscallDesc("init_module", unimplementedFunc), + /* 129 */ SyscallDesc("delete_module", unimplementedFunc), + /* 130 */ SyscallDesc("get_kernel_syms", unimplementedFunc), + /* 131 */ SyscallDesc("quotactl", unimplementedFunc), + /* 132 */ SyscallDesc("getpgid", unimplementedFunc), + /* 133 */ SyscallDesc("fchdir", unimplementedFunc), + /* 134 */ SyscallDesc("bdflush", unimplementedFunc), + /* 135 */ SyscallDesc("sysfs", unimplementedFunc), + /* 136 */ SyscallDesc("personality", unimplementedFunc), + /* 137 */ SyscallDesc("afs_syscall", unimplementedFunc), + /* 138 */ SyscallDesc("setfsuid", unimplementedFunc), + /* 139 */ SyscallDesc("setfsgid", unimplementedFunc), + /* 140 */ SyscallDesc("llseek", unimplementedFunc), + /* 141 */ SyscallDesc("getdents", unimplementedFunc), + /* 142 */ SyscallDesc("newselect", unimplementedFunc), + /* 143 */ SyscallDesc("flock", unimplementedFunc), + /* 144 */ SyscallDesc("msync", unimplementedFunc), + /* 145 */ SyscallDesc("readv", unimplementedFunc), + /* 146 */ SyscallDesc("writev", unimplementedFunc), + /* 147 */ SyscallDesc("getsid", unimplementedFunc), + /* 148 */ SyscallDesc("fdatasync", unimplementedFunc), + /* 149 */ SyscallDesc("sysctl", unimplementedFunc), + /* 150 */ SyscallDesc("mlock", unimplementedFunc), + /* 151 */ SyscallDesc("munlock", unimplementedFunc), + /* 152 */ SyscallDesc("mlockall", unimplementedFunc), + /* 153 */ SyscallDesc("munlockall", unimplementedFunc), + /* 154 */ SyscallDesc("sched_setparam", unimplementedFunc), + /* 155 */ SyscallDesc("sched_getparam", unimplementedFunc), + /* 156 */ SyscallDesc("sched_setscheduler", unimplementedFunc), + /* 157 */ SyscallDesc("sched_getscheduler", unimplementedFunc), + /* 158 */ SyscallDesc("sched_yield", unimplementedFunc), + /* 159 */ SyscallDesc("sched_get_priority_max", unimplementedFunc), + /* 160 */ SyscallDesc("sched_get_priority_min", unimplementedFunc), + /* 161 */ SyscallDesc("sched_rr_get_interval", unimplementedFunc), + /* 162 */ SyscallDesc("nanosleep", unimplementedFunc), + /* 163 */ SyscallDesc("mremap", unimplementedFunc), + /* 164 */ SyscallDesc("setresuid", unimplementedFunc), + /* 165 */ SyscallDesc("getresuid", unimplementedFunc), + /* 166 */ SyscallDesc("query_module", unimplementedFunc), + /* 167 */ SyscallDesc("poll", unimplementedFunc), + /* 168 */ SyscallDesc("nfsservctl", unimplementedFunc), + /* 169 */ SyscallDesc("setresgid", unimplementedFunc), + /* 170 */ SyscallDesc("getresgid", unimplementedFunc), + /* 171 */ SyscallDesc("prctl", unimplementedFunc), + /* 172 */ SyscallDesc("rt_sigreturn", unimplementedFunc), + /* 173 */ SyscallDesc("rt_sigaction", unimplementedFunc), + /* 174 */ SyscallDesc("rt_sigprocmask", unimplementedFunc), + /* 175 */ SyscallDesc("rt_sigpending", unimplementedFunc), + /* 176 */ SyscallDesc("rt_sigtimedwait", unimplementedFunc), + /* 177 */ SyscallDesc("rt_sigqueueinfo", unimplementedFunc), + /* 178 */ SyscallDesc("rt_sigsuspend", unimplementedFunc), + /* 179 */ SyscallDesc("pread", unimplementedFunc), + /* 180 */ SyscallDesc("pwrite", unimplementedFunc), + /* 181 */ SyscallDesc("chown", unimplementedFunc), + /* 182 */ SyscallDesc("getcwd", unimplementedFunc), + /* 183 */ SyscallDesc("capget", unimplementedFunc), + /* 184 */ SyscallDesc("capset", unimplementedFunc), + /* 185 */ SyscallDesc("sigaltstack", unimplementedFunc), + /* 186 */ SyscallDesc("sendfile", unimplementedFunc), + /* 187 */ SyscallDesc("getpmsg", unimplementedFunc), + /* 188 */ SyscallDesc("putpmsg", unimplementedFunc), + /* 189 */ SyscallDesc("vfork", unimplementedFunc), + /* 190 */ SyscallDesc("ugetrlimit", unimplementedFunc), + /* 191 */ SyscallDesc("unknown #191", unimplementedFunc), + /* 192 */ SyscallDesc("mmap2", unimplementedFunc), + /* 193 */ SyscallDesc("truncate64", unimplementedFunc), + /* 194 */ SyscallDesc("ftruncate64", unimplementedFunc), + /* 195 */ SyscallDesc("stat64", unimplementedFunc), + /* 196 */ SyscallDesc("lstat64", unimplementedFunc), + /* 197 */ SyscallDesc("fstat64", unimplementedFunc), + /* 198 */ SyscallDesc("pciconfig_read", unimplementedFunc), + /* 199 */ SyscallDesc("pciconfig_write", unimplementedFunc), + /* 200 */ SyscallDesc("pciconfig_iobase", unimplementedFunc), + /* 201 */ SyscallDesc("multiplexer", unimplementedFunc), + /* 202 */ SyscallDesc("getdents64", unimplementedFunc), + /* 203 */ SyscallDesc("pivot_root", unimplementedFunc), + /* 204 */ SyscallDesc("fcntl64", unimplementedFunc), + /* 205 */ SyscallDesc("madvise", unimplementedFunc), + /* 206 */ SyscallDesc("mincore", unimplementedFunc), + /* 207 */ SyscallDesc("unknown #207", unimplementedFunc), + /* 208 */ SyscallDesc("unknown #208", unimplementedFunc), + /* 209 */ SyscallDesc("unknown #209", unimplementedFunc), + /* 210 */ SyscallDesc("unknown #210", unimplementedFunc), + /* 211 */ SyscallDesc("unknown #211", unimplementedFunc), + /* 212 */ SyscallDesc("unknown #212", unimplementedFunc), + /* 213 */ SyscallDesc("unknown #213", unimplementedFunc), + /* 214 */ SyscallDesc("unknown #214", unimplementedFunc), + /* 215 */ SyscallDesc("unknown #215", unimplementedFunc), + /* 216 */ SyscallDesc("unknown #216", unimplementedFunc), + /* 217 */ SyscallDesc("unknown #217", unimplementedFunc), + /* 218 */ SyscallDesc("unknown #218", unimplementedFunc), + /* 219 */ SyscallDesc("unknown #219", unimplementedFunc), + /* 220 */ SyscallDesc("unknown #220", unimplementedFunc), + /* 221 */ SyscallDesc("unknown #221", unimplementedFunc), + /* 222 */ SyscallDesc("unknown #222", unimplementedFunc), + /* 223 */ SyscallDesc("unknown #223", unimplementedFunc), + /* 224 */ SyscallDesc("unknown #224", unimplementedFunc), + /* 225 */ SyscallDesc("unknown #225", unimplementedFunc), + /* 226 */ SyscallDesc("unknown #226", unimplementedFunc), + /* 227 */ SyscallDesc("unknown #227", unimplementedFunc), + /* 228 */ SyscallDesc("unknown #228", unimplementedFunc), + /* 229 */ SyscallDesc("unknown #229", unimplementedFunc), + /* 230 */ SyscallDesc("dumpperf", unimplementedFunc) +}; + +TripsLinuxProcess::TripsLinuxProcess(LiveProcessParams * params, + ObjectFile *objFile) + : TripsLiveProcess(params, objFile), + Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)) +{ + //init_regs->intRegFile[0] = 0; +} + + + +SyscallDesc* +TripsLinuxProcess::getDesc(int callnum) +{ + if (callnum < 0 || callnum >= Num_Syscall_Descs) + return NULL; + return &syscallDescs[callnum]; +} diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/linux/system.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/linux/system.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2004-2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + * Lisa Hsu + * Nathan Binkert + */ + +#ifndef __ARCH_TRIPS_LINUX_SYSTEM_HH__ +#define __ARCH_TRIPS_LINUX_SYSTEM_HH__ + +class ThreadContext; + +class BreakPCEvent; +class IdleStartEvent; + +#include "arch/trips/idle_event.hh" +#include "arch/trips/system.hh" +#include "kern/linux/events.hh" +#include "params/LinuxTripsSystem.hh" + +/** + * This class contains linux specific system code (Loading, Events). + * It points to objects that are the system binaries to load and patches them + * appropriately to work in simulator. + */ +class LinuxTripsSystem : public TripsSystem +{ + private: + struct SkipDelayLoopEvent : public SkipFuncEvent + { + SkipDelayLoopEvent(PCEventQueue *q, const std::string &desc, Addr addr) + : SkipFuncEvent(q, desc, addr) {} + virtual void process(ThreadContext *tc); + }; + + struct PrintThreadInfo : public PCEvent + { + PrintThreadInfo(PCEventQueue *q, const std::string &desc, Addr addr) + : PCEvent(q, desc, addr) {} + virtual void process(ThreadContext *tc); + }; + + /** + * Addresses defining where the kernel bootloader places various + * elements. Details found in include/asm-trips/system.h + */ + Addr KernelStart; // Lookup the symbol swapper_pg_dir + + public: + Addr InitStack() const { return KernelStart + 0x02000; } + Addr EmptyPGT() const { return KernelStart + 0x04000; } + Addr EmptyPGE() const { return KernelStart + 0x08000; } + Addr ZeroPGE() const { return KernelStart + 0x0A000; } + Addr StartAddr() const { return KernelStart + 0x10000; } + + Addr Param() const { return ZeroPGE() + 0x0; } + Addr CommandLine() const { return Param() + 0x0; } + Addr InitrdStart() const { return Param() + 0x100; } + Addr InitrdSize() const { return Param() + 0x108; } + static const int CommandLineSize = 256; + + private: +#ifndef NDEBUG + /** Event to halt the simulator if the kernel calls panic() */ + BreakPCEvent *kernelPanicEvent; + + /** Event to halt the simulator if the kernel calls die_if_kernel */ + BreakPCEvent *kernelDieEvent; +#endif + + /** + * Event to skip determine_cpu_caches() because we don't support + * the IPRs that the code can access to figure out cache sizes + */ + SkipFuncEvent *skipCacheProbeEvent; + + /** PC based event to skip the ide_delay_50ms() call */ + SkipFuncEvent *skipIdeDelay50msEvent; + + /** + * PC based event to skip the dprink() call and emulate its + * functionality + */ + Linux::DebugPrintkEvent *debugPrintkEvent; + + /** + * Skip calculate_delay_loop() rather than waiting for this to be + * calculated + */ + SkipDelayLoopEvent *skipDelayLoopEvent; + + /** + * Event to print information about thread switches if the trace flag + * Thread is set + */ + PrintThreadInfo *printThreadEvent; + + /** Grab the PCBB of the idle process when it starts */ + IdleStartEvent *idleStartEvent; + + public: + typedef LinuxTripsSystemParams Params; + LinuxTripsSystem(Params *p); + ~LinuxTripsSystem(); + + void setDelayLoop(ThreadContext *tc); +}; + +#endif // __ARCH_TRIPS_LINUX_SYSTEM_HH__ diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/linux/system.cc --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/linux/system.cc Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2004-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + * Lisa Hsu + * Nathan Binkert + * Steve Reinhardt + */ + +/** + * @file + * This code loads the linux kernel, console, pal and patches certain + * functions. The symbol tables are loaded so that traces can show + * the executing function and we can skip functions. Various delay + * loops are skipped and their final values manually computed to speed + * up boot time. + */ + +#include "arch/vtophys.hh" +#include "arch/trips/idle_event.hh" +#include "arch/trips/linux/system.hh" +#include "arch/trips/linux/threadinfo.hh" +#include "arch/trips/system.hh" +#include "base/loader/symtab.hh" +#include "cpu/thread_context.hh" +#include "cpu/base.hh" +#include "dev/platform.hh" +#include "kern/linux/printk.hh" +#include "kern/linux/events.hh" +#include "mem/physical.hh" +#include "mem/port.hh" +#include "sim/arguments.hh" +#include "sim/byteswap.hh" + +using namespace std; +using namespace TripsISA; +using namespace Linux; + +LinuxTripsSystem::LinuxTripsSystem(Params *p) + : TripsSystem(p) +{ + Addr addr = 0; + + /** + * The symbol swapper_pg_dir marks the beginning of the kernel and + * the location of bootloader passed arguments + */ + if (!kernelSymtab->findAddress("swapper_pg_dir", KernelStart)) { + panic("Could not determine start location of kernel"); + } + + /** + * Since we aren't using a bootloader, we have to copy the + * kernel arguments directly into the kernel's memory. + */ + virtPort.writeBlob(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(), + params()->boot_osflags.length()+1); + + /** + * find the address of the est_cycle_freq variable and insert it + * so we don't through the lengthly process of trying to + * calculated it by using the PIT, RTC, etc. + */ + if (kernelSymtab->findAddress("est_cycle_freq", addr)) + virtPort.write(addr, (uint64_t)(Clock::Frequency / + p->boot_cpu_frequency)); + + + /** + * EV5 only supports 127 ASNs so we are going to tell the kernel that the + * paritiuclar EV6 we have only supports 127 asns. + * @todo At some point we should change ev5.hh and the palcode to support + * 255 ASNs. + */ + if (kernelSymtab->findAddress("dp264_mv", addr)) + virtPort.write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127)); + else + panic("could not find dp264_mv\n"); + +#ifndef NDEBUG + kernelPanicEvent = addKernelFuncEvent("panic"); + if (!kernelPanicEvent) + panic("could not find kernel symbol \'panic\'"); + +#if 0 + kernelDieEvent = addKernelFuncEvent("die_if_kernel"); + if (!kernelDieEvent) + panic("could not find kernel symbol \'die_if_kernel\'"); +#endif + +#endif + + /** + * Any time ide_delay_50ms, calibarte_delay or + * determine_cpu_caches is called just skip the + * function. Currently determine_cpu_caches only is used put + * information in proc, however if that changes in the future we + * will have to fill in the cache size variables appropriately. + */ + + skipIdeDelay50msEvent = + addKernelFuncEvent("ide_delay_50ms"); + skipDelayLoopEvent = + addKernelFuncEvent("calibrate_delay"); + skipCacheProbeEvent = + addKernelFuncEvent("determine_cpu_caches"); + debugPrintkEvent = addKernelFuncEvent("dprintk"); + idleStartEvent = addKernelFuncEvent("cpu_idle"); + + // Disable for now as it runs into panic() calls in VPTr methods + // (see sim/vptr.hh). Once those bugs are fixed, we can + // re-enable, but we should find a better way to turn it on than + // using DTRACE(Thread), since looking at a trace flag at tick 0 + // leads to non-intuitive behavior with --trace-start. + if (false && kernelSymtab->findAddress("trips_switch_to", addr)) { + printThreadEvent = new PrintThreadInfo(&pcEventQueue, "threadinfo", + addr + sizeof(MachInst) * 6); + } else { + printThreadEvent = NULL; + } +} + +LinuxTripsSystem::~LinuxTripsSystem() +{ +#ifndef NDEBUG + delete kernelPanicEvent; +#endif + delete skipIdeDelay50msEvent; + delete skipDelayLoopEvent; + delete skipCacheProbeEvent; + delete debugPrintkEvent; + delete idleStartEvent; + delete printThreadEvent; +} + +void +LinuxTripsSystem::setDelayLoop(ThreadContext *tc) +{ + Addr addr = 0; + if (kernelSymtab->findAddress("loops_per_jiffy", addr)) { + Tick cpuFreq = tc->getCpuPtr()->frequency(); + Tick intrFreq = platform->intrFrequency(); + VirtualPort *vp; + + vp = tc->getVirtPort(); + vp->writeHtoG(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988)); + } +} + +void +LinuxTripsSystem::SkipDelayLoopEvent::process(ThreadContext *tc) +{ + SkipFuncEvent::process(tc); + // calculate and set loops_per_jiffy + ((LinuxTripsSystem *)tc->getSystemPtr())->setDelayLoop(tc); +} + +void +LinuxTripsSystem::PrintThreadInfo::process(ThreadContext *tc) +{ + Linux::ThreadInfo ti(tc); + + DPRINTF(Thread, "Currently Executing Thread %s, pid %d, started at: %d\n", + ti.curTaskName(), ti.curTaskPID(), ti.curTaskStart()); +} + +LinuxTripsSystem * +LinuxTripsSystemParams::create() +{ + return new LinuxTripsSystem(this); +} diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/linux/threadinfo.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/linux/threadinfo.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2004 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + * Nathan Binkert + */ + +#ifndef __ARCH_TRIPS_LINUX_LINUX_TREADNIFO_HH__ +#define __ARCH_TRIPS_LINUX_LINUX_TREADNIFO_HH__ + +#include "cpu/thread_context.hh" +#include "sim/system.hh" +#include "sim/vptr.hh" + +namespace Linux { + +class ThreadInfo +{ + private: + ThreadContext *tc; + System *sys; + Addr pcbb; + + template + bool + get_data(const char *symbol, T &data) + { + Addr addr = 0; + if (!sys->kernelSymtab->findAddress(symbol, addr)) + return false; + + CopyOut(tc, &data, addr, sizeof(T)); + + data = TripsISA::gtoh(data); + + return true; + } + + public: + ThreadInfo(ThreadContext *_tc, Addr _pcbb = 0) + : tc(_tc), sys(tc->getSystemPtr()), pcbb(_pcbb) + { + + } + ~ThreadInfo() + {} + + inline Addr + curThreadInfo() + { + Addr addr = pcbb; + Addr sp; + + if (!addr) + addr = tc->readMiscRegNoEffect(TripsISA::IPR_PALtemp23); + + FunctionalPort *p = tc->getPhysPort(); + p->readBlob(addr, (uint8_t *)&sp, sizeof(Addr)); + + return sp & ~ULL(0x3fff); + } + + inline Addr + curTaskInfo(Addr thread_info = 0) + { + int32_t offset; + if (!get_data("thread_info_task", offset)) + return 0; + + if (!thread_info) + thread_info = curThreadInfo(); + + Addr addr; + CopyOut(tc, &addr, thread_info + offset, sizeof(addr)); + + return addr; + } + + int32_t + curTaskPID(Addr thread_info = 0) + { + Addr offset; + if (!get_data("task_struct_pid", offset)) + return -1; + + int32_t pid; + CopyOut(tc, &pid, curTaskInfo(thread_info) + offset, sizeof(pid)); + + return pid; + } + + int64_t + curTaskStart(Addr thread_info = 0) + { + Addr offset; + if (!get_data("task_struct_start_time", offset)) + return -1; + + int64_t data; + // start_time is actually of type timespec, but if we just + // grab the first long, we'll get the seconds out of it + CopyOut(tc, &data, curTaskInfo(thread_info) + offset, sizeof(data)); + + return data; + } + + std::string + curTaskName(Addr thread_info = 0) + { + int32_t offset; + int32_t size; + + if (!get_data("task_struct_comm", offset)) + return "FailureIn_curTaskName"; + + if (!get_data("task_struct_comm_size", size)) + return "FailureIn_curTaskName"; + + char buffer[size + 1]; + CopyStringOut(tc, buffer, curTaskInfo(thread_info) + offset, size); + + return buffer; + } +}; + +} // namespace Linux + +#endif // __ARCH_TRIPS_LINUX_LINUX_THREADINFO_HH__ diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/locked_mem.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/locked_mem.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + */ + +#ifndef __ARCH_TRIPS_LOCKED_MEM_HH__ +#define __ARCH_TRIPS_LOCKED_MEM_HH__ + +/** + * @file + * + * ISA-specific helper functions for locked memory accesses. + * + * Note that these functions are not embedded in the ISA description + * because they operate on the *physical* address rather than the + * virtual address. In the current M5 design, the physical address is + * not accessible from the ISA description, only from the CPU model. + * Thus the CPU is responsible for calling back to the ISA (here) + * after the address translation has been performed to allow the ISA + * to do these manipulations based on the physical address. + */ + +#include "arch/trips/registers.hh" +#include "base/misc.hh" +#include "mem/request.hh" + +namespace TripsISA { + +template +inline void +handleLockedRead(XC *xc, Request *req) +{ + xc->setMiscRegNoEffect(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); + xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, true); +} + + +template +inline bool +handleLockedWrite(XC *xc, Request *req) +{ + if (req->isUncacheable()) { + // Funky Turbolaser mailbox access...don't update + // result register (see stq_c in decoder.isa) + req->setExtraData(2); + } else { + // standard store conditional + bool lock_flag = xc->readMiscRegNoEffect(MISCREG_LOCKFLAG); + Addr lock_addr = xc->readMiscRegNoEffect(MISCREG_LOCKADDR); + if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { + // Lock flag not set or addr mismatch in CPU; + // don't even bother sending to memory system + req->setExtraData(0); + xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, false); + // the rest of this code is not architectural; + // it's just a debugging aid to help detect + // livelock by warning on long sequences of failed + // store conditionals + int stCondFailures = xc->readStCondFailures(); + stCondFailures++; + xc->setStCondFailures(stCondFailures); + if (stCondFailures % 100000 == 0) { + warn("context %d: %d consecutive " + "store conditional failures\n", + xc->contextId(), stCondFailures); + } + + // store conditional failed already, so don't issue it to mem + return false; + } + } + + return true; +} + +} // namespace TripsISA + +#endif // __ARCH_TRIPS_LOCKED_MEM_HH__ diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/microcode_rom.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/microcode_rom.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2008 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_TRIPS_MICROCODE_ROM_HH__ +#define __ARCH_TRIPS_MICROCODE_ROM_HH__ + +#include "sim/microcode_rom.hh" + +namespace TripsISA +{ + // This file currently not used in TRIPS + using ::MicrocodeRom; +} + +#endif // __ARCH_TRIPS_MICROCODE_ROM_HH__ diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/pagetable.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/pagetable.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2002-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Steve Reinhardt + */ + +#ifndef __ARCH_TRIPS_PAGETABLE_H__ +#define __ARCH_TRIPS_PAGETABLE_H__ + +#include "arch/trips/isa_traits.hh" +#include "arch/trips/utility.hh" +#include "config/full_system.hh" + +namespace TripsISA { + +struct VAddr +{ + static const int ImplBits = 43; + static const Addr ImplMask = (ULL(1) << ImplBits) - 1; + static const Addr UnImplMask = ~ImplMask; + + Addr addr; + + VAddr(Addr a) : addr(a) {} + operator Addr() const { return addr; } + const VAddr &operator=(Addr a) { addr = a; return *this; } + + Addr vpn() const { return (addr & ImplMask) >> PageShift; } + Addr page() const { return addr & PageMask; } + Addr offset() const { return addr & PageOffset; } + + Addr level3() const + { return PteAddr(addr >> PageShift); } + Addr level2() const + { return PteAddr(addr >> (NPtePageShift + PageShift)); } + Addr level1() const + { return PteAddr(addr >> (2 * NPtePageShift + PageShift)); } +}; + +struct PageTableEntry +{ + PageTableEntry(uint64_t e) : entry(e) {} + uint64_t entry; + operator uint64_t() const { return entry; } + const PageTableEntry &operator=(uint64_t e) { entry = e; return *this; } + const PageTableEntry &operator=(const PageTableEntry &e) + { entry = e.entry; return *this; } + + Addr _pfn() const { return (entry >> 32) & 0xffffffff; } + Addr _sw() const { return (entry >> 16) & 0xffff; } + int _rsv0() const { return (entry >> 14) & 0x3; } + bool _uwe() const { return (entry >> 13) & 0x1; } + bool _kwe() const { return (entry >> 12) & 0x1; } + int _rsv1() const { return (entry >> 10) & 0x3; } + bool _ure() const { return (entry >> 9) & 0x1; } + bool _kre() const { return (entry >> 8) & 0x1; } + bool _nomb() const { return (entry >> 7) & 0x1; } + int _gh() const { return (entry >> 5) & 0x3; } + bool _asm_() const { return (entry >> 4) & 0x1; } + bool _foe() const { return (entry >> 3) & 0x1; } + bool _fow() const { return (entry >> 2) & 0x1; } + bool _for() const { return (entry >> 1) & 0x1; } + bool valid() const { return (entry >> 0) & 0x1; } + + Addr paddr() const { return _pfn() << PageShift; } +}; + +// ITB/DTB table entry +struct TlbEntry +{ + Addr tag; // virtual page number tag + Addr ppn; // physical page number + uint8_t xre; // read permissions - VMEM_PERM_* mask + uint8_t xwe; // write permissions - VMEM_PERM_* mask + uint8_t asn; // address space number + bool asma; // address space match + bool fonr; // fault on read + bool fonw; // fault on write + bool valid; // valid page table entry + + + //Construct an entry that maps to physical address addr. + TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr) + { + VAddr vaddr(_vaddr); + VAddr paddr(_paddr); + tag = vaddr.vpn(); + ppn = paddr.vpn(); + xre = 15; + xwe = 15; + asn = _asn; + asma = false; + fonr = false; + fonw = false; + valid = true; + } + + TlbEntry() + {} + + void + updateVaddr(Addr new_vaddr) + { + VAddr vaddr(new_vaddr); + tag = vaddr.vpn(); + } + + Addr + pageStart() + { + return ppn << PageShift; + } + + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); +}; + +} // namespace TripsISA + +#endif // __ARCH_TRIPS_PAGETABLE_H__ + diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/pagetable.cc --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/pagetable.cc Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2006-2007 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/trips/pagetable.hh" +#include "sim/serialize.hh" + +namespace TripsISA { + +void +TlbEntry::serialize(std::ostream &os) +{ + SERIALIZE_SCALAR(tag); + SERIALIZE_SCALAR(ppn); + SERIALIZE_SCALAR(xre); + SERIALIZE_SCALAR(xwe); + SERIALIZE_SCALAR(asn); + SERIALIZE_SCALAR(asma); + SERIALIZE_SCALAR(fonr); + SERIALIZE_SCALAR(fonw); + SERIALIZE_SCALAR(valid); +} + +void +TlbEntry::unserialize(Checkpoint *cp, const std::string §ion) +{ + UNSERIALIZE_SCALAR(tag); + UNSERIALIZE_SCALAR(ppn); + UNSERIALIZE_SCALAR(xre); + UNSERIALIZE_SCALAR(xwe); + UNSERIALIZE_SCALAR(asn); + UNSERIALIZE_SCALAR(asma); + UNSERIALIZE_SCALAR(fonr); + UNSERIALIZE_SCALAR(fonw); + UNSERIALIZE_SCALAR(valid); +} + +} //namespace TripsISA diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/predecoder.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/predecoder.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_TRIPS_PREDECODER_HH__ +#define __ARCH_TRIPS_PREDECODER_HH__ + +#include "arch/alpha/types.hh" +#include "base/misc.hh" +#include "base/types.hh" +#include "config/full_system.hh" + +class ThreadContext; + +namespace TripsISA { + +class Predecoder +{ + protected: + ThreadContext *tc; + + // The extended machine instruction being generated + ExtMachInst ext_inst; + + public: + Predecoder(ThreadContext * _tc) + : tc(_tc) + {} + + ThreadContext * + getTC() + { + return tc; + } + + void + setTC(ThreadContext * _tc) + { + tc = _tc; + } + + void + process() + { } + + void + reset() + { } + + // Use this to give data to the predecoder. This should be used + // when there is control flow. + void + moreBytes(Addr pc, Addr fetchPC, MachInst inst) + { + ext_inst = inst; +#if FULL_SYSTEM + ext_inst |= (static_cast(pc & 0x1) << 32); +#endif + } + + bool + needMoreBytes() + { + return true; + } + + bool + extMachInstReady() + { + return true; + } + + // This returns a constant reference to the ExtMachInst to avoid a copy + const ExtMachInst & + getExtMachInst() + { + return ext_inst; + } +}; + +} // namespace TripsISA + +#endif // __ARCH_TRIPS_PREDECODER_HH__ diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/process.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/process.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + * Ali Saidi + */ + +#ifndef __ARCH_TRIPS_PROCESS_HH__ +#define __ARCH_TRIPS_PROCESS_HH__ + +#include "sim/process.hh" + +class TripsLiveProcess : public LiveProcess +{ + protected: + TripsLiveProcess(LiveProcessParams *params, ObjectFile *objFile); + + void startup(); + + void argsInit(int intSize, int pageSize); + + public: + TripsISA::IntReg getSyscallArg(ThreadContext *tc, int &i); + void setSyscallArg(ThreadContext *tc, int i, TripsISA::IntReg val); + void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value); +}; + +#endif // __ARCH_TRIPS_PROCESS_HH__ diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/process.cc --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/process.cc Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + * Ali Saidi + */ + +#include + +#include "arch/trips/isa_traits.hh" +#include "arch/trips/process.hh" +#include "base/loader/object_file.hh" +#include "base/loader/elf_object.hh" +#include "base/misc.hh" +#include "cpu/thread_context.hh" +#include "mem/page_table.hh" +#include "sim/process_impl.hh" +#include "sim/system.hh" + +using namespace TripsISA; +using namespace std; + +TripsLiveProcess::TripsLiveProcess(LiveProcessParams *params, + ObjectFile *objFile) + : LiveProcess(params, objFile) +{ + brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); + brk_point = roundUp(brk_point, VMPageSize); + + // Set up stack. On TRIPS, stack on top of the virtual address space. + // This code should get moved to some architecture-specific spot. + stack_base = 0xFFFFFFFFULL; + + mmap_start = mmap_end = 0x10000; + + // Set pointer for next thread stack. Reserve 8M for main stack. + next_thread_stack_base = stack_base - (8 * 1024 * 1024); + +} + +void +TripsLiveProcess::argsInit(int intSize, int pageSize) +{ + objFile->loadSections(initVirtMem); + + typedef AuxVector auxv_t; + std::vector auxv; + + ElfObject * elfObject = dynamic_cast(objFile); + if(elfObject) + { + // modern glibc uses a bunch of auxiliary vectors to set up + // TLS as well as do a bunch of other stuff + // these vectors go on the bottom of the stack, below argc/argv/envp + // pointers but above actual arg strings + // I don't have all the ones glibc looks at here, but so far it doesn't + // seem to be a problem. + // check out _dl_aux_init() in glibc/elf/dl-support.c for details + // --Lisa + auxv.push_back(auxv_t(M5_AT_PAGESZ, TripsISA::VMPageSize)); + auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); + auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); + DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable()); + auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); + auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); + auxv.push_back(auxv_t(M5_AT_UID, uid())); + auxv.push_back(auxv_t(M5_AT_EUID, euid())); + auxv.push_back(auxv_t(M5_AT_GID, gid())); + auxv.push_back(auxv_t(M5_AT_EGID, egid())); + + } + + // Calculate how much space we need for arg & env & auxv arrays. + int argv_array_size = intSize * (argv.size() + 1); + int envp_array_size = intSize * (envp.size() + 1); + int auxv_array_size = intSize * 2 * (auxv.size() + 1); + + int arg_data_size = 0; + for (vector::size_type i = 0; i < argv.size(); ++i) { + arg_data_size += argv[i].size() + 1; + } + int env_data_size = 0; + for (vector::size_type i = 0; i < envp.size(); ++i) { + env_data_size += envp[i].size() + 1; + } + + int space_needed = + argv_array_size + + envp_array_size + + auxv_array_size + + arg_data_size + + env_data_size; + + if (space_needed < 32*1024) + space_needed = 32*1024; + + // set bottom of stack + stack_min = stack_base - space_needed; + // align it + stack_min = roundDown(stack_min, pageSize); + stack_size = stack_base - stack_min; + // map memory + + //hack + //stack_min = 0xFFFFDFF8ULL; + pTable->allocate(stack_min, roundUp(stack_size, pageSize)); + + // map out initial stack contents + Addr argv_array_base = stack_min + intSize; // room for argc + Addr envp_array_base = argv_array_base + argv_array_size; + Addr auxv_array_base = envp_array_base + envp_array_size; + Addr arg_data_base = auxv_array_base + auxv_array_size; + Addr env_data_base = arg_data_base + arg_data_size; + + // write contents to stack + uint64_t argc = argv.size(); + uint64_t argc_mem = 0; + if (intSize == 8) + argc_mem = htog((uint64_t)argc); + else if (intSize == 4) + argc_mem = htog((uint32_t)argc); + else + panic("Unknown int size"); + + initVirtMem->writeBlob(stack_min, (uint8_t*)&argc_mem, intSize); + + copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); + copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); + + //Copy the aux stuff + for (vector::size_type x = 0; x < auxv.size(); x++) { + initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize, + (uint8_t*)&(auxv[x].a_type), intSize); + initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize, + (uint8_t*)&(auxv[x].a_val), intSize); + } + + ThreadContext *tc = system->getThreadContext(contextIds[0]); + + setSyscallArg(tc, 0, argc); + setSyscallArg(tc, 1, argv_array_base); + setSyscallArg(tc, 2, envp_array_base); + tc->setIntReg(StackPointerReg, stack_min); + + Addr prog_entry = objFile->entryPoint(); + + //tc->setPC(prog_entry); + // Set block PC in commit instead of setting PC in fetch + tc->setBlockPC(prog_entry); + + //tc->setNextPC(prog_entry + sizeof(MachInst)); + + // MIPS/Sparc need NNPC for delay slot handling, while + // TRIPS has no delay slots... However, CPU models + // cycle PCs by PC=NPC, NPC=NNPC, etc. so setting this + // here ensures CPU-Model Compatibility across board + //tc->setNextNPC(prog_entry + (2 * sizeof(MachInst))); +} + +void +TripsLiveProcess::startup() +{ + if (checkpointRestored) + return; + + Process::startup(); + + argsInit(MachineBytes, VMPageSize); + + //ThreadContext *tc = system->getThreadContext(contextIds[0]); + //tc->setIntReg(GlobalPointerReg, objFile->globalPointer()); +} + +TripsISA::IntReg +TripsLiveProcess::getSyscallArg(ThreadContext *tc, int &i) +{ + assert(i < 10); + return tc->readIntReg(FirstArgumentReg + i++); +} + +void +TripsLiveProcess::setSyscallArg(ThreadContext *tc, + int i, TripsISA::IntReg val) +{ + assert(i < 10); + tc->setIntReg(FirstArgumentReg + i, val); +} + +void +TripsLiveProcess::setSyscallReturn(ThreadContext *tc, + SyscallReturn return_value) +{ + // check for error condition. TRIPS syscall convention put + // the syscall return value to r3. + // + // There seems no syscall successful reg in TRIPS ... + // In TRIPS abi doc, it looks r3 performce as a syscall + // successful reg because it says r3 will be set to 0 if + // syscall success, but in the same time it says syscall + // return value will put into r3. It's confusing ... + // With observation of tsim_arch, it looks r3 will be set + // as the syscall return value. I respect this ... + // Moreover, r4 will be set as the error code while there's + // an error occurs during syscall + if (return_value.successful()) { + // no error + //tc->setIntReg(SyscallSuccessReg, 0); + tc->setIntReg(SyscallReturnValueReg, return_value.value()); + } else { + // got an error, return details + //tc->setIntReg(SyscallSuccessReg, (IntReg)-1); + tc->setIntReg(SyscallReturnValueReg, return_value.value()); + // Set syscall error code reg with host error code + tc->setIntReg(SyscallErrorCodeReg, errno); + } +} diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/registers.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/registers.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_TRIPS_REGISTERS_HH__ +#define __ARCH_TRIPS_REGISTERS_HH__ + +#include "arch/trips/max_inst_regs.hh" +#include "base/types.hh" + +namespace TripsISA { + +using TripsISAInst::MaxInstSrcRegs; +using TripsISAInst::MaxInstDestRegs; +using TripsISAInst::MaxInstConsumers; +using TripsISAInst::MaxInstOperands; + +typedef uint8_t RegIndex; +typedef uint64_t IntReg; + +// floating point register file entry type +typedef double FloatReg; +typedef uint64_t FloatRegBits; + +// control register file contents +typedef uint64_t MiscReg; + +// This is the fraction bits mask +const uint64_t FMASK_D = 0xFFF0000000000000ULL; +const uint32_t FMASK_S = 0xFF800000; + +const uint8_t EXPH_D = 62; +const uint8_t EXPL_D = 52; +const uint8_t EXPH_S = 30; +const uint8_t EXPL_S = 23; + +union AnyReg +{ + IntReg intreg; + FloatReg fpreg; + MiscReg ctrlreg; +}; + +enum MiscRegIndex +{ + MISCREG_FPCR = 1, // Fix me + MISCREG_UNIQ, + MISCREG_LOCKFLAG, + MISCREG_LOCKADDR, + MISCREG_INTR +}; + +// There's no zero reg in trips, so set the reg number to some kind of dummy number +const RegIndex ZeroReg = 128; + +// the rest of these depend on the ABI +const RegIndex StackPointerReg = 1; +//const RegIndex GlobalPointerReg = 11; +//const RegIndex ProcedureValueReg = 27; +const RegIndex ReturnAddressReg = 2; +const RegIndex ReturnValueReg = 3; +const RegIndex FramePointerReg = 12; + +const RegIndex SyscallNumReg = 0; +const RegIndex FirstArgumentReg = 3; +const RegIndex SyscallPseudoReturnReg = 4; +const RegIndex SyscallSuccessReg = 3; +const RegIndex SyscallReturnValueReg = 3; +const RegIndex SyscallErrorCodeReg = 4; + +const int NumIntArchRegs = 128; +//const int NumPALShadowRegs = 8; +const int NumFloatArchRegs = 128; +// @todo: Figure out what this number really should be. +const int NumMiscArchRegs = 77; + +const int NumIntRegs = NumIntArchRegs; +const int NumFloatRegs = NumFloatArchRegs; +const int NumMiscRegs = NumMiscArchRegs ; + +const int TotalNumRegs = + NumIntRegs + NumFloatRegs + NumMiscRegs; + +const int TotalDataRegs = NumIntRegs + NumFloatRegs; + +// These enumerate all the registers for dependence tracking. +enum DependenceTags { + // 0..31 are the integer regs 0..31 + // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) + FP_Base_DepTag = 40, + Ctrl_Base_DepTag = 72 +}; + +} // namespace TripsISA + +#endif // __ARCH_TRIPS_REGFILE_HH__ diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/regredir.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/regredir.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2003-2009 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_TRIPS_REGREDIR_HH__ +#define __ARCH_TRIPS_REGREDIR_HH__ + +#include "arch/trips/registers.hh" + +namespace TripsISA { + +// redirected register map, really only used for the full system case. +extern const int reg_redir[NumIntRegs]; + +} // namespace TripsISA + +#endif // __ARCH_TRIPS_REGREDIR_HH__ diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/regredir.cc --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/regredir.cc Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2003-2009 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + * Gabe Black + * Kevin Lim + */ + +#include "arch/trips/regredir.hh" +#include "config/full_system.hh" + +namespace TripsISA { + +#if FULL_SYSTEM +const int reg_redir[NumIntRegs] = { + /* 0 */ 0, 1, 2, 3, 4, 5, 6, 7, + /* 8 */ 32, 33, 34, 35, 36, 37, 38, 15, + /* 16 */ 16, 17, 18, 19, 20, 21, 22, 23, + /* 24 */ 24, 39, 26, 27, 28, 29, 30, 31 }; +#else +const int reg_redir[NumIntRegs] = { + /* 0 */ 0, 1, 2, 3, 4, 5, 6, 7, + /* 8 */ 8, 9, 10, 11, 12, 13, 14, 15, + /* 16 */ 16, 17, 18, 19, 20, 21, 22, 23, + /* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 }; +#endif + +} // namespace TripsISA diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/remote_gdb.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/remote_gdb.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2007 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + */ + +#ifndef __ARCH_TRIPS_REMOTE_GDB_HH__ +#define __ARCH_TRIPS_REMOTE_GDB_HH__ + +#include "base/remote_gdb.hh" + +namespace TripsISA +{ + class RemoteGDB : public BaseRemoteGDB + { + public: + //These needs to be written to suit TRIPS + + RemoteGDB(System *system, ThreadContext *context) + : BaseRemoteGDB(system, context, 1) + {} + + bool acc(Addr, size_t) + { panic("acc not implemented for TRIPS!"); } + + void getregs() + { panic("getregs not implemented for TRIPS!"); } + + void setregs() + { panic("setregs not implemented for TRIPS!"); } + + void clearSingleStep() + { panic("clearSingleStep not implemented for TRIPS!"); } + + void setSingleStep() + { panic("setSingleStep not implemented for TRIPS!"); } + }; +} + +#endif /* __ARCH_ALPHA_REMOTE_GDB_H__ */ diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/stacktrace.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/stacktrace.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + */ + +#ifndef __ARCH_TRIPS_STACKTRACE_HH__ +#define __ARCH_TRIPS_STACKTRACE_HH__ + +#include "base/trace.hh" +#include "cpu/edge/static_inst.hh" + +class ThreadContext; + +namespace TripsISA { + +class StackTrace; + +class ProcessInfo +{ + private: + ThreadContext *tc; + + int thread_info_size; + int task_struct_size; + int task_off; + int pid_off; + int name_off; + + public: + ProcessInfo(ThreadContext *_tc); + + Addr task(Addr ksp) const; + int pid(Addr ksp) const; + std::string name(Addr ksp) const; +}; + +class StackTrace +{ + private: + ThreadContext *tc; + std::vector stack; + + private: + bool isEntry(Addr addr); + bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra); + bool decodeSave(MachInst inst, int ®, int &disp); + bool decodeStack(MachInst inst, int &disp); + + void trace(ThreadContext *tc, bool is_call); + + public: + StackTrace(); + StackTrace(ThreadContext *tc, StaticInstPtr inst); + ~StackTrace(); + + void + clear() + { + tc = 0; + stack.clear(); + } + + bool valid() const { return tc != NULL; } + bool trace(ThreadContext *tc, StaticInstPtr inst); + + public: + const std::vector &getstack() const { return stack; } + + enum { + user = 1, + console = 2, + unknown = 3 + }; + +#if TRACING_ON + private: + void dump(); + + public: + void dprintf() { if (DTRACE(Stack)) dump(); } +#else + public: + void dprintf() {} +#endif +}; + +inline bool +StackTrace::trace(ThreadContext *tc, StaticInstPtr inst) +{ + if (!inst->isCall() && !inst->isReturn()) + return false; + + if (valid()) + clear(); + + trace(tc, !inst->isReturn()); + return true; +} + +} // namespace TripsISA + +#endif // __ARCH_TRIPS_STACKTRACE_HH__ diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/stacktrace.cc --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/stacktrace.cc Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,349 @@ +/* + * Copyright (c) 2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + */ + +#include + +#include "arch/trips/isa_traits.hh" +#include "arch/trips/stacktrace.hh" +#include "arch/trips/vtophys.hh" +#include "base/bitfield.hh" +#include "base/trace.hh" +#include "cpu/base.hh" +#include "cpu/edge/thread_context.hh" +#include "sim/system.hh" + +using namespace std; + +namespace TripsISA { + +ProcessInfo::ProcessInfo(ThreadContext *_tc) + : tc(_tc) +{ + Addr addr = 0; + VirtualPort *vp = tc->getVirtPort(); + SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; + + if (!symtab->findAddress("thread_info_size", addr)) + panic("thread info not compiled into kernel\n"); + thread_info_size = vp->readGtoH(addr); + + if (!symtab->findAddress("task_struct_size", addr)) + panic("thread info not compiled into kernel\n"); + task_struct_size = vp->readGtoH(addr); + + if (!symtab->findAddress("thread_info_task", addr)) + panic("thread info not compiled into kernel\n"); + task_off = vp->readGtoH(addr); + + if (!symtab->findAddress("task_struct_pid", addr)) + panic("thread info not compiled into kernel\n"); + pid_off = vp->readGtoH(addr); + + if (!symtab->findAddress("task_struct_comm", addr)) + panic("thread info not compiled into kernel\n"); + name_off = vp->readGtoH(addr); +} + +Addr +ProcessInfo::task(Addr ksp) const +{ + Addr base = ksp & ~0x3fff; + if (base == ULL(0xfffffc0000000000)) + return 0; + + Addr tsk; + + VirtualPort *vp; + + vp = tc->getVirtPort(); + tsk = vp->readGtoH(base + task_off); + + return tsk; +} + +int +ProcessInfo::pid(Addr ksp) const +{ + Addr task = this->task(ksp); + if (!task) + return -1; + + uint16_t pd; + + VirtualPort *vp; + + vp = tc->getVirtPort(); + pd = vp->readGtoH(task + pid_off); + + return pd; +} + +string +ProcessInfo::name(Addr ksp) const +{ + Addr task = this->task(ksp); + if (!task) + return "console"; + + char comm[256]; + CopyStringOut(tc, comm, task + name_off, sizeof(comm)); + if (!comm[0]) + return "startup"; + + return comm; +} + +StackTrace::StackTrace() + : tc(0), stack(64) +{ +} + +StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst) + : tc(0), stack(64) +{ + trace(_tc, inst); +} + +StackTrace::~StackTrace() +{ +} + +void +StackTrace::trace(ThreadContext *_tc, bool is_call) +{ + tc = _tc; + + System *sys = tc->getSystemPtr(); + + bool usermode = + (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0; + + Addr pc = tc->readNextPC(); + bool kernel = sys->kernelStart <= pc && pc <= sys->kernelEnd; + + if (usermode) { + stack.push_back(user); + return; + } + + if (!kernel) { + stack.push_back(console); + return; + } + + SymbolTable *symtab = sys->kernelSymtab; + Addr ksp = tc->readIntReg(StackPointerReg); + Addr bottom = ksp & ~0x3fff; + + if (is_call) { + Addr addr; + if (!symtab->findNearestAddr(pc, addr)) + panic("could not find address %#x", pc); + + stack.push_back(addr); + pc = tc->readPC(); + } + + while (ksp > bottom) { + Addr addr; + if (!symtab->findNearestAddr(pc, addr)) + panic("could not find symbol for pc=%#x", pc); + assert(pc >= addr && "symbol botch: callpc < func"); + + stack.push_back(addr); + + if (isEntry(addr)) + return; + + Addr ra; + int size; + if (decodePrologue(ksp, pc, addr, size, ra)) { + if (!ra) + return; + + if (size <= 0) { + stack.push_back(unknown); + return; + } + + pc = ra; + ksp += size; + } else { + stack.push_back(unknown); + return; + } + + bool kernel = sys->kernelStart <= pc && pc <= sys->kernelEnd; + if (!kernel) + return; + + if (stack.size() >= 1000) + panic("unwinding too far"); + } + + panic("unwinding too far"); +} + +bool +StackTrace::isEntry(Addr addr) +{ + panic("StackTrace::isEntry unimplemented yet!\n"); + return false; +} + +bool +StackTrace::decodeStack(MachInst inst, int &disp) +{ + // lda $sp, -disp($sp) + // + // Opcode<31:26> == 0x08 + // RA<25:21> == 30 + // RB<20:16> == 30 + // Disp<15:0> + const MachInst mem_mask = 0xffff0000; + const MachInst lda_pattern = 0x23de0000; + const MachInst lda_disp_mask = 0x0000ffff; + + // subq $sp, disp, $sp + // addq $sp, disp, $sp + // + // Opcode<31:26> == 0x10 + // RA<25:21> == 30 + // Lit<20:13> + // One<12> = 1 + // Func<11:5> == 0x20 (addq) + // Func<11:5> == 0x29 (subq) + // RC<4:0> == 30 + const MachInst intop_mask = 0xffe01fff; + const MachInst addq_pattern = 0x43c0141e; + const MachInst subq_pattern = 0x43c0153e; + const MachInst intop_disp_mask = 0x001fe000; + const int intop_disp_shift = 13; + + if ((inst & mem_mask) == lda_pattern) + disp = -sext<16>(inst & lda_disp_mask); + else if ((inst & intop_mask) == addq_pattern) + disp = -int((inst & intop_disp_mask) >> intop_disp_shift); + else if ((inst & intop_mask) == subq_pattern) + disp = int((inst & intop_disp_mask) >> intop_disp_shift); + else + return false; + + return true; +} + +bool +StackTrace::decodeSave(MachInst inst, int ®, int &disp) +{ + // lda $stq, disp($sp) + // + // Opcode<31:26> == 0x08 + // RA<25:21> == ? + // RB<20:16> == 30 + // Disp<15:0> + const MachInst stq_mask = 0xfc1f0000; + const MachInst stq_pattern = 0xb41e0000; + const MachInst stq_disp_mask = 0x0000ffff; + const MachInst reg_mask = 0x03e00000; + const int reg_shift = 21; + + if ((inst & stq_mask) == stq_pattern) { + reg = (inst & reg_mask) >> reg_shift; + disp = sext<16>(inst & stq_disp_mask); + } else { + return false; + } + + return true; +} + +/* + * Decode the function prologue for the function we're in, and note + * which registers are stored where, and how large the stack frame is. + */ +bool +StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, int &size, + Addr &ra) +{ + size = 0; + ra = 0; + + for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) { + MachInst inst; + CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst)); + + int reg, disp; + if (decodeStack(inst, disp)) { + if (size) { + // panic("decoding frame size again"); + return true; + } + size += disp; + } else if (decodeSave(inst, reg, disp)) { + if (!ra && reg == ReturnAddressReg) { + CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr)); + if (!ra) { + // panic("no return address value pc=%#x\n", pc); + return false; + } + } + } + } + + return true; +} + +#if TRACING_ON +void +StackTrace::dump() +{ + StringWrap name(tc->getCpuPtr()->name()); + SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; + + DPRINTFN("------ Stack ------\n"); + + string symbol; + for (int i = 0, size = stack.size(); i < size; ++i) { + Addr addr = stack[size - i - 1]; + if (addr == user) + symbol = "user"; + else if (addr == console) + symbol = "console"; + else if (addr == unknown) + symbol = "unknown"; + else + symtab->findSymbol(addr, symbol); + + DPRINTFN("%#x: %s\n", addr, symbol); + } +} +#endif + +} // namespace TripsISA diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/tlb.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/tlb.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2001-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Steve Reinhardt + */ + +#ifndef __ARCH_TRIPS_TLB_HH__ +#define __ARCH_TRIPS_TLB_HH__ + +#include + +#include "arch/trips/isa_traits.hh" +#include "arch/trips/pagetable.hh" +#include "arch/trips/utility.hh" +#include "arch/trips/vtophys.hh" +#include "base/statistics.hh" +#include "mem/request.hh" +#include "params/TripsTLB.hh" +#include "sim/faults.hh" +#include "sim/tlb.hh" + +class ThreadContext; + +namespace TripsISA { + +class TLB : public BaseTLB +{ + protected: + mutable Stats::Scalar fetch_hits; + mutable Stats::Scalar fetch_misses; + mutable Stats::Scalar fetch_acv; + mutable Stats::Formula fetch_accesses; + mutable Stats::Scalar read_hits; + mutable Stats::Scalar read_misses; + mutable Stats::Scalar read_acv; + mutable Stats::Scalar read_accesses; + mutable Stats::Scalar write_hits; + mutable Stats::Scalar write_misses; + mutable Stats::Scalar write_acv; + mutable Stats::Scalar write_accesses; + Stats::Formula data_hits; + Stats::Formula data_misses; + Stats::Formula data_acv; + Stats::Formula data_accesses; + + typedef std::multimap PageTable; + PageTable lookupTable; // Quick lookup into page table + + TlbEntry *table; // the Page Table + int size; // TLB Size + int nlu; // not last used entry (for replacement) + + void nextnlu() { if (++nlu >= size) nlu = 0; } + TlbEntry *lookup(Addr vpn, uint8_t asn); + + public: + typedef TripsTLBParams Params; + TLB(const Params *p) ; + virtual ~TLB(); + + virtual void regStats(); + + int getsize() const { return size; } + + TlbEntry &index(bool advance = true); + void insert(Addr vaddr, TlbEntry &entry); + + void flushAll(); + void flushProcesses(); + void flushAddr(Addr addr, uint8_t asn); + + void + demapPage(Addr vaddr, uint64_t asn) + { + assert(asn < (1 << 8)); + flushAddr(vaddr, asn); + } + + // static helper functions... really EV5 VM traits + static bool + validVirtualAddress(Addr vaddr) + { + panic("TLB::validVirtualAddress unimplemented yet!\n"); + return false; + } + + static Fault checkCacheability(RequestPtr &req, bool itb = false); + + // Checkpointing + virtual void serialize(std::ostream &os); + virtual void unserialize(Checkpoint *cp, const std::string §ion); + + // Most recently used page table entries + TlbEntry *EntryCache[3]; + inline void + flushCache() + { + memset(EntryCache, 0, 3 * sizeof(TlbEntry*)); + } + + inline TlbEntry * + updateCache(TlbEntry *entry) { + EntryCache[2] = EntryCache[1]; + EntryCache[1] = EntryCache[0]; + EntryCache[0] = entry; + return entry; + } + + protected: + Fault translateData(RequestPtr req, ThreadContext *tc, bool write); + Fault translateInst(RequestPtr req, ThreadContext *tc); + + public: + Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); + void translateTiming(RequestPtr req, ThreadContext *tc, + Translation *translation, Mode mode); +}; + +} // namespace TripsISA + +#endif // __ARCH_TRIPS_TLB_HH__ diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/tlb.cc --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/tlb.cc Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2001-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Steve Reinhardt + * Andrew Schultz + */ + +#include +#include + +#include "arch/trips/tlb.hh" +#include "arch/trips/faults.hh" +#include "sim/process.hh" +#include "mem/page_table.hh" + +using namespace std; +using namespace TripsISA; + +/////////////////////////////////////////////////////////////////////// +// +// TRIPS TLB +// +#define MODE2MASK(X) (1 << (X)) + +TLB::TLB(const Params *p) + : BaseTLB(p), size(p->size), nlu(0) +{ + table = new TlbEntry[size]; + memset(table, 0, sizeof(TlbEntry[size])); + flushCache(); +} + +TLB::~TLB() +{ + if (table) + delete [] table; +} + +void +TLB::regStats() +{ + fetch_hits + .name(name() + ".fetch_hits") + .desc("ITB hits"); + fetch_misses + .name(name() + ".fetch_misses") + .desc("ITB misses"); + fetch_acv + .name(name() + ".fetch_acv") + .desc("ITB acv"); + fetch_accesses + .name(name() + ".fetch_accesses") + .desc("ITB accesses"); + + fetch_accesses = fetch_hits + fetch_misses; + + read_hits + .name(name() + ".read_hits") + .desc("DTB read hits") + ; + + read_misses + .name(name() + ".read_misses") + .desc("DTB read misses") + ; + + read_acv + .name(name() + ".read_acv") + .desc("DTB read access violations") + ; + + read_accesses + .name(name() + ".read_accesses") + .desc("DTB read accesses") + ; + + write_hits + .name(name() + ".write_hits") + .desc("DTB write hits") + ; + + write_misses + .name(name() + ".write_misses") + .desc("DTB write misses") + ; + + write_acv + .name(name() + ".write_acv") + .desc("DTB write access violations") + ; + + write_accesses + .name(name() + ".write_accesses") + .desc("DTB write accesses") + ; + + data_hits + .name(name() + ".data_hits") + .desc("DTB hits") + ; + + data_misses + .name(name() + ".data_misses") + .desc("DTB misses") + ; + + data_acv + .name(name() + ".data_acv") + .desc("DTB access violations") + ; + + data_accesses + .name(name() + ".data_accesses") + .desc("DTB accesses") + ; + + data_hits = read_hits + write_hits; + data_misses = read_misses + write_misses; + data_acv = read_acv + write_acv; + data_accesses = read_accesses + write_accesses; +} + +// look up an entry in the TLB +TlbEntry * +TLB::lookup(Addr vpn, uint8_t asn) +{ + panic("TLB::lookup unimplemented yet!\n"); + return NULL; +} + +Fault +TLB::checkCacheability(RequestPtr &req, bool itb) +{ + warn("TLB::checkCacheability unimplemented yet!\n"); + return NoFault; +} + + +// insert a new TLB entry +void +TLB::insert(Addr addr, TlbEntry &entry) +{ + panic("TLB::insert unimplemented yet!\n"); +} + +void +TLB::flushAll() +{ + panic("TLB::flushAll unimplemented yet!\n"); +} + +void +TLB::flushProcesses() +{ + panic("TLB::flushProcesses unimplemented yet!\n"); +} + +void +TLB::flushAddr(Addr addr, uint8_t asn) +{ + panic("TLB::flushAddr unimplemented yet!\n"); +} + + +void +TLB::serialize(ostream &os) +{ +} + +void +TLB::unserialize(Checkpoint *cp, const string §ion) +{ +} + +Fault +TLB::translateInst(RequestPtr req, ThreadContext *tc) +{ + Process * p = tc->getProcessPtr(); + + Fault fault = p->pTable->translate(req); + if (fault != NoFault) + return fault; + + return NoFault; + +} + +Fault +TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) +{ + DPRINTF(TLB, "size = %d.\n",req->getSize()); + if (req->getVaddr() & (req->getSize() - 1)) { + DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), + req->getSize()); + return new TripsFault(); + } + + + Process * p = tc->getProcessPtr(); + + Fault fault = p->pTable->translate(req); + if (fault != NoFault) + return fault; + + return NoFault; +} + +TlbEntry & +TLB::index(bool advance) +{ + TlbEntry *entry = &table[nlu]; + + if (advance) + nextnlu(); + + return *entry; +} + +Fault +TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) +{ + DPRINTF(TLB,"atomic size = %d.\n",req->getSize()); + if (mode == Execute) + return translateInst(req, tc); + else + return translateData(req, tc, mode == Write); +} + +void +TLB::translateTiming(RequestPtr req, ThreadContext *tc, + Translation *translation, Mode mode) +{ + assert(translation); + translation->finish(translateAtomic(req, tc, mode), req, tc, mode); +} + + +TripsISA::TLB * +TripsTLBParams::create() +{ + return new TripsISA::TLB(this); +} diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/types.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/types.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Steve Reinhardt + */ + +#ifndef __ARCH_TRIPS_TYPES_HH__ +#define __ARCH_TRIPS_TYPES_HH__ + +#include "base/types.hh" + +namespace TripsISA { + +typedef uint32_t MachInst; +typedef uint64_t ExtMachInst; + +typedef uint64_t LargestRead; + +enum annotes +{ + ANNOTE_NONE = 0, + // An impossible number for instruction annotations + ITOUCH_ANNOTE = 0xffffffff, +}; + +struct CoreSpecific +{ + int core_type; +}; + +} // namespace TripsISA + +#endif // __ARCH_TRIPS_TYPES_HH__ diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/utility.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/utility.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Steve Reinhardt + */ + +#ifndef __ARCH_TRIPS_UTILITY_HH__ +#define __ARCH_TRIPS_UTILITY_HH__ + +#include "arch/trips/types.hh" +#include "arch/trips/isa_traits.hh" +#include "arch/trips/registers.hh" +#include "base/misc.hh" +#include "config/full_system.hh" +#include "cpu/thread_context.hh" + +namespace TripsISA { + +uint64_t getArgument(ThreadContext *tc, int number, bool fp); + +// Trips has a little difference with ieee754 standard in float-point +inline void checkFloat64(uint64_t &input) +{ + uint32_t exp = bits(input, EXPH_D, EXPL_D); + + if ( exp == 0x0 || exp == 0x7FF ) input &= FMASK_D; +} + +inline void checkFloat32( uint64_t &input ) +{ + uint32_t exp = bits(input, EXPH_S, EXPL_S); + + if ( exp == 0x0 || exp == 0xFF ) input &= FMASK_S; +} + +inline bool +inUserMode(ThreadContext *tc) +{ + panic("inUserMode Unimplemented!\n"); + return false; +} + +inline bool +isCallerSaveIntegerRegister(unsigned int reg) +{ + panic("register classification not implemented"); + return (reg >= 1 && reg <= 8) || (reg >= 22 && reg <= 25) || reg == 27; +} + +inline bool +isCalleeSaveIntegerRegister(unsigned int reg) +{ + panic("register classification not implemented"); + return reg >= 9 && reg <= 15; +} + +inline bool +isCallerSaveFloatRegister(unsigned int reg) +{ + panic("register classification not implemented"); + return false; +} + +inline bool +isCalleeSaveFloatRegister(unsigned int reg) +{ + panic("register classification not implemented"); + return false; +} + +inline Addr +alignAddress(const Addr &addr, unsigned int nbytes) +{ + return (addr & ~(nbytes - 1)); +} + +// Instruction address compression hooks +inline Addr +realPCToFetchPC(const Addr &addr) +{ + return addr; +} + +inline Addr +fetchPCToRealPC(const Addr &addr) +{ + return addr; +} + +// the size of "fetched" instructions (not necessarily the size +// of real instructions for PISA) +inline size_t +fetchInstSize() +{ + return sizeof(MachInst); +} + +inline MachInst +makeRegisterCopy(int dest, int src) +{ + panic("makeRegisterCopy not implemented"); + return 0; +} + +/** + * Function to insure ISA semantics about 0 registers. + * @param tc The thread context. + */ +template +void zeroRegisters(TC *tc); + +// Alpha IPR register accessors +inline bool PcPAL(Addr addr) { return addr & 0x3; } +inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); } + +//////////////////////////////////////////////////////////////////////// +// +// Translation stuff +// + +inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } + +// User Virtual +inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } + +// Kernel Direct Mapped +inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } +inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; } + +// Kernel Virtual +inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; } + +inline Addr +TruncPage(Addr addr) +{ return addr & ~(PageBytes - 1); } + +inline Addr +RoundPage(Addr addr) +{ return (addr + PageBytes - 1) & ~(PageBytes - 1); } + +void initIPRs(ThreadContext *tc, int cpuId); +#if FULL_SYSTEM +void initCPU(ThreadContext *tc, int cpuId); + +/** + * Function to check for and process any interrupts. + * @param tc The thread context. + */ +template +void processInterrupts(TC *tc); +#endif + +void copyRegs(ThreadContext *src, ThreadContext *dest); + +void copyMiscRegs(ThreadContext *src, ThreadContext *dest); + + + +} // namespace AlphaISA + +#endif // __ARCH_TRIPS_UTILITY_HH__ diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/utility.cc --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/utility.cc Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Ali Saidi + */ + +#include "arch/trips/utility.hh" + +namespace TripsISA { + +uint64_t +getArgument(ThreadContext *tc, int number, bool fp) +{ + panic("getArgument() is Full system only\n"); + M5_DUMMY_RETURN; +} + +void +copyRegs(ThreadContext *src, ThreadContext *dest) +{ + panic("copyRegs unimplemented yet!\n"); +} + +void +copyMiscRegs(ThreadContext *src, ThreadContext *dest) +{ + panic("copyMiscRegs unimplemented yet!\n"); +} + +} // namespace AlphaISA + diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/vtophys.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/vtophys.hh Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2002-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Steve Reinhardt + */ + +#ifndef __ARCH_TRIPS_VTOPHYS_H__ +#define __ARCH_TRIPS_VTOPHYS_H__ + +#include "arch/trips/isa_traits.hh" +#include "arch/trips/pagetable.hh" +#include "arch/trips/utility.hh" + +class ThreadContext; +class FunctionalPort; + +namespace TripsISA { + +PageTableEntry kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, + VAddr vaddr); + +Addr vtophys(Addr vaddr); +Addr vtophys(ThreadContext *tc, Addr vaddr); + +} // namespace TripsISA + +#endif // __ARCH_TRIPS_VTOPHYS_H__ + diff -r edde97a6ea7c -r 9bb72531ffd5 src/arch/trips/vtophys.cc --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/trips/vtophys.cc Wed Apr 28 19:24:20 2010 +0800 @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2002-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Steve Reinhardt + * Ali Saidi + */ + +#include + +#include "arch/trips/ev5.hh" +#include "arch/trips/vtophys.hh" +#include "base/chunk_generator.hh" +#include "base/trace.hh" +#include "cpu/thread_context.hh" +#include "mem/vport.hh" + +using namespace std; + +namespace TripsISA { + +PageTableEntry +kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, VAddr vaddr) +{ + Addr level1_pte = ptbr + vaddr.level1(); + PageTableEntry level1 = mem->read(level1_pte); + if (!level1.valid()) { + DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr); + return 0; + } + + Addr level2_pte = level1.paddr() + vaddr.level2(); + PageTableEntry level2 = mem->read(level2_pte); + if (!level2.valid()) { + DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr); + return 0; + } + + Addr level3_pte = level2.paddr() + vaddr.level3(); + PageTableEntry level3 = mem->read(level3_pte); + if (!level3.valid()) { + DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr); + return 0; + } + return level3; +} + +Addr +vtophys(Addr vaddr) +{ + Addr paddr = 0; + if (IsUSeg(vaddr)) + DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr); + else if (IsK0Seg(vaddr)) + paddr = K0Seg2Phys(vaddr); + else + panic("vtophys: ptbr is not set on virtual lookup"); + + DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); + + return paddr; +} + +Addr +vtophys(ThreadContext *tc, Addr addr) +{ + VAddr vaddr = addr; + Addr ptbr = tc->readMiscRegNoEffect(IPR_PALtemp20); + Addr paddr = 0; + //@todo Andrew couldn't remember why he commented some of this code + //so I put it back in. Perhaps something to do with gdb debugging? + if (PcPAL(vaddr) && (vaddr < PalMax)) { + paddr = vaddr & ~ULL(1); + } else { + if (IsK0Seg(vaddr)) { + paddr = K0Seg2Phys(vaddr); + } else if (!ptbr) { + paddr = vaddr; + } else { + PageTableEntry pte = + kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr); + if (pte.valid()) + paddr = pte.paddr() | vaddr.offset(); + } + } + + + DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); + + return paddr; +} + +} // namespace TripsISA