diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -117,6 +117,7 @@
     State CacheState,        desc="cache state";
     bool Dirty,              desc="Is the data dirty (different than memory)?";
     DataBlock DataBlk,       desc="data for the block";
+    RubyAccessMode accessMode, desc="Access Mode permission for this block";
   }
 
   // TBE fields
@@ -125,6 +126,7 @@
     State TBEState,          desc="Transient state";
     DataBlock DataBlk,       desc="data for the block, required for concurrent writebacks";
     bool Dirty,              desc="Is the data dirty (different than memory)?";
+    RubyAccessMode accessMode, desc="Access Mode permission for this block";
     int NumPendingMsgs, default="0",     desc="Number of acks/data messages that this processor is waiting for";
   }
 
@@ -648,6 +650,7 @@
     assert(is_valid(cache_entry));
     tbe.DataBlk := cache_entry.DataBlk; // Data only used for writebacks
     tbe.Dirty := cache_entry.Dirty;
+    tbe.accessMode := cache_entry.accessMode;
   }
 
   action(j_popTriggerQueue, "j", desc="Pop trigger queue.") {
@@ -666,6 +669,17 @@
     requestNetwork_in.dequeue();
   }
 
+  action(ma_markAccessMode, "ma", desc="Record the Access Mode in the cache entry") {
+    peek(mandatoryQueue_in, RubyRequest) {
+      if(is_valid(cache_entry)) {
+        cache_entry.accessMode := in_msg.AccessMode;
+      }
+      if(is_valid(tbe)) {
+        tbe.accessMode := in_msg.AccessMode;
+      }
+    }
+  }
+
   action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") {
     peek(responseToL1Cache_in, ResponseMsg) {
       assert(is_valid(tbe));
@@ -923,6 +937,7 @@
     ii_allocateL1DCacheBlock;
     i_allocateTBE;
     a_issueGETS;
+    ma_markAccessMode;
     uu_profileDataMiss;
     k_popMandatoryQueue;
   }
@@ -931,6 +946,7 @@
     jj_allocateL1ICacheBlock;
     i_allocateTBE;
     a_issueGETS;
+    ma_markAccessMode;
     uu_profileInstMiss;
     k_popMandatoryQueue;
   }
@@ -939,6 +955,7 @@
     ii_allocateL1DCacheBlock;
     i_allocateTBE;
     b_issueGETX;
+    ma_markAccessMode;
     uu_profileDataMiss;
     k_popMandatoryQueue;
   }
@@ -955,6 +972,7 @@
   // Transitions from Shared
   transition({S, SM}, {Load, Ifetch}) {
     h_load_hit;
+    ma_markAccessMode;
     uu_profileDataHit;
     k_popMandatoryQueue;
   }
@@ -962,6 +980,7 @@
   transition(S, Store, SM) {
     i_allocateTBE;
     b_issueGETX;
+    ma_markAccessMode;
     uu_profileDataMiss;
     k_popMandatoryQueue;
   }
@@ -993,12 +1012,14 @@
   // Transitions from Owned
   transition({O, OM}, Ifetch) {
     h_load_hit;
+    ma_markAccessMode;
     uu_profileInstHit;
     k_popMandatoryQueue;
   }
 
   transition({O, OM}, Load) {
     h_load_hit;
+    ma_markAccessMode;
     uu_profileDataHit;
     k_popMandatoryQueue;
   }
@@ -1006,6 +1027,7 @@
   transition(O, Store, OM) {
     i_allocateTBE;
     b_issueGETX;
+    ma_markAccessMode;
     uu_profileDataMiss;
     k_popMandatoryQueue;
   }
@@ -1037,18 +1059,21 @@
   // Transitions from MM
   transition({MM, MM_W}, Ifetch) {
     h_load_hit;
+    ma_markAccessMode;
     uu_profileInstHit;
     k_popMandatoryQueue;
   }
 
   transition({MM, MM_W}, Load) {
     h_load_hit;
+    ma_markAccessMode;
     uu_profileDataHit;
     k_popMandatoryQueue;
   }
 
   transition({MM, MM_W}, Store) {
     hh_store_hit;
+    ma_markAccessMode;
     uu_profileDataHit;
     k_popMandatoryQueue;
   }
@@ -1081,24 +1106,28 @@
   // Transitions from M
   transition({M, M_W}, Ifetch) {
     h_load_hit;
+    ma_markAccessMode;
     uu_profileInstHit;
     k_popMandatoryQueue;
   }
 
   transition({M, M_W}, Load) {
     h_load_hit;
+    ma_markAccessMode;
     uu_profileDataHit;
     k_popMandatoryQueue;
   }
 
   transition(M, Store, MM) {
     hh_store_hit;
+    ma_markAccessMode;
     uu_profileDataHit;
     k_popMandatoryQueue;
   }
 
   transition(M_W, Store, MM_W) {
     hh_store_hit;
+    ma_markAccessMode;
     uu_profileDataHit;
     k_popMandatoryQueue;
   }
diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -181,6 +181,8 @@
     bool OwnerValid, default="false", desc="true if Owner means something";
     bool Dirty,              desc="Is the data dirty (different than memory)?";
     DataBlock DataBlk,       desc="data for the block";
+    RubyAccessMode accessMode,   desc="Access Mode permission for this block";
+    PrefetchBit pfBit,	     desc="Prefetch Bit for this block";
   }
 
 
@@ -189,6 +191,7 @@
     MachineID Owner,   desc="ID of the L1 cache to forward the block to once we get a response";
     bool OwnerValid, default="false", desc="true if Owner means something";
     State DirState,        desc="directory state";
+    RubyAccessMode accessMode,  desc="AccessMode permission for this Block";
   }
 
   // TBE fields
@@ -198,6 +201,8 @@
     Address PC,                           desc="Program counter of request";
     DataBlock DataBlk,                    desc="Buffer for the data block";
     bool Dirty,              desc="Is the data dirty (different than memory)?";
+    RubyAccessMode accessMode,            desc="Access Mode";
+    PrefetchBit pfBit,			  desc="Prefetch Bit for this Block";
 
     int NumExtPendingAcks, default="0",      desc="Number of global acks/data messages waiting for";
     int NumIntPendingAcks, default="0",      desc="Number of global acks/data messages waiting for";
@@ -290,7 +295,7 @@
     localDirectory[addr].Sharers := cache_entry.Sharers;
     localDirectory[addr].Owner := cache_entry.Owner;
     localDirectory[addr].OwnerValid := cache_entry.OwnerValid;
-
+    localDirectory[addr].accessMode := cache_entry.accessMode;
   }
 
   void copyDirToCache(Entry cache_entry, Address addr) {
@@ -531,7 +536,6 @@
     return getCacheEntry(addr).DataBlk;
   }
 
-
   GenericRequestType convertToGenericType(CoherenceRequestType type) {
     if(type == CoherenceRequestType:GETS) {
       return GenericRequestType:GETS;
@@ -713,6 +717,8 @@
         out_msg.Requestor := machineID;
         out_msg.Destination.add(map_Address_to_Directory(address));
         out_msg.MessageSize := MessageSizeType:Request_Control;
+	out_msg.AccessMode := in_msg.AccessMode;
+	out_msg.Prefetch := in_msg.Prefetch;
       }
     }
   }
@@ -726,6 +732,8 @@
         out_msg.Requestor := machineID;
         out_msg.Destination.add(map_Address_to_Directory(address));
         out_msg.MessageSize := MessageSizeType:Request_Control;
+        out_msg.AccessMode := in_msg.AccessMode;
+	out_msg.Prefetch := in_msg.Prefetch;
       }
     }
   }
@@ -738,6 +746,8 @@
       out_msg.Requestor := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
       out_msg.MessageSize := MessageSizeType:Writeback_Control;
+      out_msg.AccessMode  := cache_entry.accessMode;
+      out_msg.Prefetch    := cache_entry.pfBit; 
     }
   }
 
@@ -749,6 +759,8 @@
       out_msg.RequestorMachine := MachineType:L2Cache;
       out_msg.Destination.add(map_Address_to_Directory(address));
       out_msg.MessageSize := MessageSizeType:Writeback_Control;
+      out_msg.AccessMode  := cache_entry.accessMode;
+      out_msg.Prefetch    := cache_entry.pfBit;
     }
   }
 
@@ -761,6 +773,8 @@
       out_msg.RequestorMachine := MachineType:L2Cache;
       out_msg.Destination.add(map_Address_to_Directory(address));
       out_msg.MessageSize := MessageSizeType:Writeback_Control;
+      out_msg.AccessMode := cache_entry.accessMode;
+      out_msg.Prefetch := cache_entry.pfBit;
     }
   }
 
@@ -1203,6 +1217,8 @@
     if(is_valid(cache_entry)) {
       tbe.DataBlk := cache_entry.DataBlk;
       tbe.Dirty := cache_entry.Dirty;
+      tbe.accessMode := cache_entry.accessMode;
+      tbe.pfBit      := cache_entry.pfBit;
     }
     tbe.NumIntPendingAcks := 0;  // default value
     tbe.NumExtPendingAcks := 0;  // default value
@@ -1223,6 +1239,8 @@
         out_msg.Type := in_msg.Type;
         out_msg.MessageSize := MessageSizeType:Forwarded_Control;
         out_msg.Acks := 0 - 1;
+	out_msg.AccessMode := in_msg.AccessMode;
+	out_msg.Prefetch   := in_msg.Prefetch;
       }
     }
   }
@@ -1238,6 +1256,8 @@
         out_msg.Type := in_msg.Type;
         out_msg.MessageSize := MessageSizeType:Forwarded_Control;
         out_msg.Acks := 0 - 1;
+	out_msg.AccessMode := in_msg.AccessMode;
+	out_msg.Prefetch   := in_msg.Prefetch;
       }
     }
   }
@@ -1253,6 +1273,8 @@
         // should randomize this so one node doesn't get abused more than others
         out_msg.Destination.add(localDirectory[in_msg.Address].Sharers.smallestElement(MachineType:L1Cache));
         out_msg.MessageSize := MessageSizeType:Forwarded_Control;
+	out_msg.AccessMode  := in_msg.AccessMode;
+	out_msg.Prefetch    := in_msg.Prefetch;
       }
     }
   }
@@ -1267,6 +1289,8 @@
       out_msg.Destination.add(localDirectory[address].Owner);
       out_msg.MessageSize := MessageSizeType:Forwarded_Control;
       out_msg.Acks := 1 + tbe.Local_GETX_IntAcks;
+      out_msg.AccessMode := tbe.accessMode;
+      out_msg.Prefetch   := tbe.pfBit;
     }
   }
 
@@ -1281,6 +1305,8 @@
         out_msg.Destination.add(getLocalOwner(cache_entry, in_msg.Address));
         out_msg.MessageSize := MessageSizeType:Forwarded_Control;
         out_msg.Acks := 1;
+	out_msg.AccessMode := in_msg.AccessMode;
+	out_msg.Prefetch   := in_msg.Prefetch;
       }
     }
   }
@@ -1294,6 +1320,8 @@
         out_msg.RequestorMachine := MachineType:L1Cache;
         out_msg.Destination.add(getLocalOwner(cache_entry, in_msg.Address));
         out_msg.MessageSize := MessageSizeType:Forwarded_Control;
+	out_msg.AccessMode  := in_msg.AccessMode;
+	out_msg.Prefetch    := in_msg.Prefetch;
       }
     }
   }