diff -r 2daeea4bce1b -r 1c76d65922f3 configs/common/Caches.py --- a/configs/common/Caches.py Fri Oct 26 06:42:45 2012 -0400 +++ b/configs/common/Caches.py Fri Oct 26 17:58:06 2012 +0100 @@ -60,8 +60,8 @@ block_size = 64 hit_latency = 20 response_latency = 20 - mshrs = 92 - tgts_per_mshr = 16 + mshrs = 20 + tgts_per_mshr = 12 write_buffers = 8 class IOCache(BaseCache): diff -r 2daeea4bce1b -r 1c76d65922f3 tests/configs/inorder-timing.py --- a/tests/configs/inorder-timing.py Fri Oct 26 06:42:45 2012 -0400 +++ b/tests/configs/inorder-timing.py Fri Oct 26 17:58:06 2012 +0100 @@ -29,23 +29,12 @@ import m5 from m5.objects import * m5.util.addToPath('../configs/common') - -class MyCache(BaseCache): - assoc = 2 - block_size = 64 - hit_latency = 2 - response_latency = 2 - mshrs = 10 - tgts_per_mshr = 5 - -class MyL1Cache(MyCache): - is_top_level = True +from Caches import * cpu = InOrderCPU(cpu_id=0) -cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), - MyL1Cache(size = '256kB'), - MyCache(size = '2MB', hit_latency = 20, - response_latency = 20)) +cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'), + L1Cache(size = '256kB'), + L2Cache(size = '2MB')) cpu.clock = '2GHz' diff -r 2daeea4bce1b -r 1c76d65922f3 tests/configs/memtest.py --- a/tests/configs/memtest.py Fri Oct 26 06:42:45 2012 -0400 +++ b/tests/configs/memtest.py Fri Oct 26 17:58:06 2012 +0100 @@ -28,30 +28,8 @@ import m5 from m5.objects import * - -# -------------------- -# Base L1 Cache -# ==================== - -class L1(BaseCache): - hit_latency = 2 - response_latency = 2 - block_size = 64 - mshrs = 12 - tgts_per_mshr = 8 - is_top_level = True - -# ---------------------- -# Base L2 Cache -# ---------------------- - -class L2(BaseCache): - block_size = 64 - hit_latency = 20 - response_latency = 20 - mshrs = 92 - tgts_per_mshr = 16 - write_buffers = 8 +m5.util.addToPath('../configs/common') +from Caches import * #MAX CORES IS 8 with the fals sharing method nb_cores = 8 @@ -65,7 +43,7 @@ # l2cache & bus system.toL2Bus = CoherentBus(clock="2GHz", width=16) -system.l2c = L2(clock = '2GHz', size='64kB', assoc=8) +system.l2c = L2Cache(clock = '2GHz', size='64kB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master # connect l2c to membus @@ -73,7 +51,7 @@ # add L1 caches for cpu in cpus: - cpu.l1c = L1(size = '32kB', assoc = 4) + cpu.l1c = L1Cache(size = '32kB', assoc = 4) cpu.l1c.cpu_side = cpu.test cpu.l1c.mem_side = system.toL2Bus.slave system.funcbus.slave = cpu.functional diff -r 2daeea4bce1b -r 1c76d65922f3 tests/configs/o3-timing-checker.py --- a/tests/configs/o3-timing-checker.py Fri Oct 26 06:42:45 2012 -0400 +++ b/tests/configs/o3-timing-checker.py Fri Oct 26 17:58:06 2012 +0100 @@ -38,25 +38,14 @@ import m5 from m5.objects import * m5.util.addToPath('../configs/common') - -class MyCache(BaseCache): - assoc = 2 - block_size = 64 - hit_latency = 2 - response_latency = 2 - mshrs = 10 - tgts_per_mshr = 5 - -class MyL1Cache(MyCache): - is_top_level = True - tgts_per_mshr = 20 +from Caches import * cpu = DerivO3CPU(cpu_id=0) cpu.createInterruptController() cpu.addCheckerCpu() -cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), - MyL1Cache(size = '256kB'), - MyCache(size = '2MB')) +cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'), + L1Cache(size = '256kB'), + L2Cache(size = '2MB')) # @todo Note that the L2 latency here is unmodified and 2 cycles, # should set hit latency and response latency to 20 cycles as for # other scripts diff -r 2daeea4bce1b -r 1c76d65922f3 tests/configs/o3-timing.py --- a/tests/configs/o3-timing.py Fri Oct 26 06:42:45 2012 -0400 +++ b/tests/configs/o3-timing.py Fri Oct 26 17:58:06 2012 +0100 @@ -29,23 +29,12 @@ import m5 from m5.objects import * m5.util.addToPath('../configs/common') - -class MyCache(BaseCache): - assoc = 2 - block_size = 64 - hit_latency = 2 - response_latency = 2 - mshrs = 10 - tgts_per_mshr = 5 - -class MyL1Cache(MyCache): - is_top_level = True - tgts_per_mshr = 20 +from Caches import * cpu = DerivO3CPU(cpu_id=0) -cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), - MyL1Cache(size = '256kB'), - MyCache(size = '2MB')) +cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'), + L1Cache(size = '256kB'), + L2Cache(size = '2MB')) # @todo Note that the L2 latency here is unmodified and 2 cycles, # should set hit latency and response latency to 20 cycles as for # other scripts diff -r 2daeea4bce1b -r 1c76d65922f3 tests/configs/simple-atomic-mp.py --- a/tests/configs/simple-atomic-mp.py Fri Oct 26 06:42:45 2012 -0400 +++ b/tests/configs/simple-atomic-mp.py Fri Oct 26 17:58:06 2012 +0100 @@ -28,30 +28,8 @@ import m5 from m5.objects import * - -# -------------------- -# Base L1 Cache -# ==================== - -class L1(BaseCache): - hit_latency = 2 - response_latency = 2 - block_size = 64 - mshrs = 4 - tgts_per_mshr = 8 - is_top_level = True - -# ---------------------- -# Base L2 Cache -# ---------------------- - -class L2(BaseCache): - block_size = 64 - hit_latency = 20 - response_latency = 20 - mshrs = 92 - tgts_per_mshr = 16 - write_buffers = 8 +m5.util.addToPath('../configs/common') +from Caches import * nb_cores = 4 cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] @@ -63,7 +41,7 @@ # l2cache & bus system.toL2Bus = CoherentBus(clock = '2GHz') -system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) +system.l2c = L2Caches(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master # connect l2c to membus @@ -71,8 +49,8 @@ # add L1 caches for cpu in cpus: - cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4)) + cpu.addPrivateSplitL1Caches(L1Caches(size = '32kB', assoc = 1), + L1Caches(size = '32kB', assoc = 4)) # create the interrupt controller cpu.createInterruptController() # connect cpu level-1 caches to shared level-2 cache diff -r 2daeea4bce1b -r 1c76d65922f3 tests/configs/simple-timing-mp.py --- a/tests/configs/simple-timing-mp.py Fri Oct 26 06:42:45 2012 -0400 +++ b/tests/configs/simple-timing-mp.py Fri Oct 26 17:58:06 2012 +0100 @@ -28,30 +28,8 @@ import m5 from m5.objects import * - -# -------------------- -# Base L1 Cache -# ==================== - -class L1(BaseCache): - hit_latency = 2 - response_latency = 2 - block_size = 64 - mshrs = 4 - tgts_per_mshr = 8 - is_top_level = True - -# ---------------------- -# Base L2 Cache -# ---------------------- - -class L2(BaseCache): - block_size = 64 - hit_latency = 20 - response_latency = 20 - mshrs = 92 - tgts_per_mshr = 16 - write_buffers = 8 +m5.util.addToPath('../configs/common') +from Caches import * nb_cores = 4 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] @@ -61,7 +39,7 @@ # l2cache & bus system.toL2Bus = CoherentBus(clock = '2GHz') -system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) +system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master # connect l2c to membus @@ -69,8 +47,8 @@ # add L1 caches for cpu in cpus: - cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4)) + cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4)) # create the interrupt controller cpu.createInterruptController() # connect cpu level-1 caches to shared level-2 cache diff -r 2daeea4bce1b -r 1c76d65922f3 tests/configs/simple-timing.py --- a/tests/configs/simple-timing.py Fri Oct 26 06:42:45 2012 -0400 +++ b/tests/configs/simple-timing.py Fri Oct 26 17:58:06 2012 +0100 @@ -28,23 +28,13 @@ import m5 from m5.objects import * - -class MyCache(BaseCache): - assoc = 2 - block_size = 64 - hit_latency = 2 - response_latency = 2 - mshrs = 10 - tgts_per_mshr = 5 - -class MyL1Cache(MyCache): - is_top_level = True +m5.util.addToPath('../configs/common') +from Caches import * cpu = TimingSimpleCPU(cpu_id=0) -cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), - MyL1Cache(size = '256kB'), - MyCache(size = '2MB', hit_latency= 20, - response_latency = 20)) +cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'), + L1Cache(size = '256kB'), + L2Cache(size = '2MB')) system = System(cpu = cpu, physmem = SimpleMemory(), membus = CoherentBus())