diff -r daac35264bb0 -r 603d6ef97673 configs/common/O3_ARM_v7a.py
--- a/configs/common/O3_ARM_v7a.py	Mon Oct 29 16:27:48 2012 +0000
+++ b/configs/common/O3_ARM_v7a.py	Wed Oct 31 12:07:31 2012 +0000
@@ -146,8 +146,8 @@
 
 # Instruction Cache
 class O3_ARM_v7a_ICache(BaseCache):
-    hit_latency = 1
-    response_latency = 1
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 2
     tgts_per_mshr = 8
@@ -157,8 +157,8 @@
 
 # Data Cache
 class O3_ARM_v7a_DCache(BaseCache):
-    hit_latency = 2
-    response_latency = 2
+    hit_latency = 4
+    response_latency = 4
     block_size = 64
     mshrs = 6
     tgts_per_mshr = 8
@@ -170,8 +170,8 @@
 # TLB Cache 
 # Use a cache as a L2 TLB
 class O3_ARM_v7aWalkCache(BaseCache):
-    hit_latency = 4
-    response_latency = 4
+    hit_latency = 8
+    response_latency = 8
     block_size = 64
     mshrs = 6
     tgts_per_mshr = 8
@@ -183,8 +183,8 @@
 
 # L2 Cache
 class O3_ARM_v7aL2(BaseCache):
-    hit_latency = 12
-    response_latency = 12
+    hit_latency = 24
+    response_latency = 24
     block_size = 64
     mshrs = 16
     tgts_per_mshr = 8
@@ -193,5 +193,5 @@
     write_buffers = 8
     prefetch_on_access = 'true'
     # Simple stride prefetcher
-    prefetcher = StridePrefetcher(degree=8, latency = 1)
+    prefetcher = StridePrefetcher(degree=8, latency = 2)