diff -r 0f376b1f47c2 -r 11ac116125d7 configs/common/O3_ARM_v7a.py
--- a/configs/common/O3_ARM_v7a.py	Thu Dec 06 15:05:16 2012 -0500
+++ b/configs/common/O3_ARM_v7a.py	Thu Dec 06 15:06:36 2012 -0500
@@ -142,7 +142,7 @@
     numIQEntries = 32
     numROBEntries = 40
 
-    defer_registration= False
+    switched_out = False
 
 # Instruction Cache
 class O3_ARM_v7a_ICache(BaseCache):
diff -r 0f376b1f47c2 -r 11ac116125d7 configs/common/Simulation.py
--- a/configs/common/Simulation.py	Thu Dec 06 15:05:16 2012 -0500
+++ b/configs/common/Simulation.py	Thu Dec 06 15:06:36 2012 -0500
@@ -296,7 +296,7 @@
             testsys.cpu[i].max_insts_any_thread = options.maxinsts
 
     if cpu_class:
-        switch_cpus = [cpu_class(defer_registration=True, cpu_id=(i))
+        switch_cpus = [cpu_class(switched_out=True, cpu_id=(i))
                        for i in xrange(np)]
 
         for i in xrange(np):
@@ -321,23 +321,23 @@
                 print "O3 CPU must be used with caches"
                 sys.exit(1)
 
-            repeat_switch_cpus = [O3_ARM_v7a_3(defer_registration=True, \
+            repeat_switch_cpus = [O3_ARM_v7a_3(switched_out=True, \
                                   cpu_id=(i)) for i in xrange(np)]
         elif options.cpu_type == "detailed":
             if not options.caches:
                 print "O3 CPU must be used with caches"
                 sys.exit(1)
 
-            repeat_switch_cpus = [DerivO3CPU(defer_registration=True, \
+            repeat_switch_cpus = [DerivO3CPU(switched_out=True, \
                                   cpu_id=(i)) for i in xrange(np)]
         elif options.cpu_type == "inorder":
             print "inorder CPU switching not supported"
             sys.exit(1)
         elif options.cpu_type == "timing":
-            repeat_switch_cpus = [TimingSimpleCPU(defer_registration=True, \
+            repeat_switch_cpus = [TimingSimpleCPU(switched_out=True, \
                                   cpu_id=(i)) for i in xrange(np)]
         else:
-            repeat_switch_cpus = [AtomicSimpleCPU(defer_registration=True, \
+            repeat_switch_cpus = [AtomicSimpleCPU(switched_out=True, \
                                   cpu_id=(i)) for i in xrange(np)]
 
         for i in xrange(np):
@@ -361,9 +361,9 @@
                                       for i in xrange(np)]
 
     if options.standard_switch:
-        switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(i))
+        switch_cpus = [TimingSimpleCPU(switched_out=True, cpu_id=(i))
                        for i in xrange(np)]
-        switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(i))
+        switch_cpus_1 = [DerivO3CPU(switched_out=True, cpu_id=(i))
                         for i in xrange(np)]
 
         for i in xrange(np):
diff -r 0f376b1f47c2 -r 11ac116125d7 src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py	Thu Dec 06 15:05:16 2012 -0500
+++ b/src/cpu/BaseCPU.py	Thu Dec 06 15:06:36 2012 -0500
@@ -173,8 +173,9 @@
     progress_interval = Param.Frequency('0Hz',
         "frequency to print out the progress message")
 
-    defer_registration = Param.Bool(False,
-        "defer registration with system (for sampling)")
+    switched_out = Param.Bool(False,
+        "Leave the CPU switched out after startup (used when switching " \
+        "between CPU models)")
 
     tracer = Param.InstTracer(default_tracer, "Instruction tracer")
 
diff -r 0f376b1f47c2 -r 11ac116125d7 src/cpu/base.cc
--- a/src/cpu/base.cc	Thu Dec 06 15:05:16 2012 -0500
+++ b/src/cpu/base.cc	Thu Dec 06 15:06:36 2012 -0500
@@ -119,7 +119,7 @@
       _instMasterId(p->system->getMasterId(name() + ".inst")),
       _dataMasterId(p->system->getMasterId(name() + ".data")),
       _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid),
-      _switchedOut(p->defer_registration),
+      _switchedOut(p->switched_out),
       interrupts(p->interrupts), profileEvent(NULL),
       numThreads(p->numThreads), system(p->system)
 {
@@ -217,7 +217,7 @@
 
     // The interrupts should always be present unless this CPU is
     // switched in later or in case it is a checker CPU
-    if (!params()->defer_registration && !is_checker) {
+    if (!params()->switched_out && !is_checker) {
         if (interrupts) {
             interrupts->setCPU(this);
         } else {
@@ -254,7 +254,7 @@
 void
 BaseCPU::init()
 {
-    if (!params()->defer_registration)
+    if (!params()->switched_out)
         registerThreadContexts();
 }
 
@@ -262,7 +262,7 @@
 BaseCPU::startup()
 {
     if (FullSystem) {
-        if (!params()->defer_registration && profileEvent)
+        if (!params()->switched_out && profileEvent)
             schedule(profileEvent, curTick());
     }
 
diff -r 0f376b1f47c2 -r 11ac116125d7 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh	Thu Dec 06 15:05:16 2012 -0500
+++ b/src/cpu/inorder/cpu.hh	Thu Dec 06 15:06:36 2012 -0500
@@ -856,9 +856,6 @@
     /** Pointers to all of the threads in the CPU. */
     std::vector<Thread *> thread;
 
-    /** Whether or not the CPU should defer its registration. */
-    bool deferRegistration;
-
     /** Per-Stage Instruction Tracing */
     bool stageTracing;
 
diff -r 0f376b1f47c2 -r 11ac116125d7 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc	Thu Dec 06 15:05:16 2012 -0500
+++ b/src/cpu/inorder/cpu.cc	Thu Dec 06 15:06:36 2012 -0500
@@ -242,7 +242,6 @@
       resReqCount(0),
 #endif // DEBUG
       drainCount(0),
-      deferRegistration(false/*params->deferRegistration*/),
       stageTracing(params->stageTracing),
       lastRunningCycle(0),
       instsPerSwitch(0)
@@ -386,7 +385,7 @@
     }
 
     // InOrderCPU always requires an interrupt controller.
-    if (!params->defer_registration && !interrupts) {
+    if (!params->switched_out && !interrupts) {
         fatal("InOrderCPU %s has no interrupt controller.\n"
               "Ensure createInterruptController() is called.\n", name());
     }
@@ -787,7 +786,7 @@
 {
     BaseCPU::init();
 
-    if (!params()->defer_registration &&
+    if (!params()->switched_out &&
         system->getMemoryMode() != Enums::timing) {
         fatal("The in-order CPU requires the memory system to be in "
               "'timing' mode.\n");
@@ -801,7 +800,7 @@
         thread[tid]->initMemProxies(thread[tid]->getTC());
     }
 
-    if (FullSystem && !params()->defer_registration) {
+    if (FullSystem && !params()->switched_out) {
         for (ThreadID tid = 0; tid < numThreads; tid++) {
             ThreadContext *src_tc = threadContexts[tid];
             TheISA::initCPU(src_tc, src_tc->contextId());
diff -r 0f376b1f47c2 -r 11ac116125d7 src/cpu/o3/cpu.hh
--- a/src/cpu/o3/cpu.hh	Thu Dec 06 15:05:16 2012 -0500
+++ b/src/cpu/o3/cpu.hh	Thu Dec 06 15:06:36 2012 -0500
@@ -741,9 +741,6 @@
     /** Pointers to all of the threads in the CPU. */
     std::vector<Thread *> thread;
 
-    /** Whether or not the CPU should defer its registration. */
-    bool deferRegistration;
-
     /** Is there a context switch pending? */
     bool contextSwitch;
 
diff -r 0f376b1f47c2 -r 11ac116125d7 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc	Thu Dec 06 15:05:16 2012 -0500
+++ b/src/cpu/o3/cpu.cc	Thu Dec 06 15:06:36 2012 -0500
@@ -258,10 +258,9 @@
       globalSeqNum(1),
       system(params->system),
       drainCount(0),
-      deferRegistration(params->defer_registration),
       lastRunningCycle(curCycle())
 {
-    if (!deferRegistration) {
+    if (!params->switched_out) {
         _status = Running;
     } else {
         _status = SwitchedOut;
@@ -461,7 +460,7 @@
     }
 
     // FullO3CPU always requires an interrupt controller.
-    if (!params->defer_registration && !interrupts) {
+    if (!params->switched_out && !interrupts) {
         fatal("FullO3CPU %s has no interrupt controller.\n"
               "Ensure createInterruptController() is called.\n", name());
     }
@@ -647,7 +646,7 @@
 {
     BaseCPU::init();
 
-    if (!params()->defer_registration &&
+    if (!params()->switched_out &&
         system->getMemoryMode() != Enums::timing) {
         fatal("The O3 CPU requires the memory system to be in "
               "'timing' mode.\n");
@@ -668,7 +667,7 @@
     if (icachePort.isConnected())
         fetch.setIcache();
 
-    if (FullSystem && !params()->defer_registration) {
+    if (FullSystem && !params()->switched_out) {
         for (ThreadID tid = 0; tid < numThreads; tid++) {
             ThreadContext *src_tc = threadContexts[tid];
             TheISA::initCPU(src_tc, src_tc->contextId());
diff -r 0f376b1f47c2 -r 11ac116125d7 src/cpu/ozone/cpu_builder.cc
--- a/src/cpu/ozone/cpu_builder.cc	Thu Dec 06 15:05:16 2012 -0500
+++ b/src/cpu/ozone/cpu_builder.cc	Thu Dec 06 15:06:36 2012 -0500
@@ -189,7 +189,7 @@
 
     params->instShiftAmt = 2;
 
-    params->deferRegistration = defer_registration;
+    params->deferRegistration = switched_out;
 
     params->functionTrace = function_trace;
     params->functionTraceStart = function_trace_start;
diff -r 0f376b1f47c2 -r 11ac116125d7 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc	Thu Dec 06 15:05:16 2012 -0500
+++ b/src/cpu/simple/atomic.cc	Thu Dec 06 15:06:36 2012 -0500
@@ -83,7 +83,7 @@
 {
     BaseCPU::init();
 
-    if (!params()->defer_registration &&
+    if (!params()->switched_out &&
         system->getMemoryMode() != Enums::atomic) {
         fatal("The atomic CPU requires the memory system to be in "
               "'atomic' mode.\n");
@@ -92,7 +92,7 @@
     // Initialise the ThreadContext's memory proxies
     tcBase()->initMemProxies(tcBase());
 
-    if (FullSystem && !params()->defer_registration) {
+    if (FullSystem && !params()->switched_out) {
         ThreadID size = threadContexts.size();
         for (ThreadID i = 0; i < size; ++i) {
             ThreadContext *tc = threadContexts[i];
diff -r 0f376b1f47c2 -r 11ac116125d7 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc	Thu Dec 06 15:05:16 2012 -0500
+++ b/src/cpu/simple/timing.cc	Thu Dec 06 15:06:36 2012 -0500
@@ -66,7 +66,7 @@
 {
     BaseCPU::init();
 
-    if (!params()->defer_registration &&
+    if (!params()->switched_out &&
         system->getMemoryMode() != Enums::timing) {
         fatal("The timing CPU requires the memory system to be in "
               "'timing' mode.\n");
@@ -75,7 +75,7 @@
     // Initialise the ThreadContext's memory proxies
     tcBase()->initMemProxies(tcBase());
 
-    if (FullSystem && !params()->defer_registration) {
+    if (FullSystem && !params()->switched_out) {
         for (int i = 0; i < threadContexts.size(); ++i) {
             ThreadContext *tc = threadContexts[i];
             // initialize CPU, including PC