diff -r 9eebfb6f3b09 -r 9ea0c09dd390 src/arch/x86/isa.cc
--- a/src/arch/x86/isa.cc	Wed Dec 12 20:00:51 2012 -0600
+++ b/src/arch/x86/isa.cc	Thu Dec 13 00:06:50 2012 -0600
@@ -127,6 +127,13 @@
     if (miscReg == MISCREG_TSC) {
         return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
     }
+
+    if (miscReg == MISCREG_FSW) {
+        MiscReg fsw = regVal[MISCREG_FSW];
+        MiscReg top = regVal[MISCREG_X87_TOP];
+        return (fsw & (~(7ULL << 11))) + (top << 11);
+    }
+
     return readMiscRegNoEffect(miscReg);
 }
 
diff -r 9eebfb6f3b09 -r 9ea0c09dd390 src/arch/x86/isa/decoder/x87.isa
--- a/src/arch/x86/isa/decoder/x87.isa	Wed Dec 12 20:00:51 2012 -0600
+++ b/src/arch/x86/isa/decoder/x87.isa	Thu Dec 13 00:06:50 2012 -0600
@@ -247,7 +247,7 @@
             }
             0x7: decode MODRM_MOD {
                 0x3: Inst::UD2();
-                default: fnstsw();
+                default: Inst::FNSTSW(Mw);
             }
         }
         //0x6: esc6();
@@ -310,7 +310,7 @@
             }
             0x4: decode MODRM_MOD {
                 0x3: decode MODRM_RM {
-                    0x0: fnstsw();
+                    0x0: Inst::FNSTSW(rAw);
                     default: Inst::UD2();
                 }
                 default: fbld();
diff -r 9eebfb6f3b09 -r 9ea0c09dd390 src/arch/x86/isa/insts/x87/control/save_x87_status_word.py
--- a/src/arch/x86/isa/insts/x87/control/save_x87_status_word.py	Wed Dec 12 20:00:51 2012 -0600
+++ b/src/arch/x86/isa/insts/x87/control/save_x87_status_word.py	Thu Dec 13 00:06:50 2012 -0600
@@ -36,6 +36,22 @@
 # Authors: Gabe Black
 
 microcode = '''
+
 # FSTSW
-# FNSTSW
+
+def macroop FNSTSW_R {
+    rdval t1, fsw
+    mov rax, rax, t1, dataSize=2
+};
+
+def macroop FNSTSW_M {
+    rdval t1, fsw
+    st t1, seg, sib, disp, dataSize=2
+};
+
+def macroop FNSTSW_P {
+    rdip t7
+    rdval t1, fsw
+    st t1, seg, riprel, disp, dataSize=2
+};
 '''
diff -r 9eebfb6f3b09 -r 9ea0c09dd390 src/arch/x86/isa/microasm.isa
--- a/src/arch/x86/isa/microasm.isa	Wed Dec 12 20:00:51 2012 -0600
+++ b/src/arch/x86/isa/microasm.isa	Thu Dec 13 00:06:50 2012 -0600
@@ -207,6 +207,11 @@
     assembler.symbols["sti"] = stack_index("env.reg")
     assembler.symbols["stim"] = stack_index("env.regm")
 
+    def readFsw():
+        return regIdx("MISCREG_FSW")
+
+    assembler.symbols["fsw"] = readFsw()
+
     macroopDict = assembler.assemble(microcode)
 
     decoder_output += mainRom.getDefinition()