diff -r 353bbdbaa9fa -r 4f23fe95cda9 src/arch/alpha/isa.hh
--- a/src/arch/alpha/isa.hh	Fri Jan 11 12:44:12 2013 -0600
+++ b/src/arch/alpha/isa.hh	Fri Jan 11 20:18:45 2013 -0600
@@ -106,6 +106,8 @@
         const Params *params() const;
 
         ISA(Params *p);
+
+        void startup(ThreadContext *tc) {}
     };
 }
 
diff -r 353bbdbaa9fa -r 4f23fe95cda9 src/arch/arm/isa.hh
--- a/src/arch/arm/isa.hh	Fri Jan 11 12:44:12 2013 -0600
+++ b/src/arch/arm/isa.hh	Fri Jan 11 20:18:45 2013 -0600
@@ -193,6 +193,8 @@
             updateRegMap(tmp_cpsr);
         }
 
+        void startup(ThreadContext *tc) {}
+
         typedef ArmISAParams Params;
 
         const Params *params() const;
diff -r 353bbdbaa9fa -r 4f23fe95cda9 src/arch/mips/isa.hh
--- a/src/arch/mips/isa.hh	Fri Jan 11 12:44:12 2013 -0600
+++ b/src/arch/mips/isa.hh	Fri Jan 11 20:18:45 2013 -0600
@@ -157,6 +157,8 @@
         static std::string miscRegNames[NumMiscRegs];
 
       public:
+        void startup(ThreadContext *tc) {}
+
         const Params *params() const;
 
         ISA(Params *p);
diff -r 353bbdbaa9fa -r 4f23fe95cda9 src/arch/power/isa.hh
--- a/src/arch/power/isa.hh	Fri Jan 11 12:44:12 2013 -0600
+++ b/src/arch/power/isa.hh	Fri Jan 11 20:18:45 2013 -0600
@@ -98,6 +98,8 @@
         return reg;
     }
 
+    void startup(ThreadContext *tc) {}
+
     const Params *params() const;
 
     ISA(Params *p);
diff -r 353bbdbaa9fa -r 4f23fe95cda9 src/arch/sparc/isa.hh
--- a/src/arch/sparc/isa.hh	Fri Jan 11 12:44:12 2013 -0600
+++ b/src/arch/sparc/isa.hh	Fri Jan 11 20:18:45 2013 -0600
@@ -171,6 +171,8 @@
 
     void unserialize(Checkpoint *cp, const std::string & section);
 
+    void startup(ThreadContext *tc) {}
+
   protected:
 
     bool isHyperPriv() { return hpstate.hpriv; }
diff -r 353bbdbaa9fa -r 4f23fe95cda9 src/arch/x86/isa.hh
--- a/src/arch/x86/isa.hh	Fri Jan 11 12:44:12 2013 -0600
+++ b/src/arch/x86/isa.hh	Fri Jan 11 20:18:45 2013 -0600
@@ -87,6 +87,7 @@
 
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
+        void startup(ThreadContext *tc);
     };
 }
 
diff -r 353bbdbaa9fa -r 4f23fe95cda9 src/arch/x86/isa.cc
--- a/src/arch/x86/isa.cc	Fri Jan 11 12:44:12 2013 -0600
+++ b/src/arch/x86/isa.cc	Fri Jan 11 20:18:45 2013 -0600
@@ -387,6 +387,12 @@
                      NULL);
 }
 
+void
+ISA::startup(ThreadContext *tc)
+{
+    tc->getDecoderPtr()->setM5Reg(regVal[MISCREG_M5_REG]);
+}
+
 }
 
 X86ISA::ISA *
diff -r 353bbdbaa9fa -r 4f23fe95cda9 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc	Fri Jan 11 12:44:12 2013 -0600
+++ b/src/cpu/o3/cpu.cc	Fri Jan 11 20:18:45 2013 -0600
@@ -678,6 +678,9 @@
 void
 FullO3CPU<Impl>::startup()
 {
+    for (int tid = 0; tid < numThreads; ++tid)
+        isa[tid]->startup(threadContexts[tid]);
+
     fetch.startupStage();
     decode.startupStage();
     iew.startupStage();
diff -r 353bbdbaa9fa -r 4f23fe95cda9 src/cpu/simple/base.hh
--- a/src/cpu/simple/base.hh	Fri Jan 11 12:44:12 2013 -0600
+++ b/src/cpu/simple/base.hh	Fri Jan 11 20:18:45 2013 -0600
@@ -172,6 +172,8 @@
     virtual void regStats();
     virtual void resetStats();
 
+    virtual void startup();
+
     // number of simulated instructions
     Counter numInst;
     Counter startNumInst;
diff -r 353bbdbaa9fa -r 4f23fe95cda9 src/cpu/simple/base.cc
--- a/src/cpu/simple/base.cc	Fri Jan 11 12:44:12 2013 -0600
+++ b/src/cpu/simple/base.cc	Fri Jan 11 20:18:45 2013 -0600
@@ -515,37 +515,9 @@
     }
 }
 
-/*Fault
-BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
+void
+BaseSimpleCPU::startup()
 {
-    // translate to physical address
-    Fault fault = NoFault;
-    int CacheID = Op & 0x3; // Lower 3 bits identify Cache
-    int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
-    if(CacheID > 1)
-      {
-        warn("CacheOps not implemented for secondary/tertiary caches\n");
-      }
-    else
-      {
-        switch(CacheOP)
-          { // Fill Packet Type
-          case 0: warn("Invalidate Cache Op\n");
-            break;
-          case 1: warn("Index Load Tag Cache Op\n");
-            break;
-          case 2: warn("Index Store Tag Cache Op\n");
-            break;
-          case 4: warn("Hit Invalidate Cache Op\n");
-            break;
-          case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
-            break;
-          case 6: warn("Hit Writeback\n");
-            break;
-          case 7: warn("Fetch & Lock Cache Op\n");
-            break;
-          default: warn("Unimplemented Cache Op\n");
-          }
-      }
-    return fault;
-}*/
+    BaseCPU::startup();
+    thread->startup();
+}
diff -r 353bbdbaa9fa -r 4f23fe95cda9 src/cpu/simple_thread.hh
--- a/src/cpu/simple_thread.hh	Fri Jan 11 12:44:12 2013 -0600
+++ b/src/cpu/simple_thread.hh	Fri Jan 11 20:18:45 2013 -0600
@@ -150,6 +150,7 @@
 
     void serialize(std::ostream &os);
     void unserialize(Checkpoint *cp, const std::string &section);
+    void startup();
 
     /***************************************************************
      *  SimpleThread functions to provide CPU with access to various
diff -r 353bbdbaa9fa -r 4f23fe95cda9 src/cpu/simple_thread.cc
--- a/src/cpu/simple_thread.cc	Fri Jan 11 12:44:12 2013 -0600
+++ b/src/cpu/simple_thread.cc	Fri Jan 11 20:18:45 2013 -0600
@@ -143,6 +143,12 @@
 }
 
 void
+SimpleThread::startup()
+{
+    isa->startup(tc);
+}
+
+void
 SimpleThread::dumpFuncProfile()
 {
     std::ostream *os = simout.create(csprintf("profile.%s.dat",