diff -r 276ad773bc71 -r 33dc5a179d7c src/mem/protocol/MOESI_CMP_token-L1cache.sm --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Tue Jan 29 22:29:16 2013 -0600 +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Tue Jan 29 22:29:56 2013 -0600 @@ -153,7 +153,7 @@ bool IsAtomic, default="false", desc="Request was an atomic request"; AccessType AccessType, desc="Type of request (used for profiling)"; - Time IssueTime, desc="Time the request was issued"; + Cycles IssueTime, desc="Time the request was issued"; RubyAccessMode AccessMode, desc="user/supervisor access type"; PrefetchBit Prefetch, desc="Is this a prefetch request"; } @@ -183,7 +183,7 @@ void unset_tbe(); void wakeUpAllBuffers(); void wakeUpBuffers(Address a); - Time curCycle(); + Cycles curCycle(); TBETable L1_TBEs, template="", constructor="m_number_of_TBEs"; @@ -1452,7 +1452,7 @@ // Update average latency if (tbe.IssueCount <= 1) { if (tbe.ExternalResponse == true) { - updateAverageLatencyEstimate(TimeToCycles(curCycle() - tbe.IssueTime)); + updateAverageLatencyEstimate(curCycle() - tbe.IssueTime); } } diff -r 276ad773bc71 -r 33dc5a179d7c src/mem/protocol/MOESI_hammer-cache.sm --- a/src/mem/protocol/MOESI_hammer-cache.sm Tue Jan 29 22:29:16 2013 -0600 +++ b/src/mem/protocol/MOESI_hammer-cache.sm Tue Jan 29 22:29:56 2013 -0600 @@ -161,9 +161,13 @@ bool AppliedSilentAcks, default="false", desc="for full-bit dir, does the pending msg count reflect the silent acks"; MachineID LastResponder, desc="last machine to send a response for this request"; MachineID CurOwner, desc="current owner of the block, used for UnblockS responses"; - Time InitialRequestTime, default="0", desc="time the initial requests was sent from the L1Cache"; - Time ForwardRequestTime, default="0", desc="time the dir forwarded the request"; - Time FirstResponseTime, default="0", desc="the time the first response was received"; + + Cycles InitialRequestTime, default="Cycles(0)", + desc="time the initial requests was sent from the L1Cache"; + Cycles ForwardRequestTime, default="Cycles(0)", + desc="time the dir forwarded the request"; + Cycles FirstResponseTime, default="Cycles(0)", + desc="the time the first response was received"; } structure(TBETable, external="yes") { @@ -181,7 +185,7 @@ void unset_tbe(); void wakeUpAllBuffers(); void wakeUpBuffers(Address a); - Time curCycle(); + Cycles curCycle(); Entry getCacheEntry(Address address), return_by_pointer="yes" { Entry L2cache_entry := static_cast(Entry, "pointer", L2cacheMemory.lookup(address)); diff -r 276ad773bc71 -r 33dc5a179d7c src/mem/protocol/MOESI_hammer-dir.sm --- a/src/mem/protocol/MOESI_hammer-dir.sm Tue Jan 29 22:29:16 2013 -0600 +++ b/src/mem/protocol/MOESI_hammer-dir.sm Tue Jan 29 22:29:56 2013 -0600 @@ -179,7 +179,7 @@ void set_tbe(TBE a); void unset_tbe(); void wakeUpBuffers(Address a); - Time curCycle(); + Cycles curCycle(); // ** OBJECTS ** diff -r 276ad773bc71 -r 33dc5a179d7c src/mem/protocol/MOESI_hammer-msg.sm --- a/src/mem/protocol/MOESI_hammer-msg.sm Tue Jan 29 22:29:16 2013 -0600 +++ b/src/mem/protocol/MOESI_hammer-msg.sm Tue Jan 29 22:29:56 2013 -0600 @@ -94,8 +94,11 @@ NetDest Destination, desc="Multicast destination mask"; MessageSizeType MessageSize, desc="size category of the message"; bool DirectedProbe, default="false", desc="probe filter directed probe"; - Time InitialRequestTime, default="0", desc="time the initial requests was sent from the L1Cache"; - Time ForwardRequestTime, default="0", desc="time the dir forwarded the request"; + + Cycles InitialRequestTime, default="Cycles(0)", + desc="time the initial requests was sent from the L1Cache"; + Cycles ForwardRequestTime, default="Cycles(0)", + desc="time the dir forwarded the request"; int SilentAcks, default="0", desc="silent acks from the full-bit directory"; bool functionalRead(Packet *pkt) { @@ -120,8 +123,11 @@ bool Dirty, desc="Is the data dirty (different than memory)?"; int Acks, default="0", desc="How many messages this counts as"; MessageSizeType MessageSize, desc="size category of the message"; - Time InitialRequestTime, default="0", desc="time the initial requests was sent from the L1Cache"; - Time ForwardRequestTime, default="0", desc="time the dir forwarded the request"; + + Cycles InitialRequestTime, default="Cycles(0)", + desc="time the initial requests was sent from the L1Cache"; + Cycles ForwardRequestTime, default="Cycles(0)", + desc="time the dir forwarded the request"; int SilentAcks, default="0", desc="silent acks from the full-bit directory"; bool functionalRead(Packet *pkt) { diff -r 276ad773bc71 -r 33dc5a179d7c src/mem/protocol/RubySlicc_Exports.sm --- a/src/mem/protocol/RubySlicc_Exports.sm Tue Jan 29 22:29:16 2013 -0600 +++ b/src/mem/protocol/RubySlicc_Exports.sm Tue Jan 29 22:29:56 2013 -0600 @@ -37,7 +37,7 @@ external_type(PacketPtr, primitive="yes"); external_type(Packet, primitive="yes"); external_type(Address); -external_type(Cycles, primitive="yes"); +external_type(Cycles, primitive="yes", default="Cycles(0)"); structure(DataBlock, external = "yes", desc="..."){ void clear(); diff -r 276ad773bc71 -r 33dc5a179d7c src/mem/protocol/RubySlicc_Types.sm --- a/src/mem/protocol/RubySlicc_Types.sm Tue Jan 29 22:29:16 2013 -0600 +++ b/src/mem/protocol/RubySlicc_Types.sm Tue Jan 29 22:29:56 2013 -0600 @@ -97,10 +97,14 @@ structure (Sequencer, external = "yes") { void readCallback(Address, DataBlock); void readCallback(Address, GenericMachineType, DataBlock); - void readCallback(Address, GenericMachineType, DataBlock, Time, Time, Time); + void readCallback(Address, GenericMachineType, DataBlock, + Cycles, Cycles, Cycles); + void writeCallback(Address, DataBlock); void writeCallback(Address, GenericMachineType, DataBlock); - void writeCallback(Address, GenericMachineType, DataBlock, Time, Time, Time); + void writeCallback(Address, GenericMachineType, DataBlock, + Cycles, Cycles, Cycles); + void checkCoherence(Address); void profileNack(Address, int, int, uint64); void evictionCallback(Address); diff -r 276ad773bc71 -r 33dc5a179d7c src/mem/protocol/RubySlicc_Util.sm --- a/src/mem/protocol/RubySlicc_Util.sm Tue Jan 29 22:29:16 2013 -0600 +++ b/src/mem/protocol/RubySlicc_Util.sm Tue Jan 29 22:29:56 2013 -0600 @@ -32,14 +32,10 @@ void error(std::string msg); void assert(bool condition); int random(int number); -Time zero_time(); +Cycles zero_time(); Cycles TimeToCycles(Time t); NodeID intToID(int nodenum); int IDToInt(NodeID id); -int time_to_int(Time time); -Time getTimeModInt(Time time, int modulus); -Time getTimePlusInt(Time addend1, int addend2); -Time getTimeMinusTime(Time t1, Time t2); void procProfileCoherenceRequest(NodeID node, bool needCLB); void dirProfileCoherenceRequest(NodeID node, bool needCLB); int max_tokens(); diff -r 276ad773bc71 -r 33dc5a179d7c src/mem/ruby/profiler/Profiler.hh --- a/src/mem/ruby/profiler/Profiler.hh Tue Jan 29 22:29:16 2013 -0600 +++ b/src/mem/ruby/profiler/Profiler.hh Tue Jan 29 22:29:56 2013 -0600 @@ -125,29 +125,23 @@ void startTransaction(int cpu); void endTransaction(int cpu); - void profilePFWait(Time waitTime); + void profilePFWait(Cycles waitTime); void controllerBusy(MachineID machID); void bankBusy(); - void missLatency(Time t, - RubyRequestType type, + void missLatency(Cycles t, RubyRequestType type, const GenericMachineType respondingMach); - void missLatencyWcc(Time issuedTime, - Time initialRequestTime, - Time forwardRequestTime, - Time firstResponseTime, - Time completionTime); + void missLatencyWcc(Cycles issuedTime, Cycles initialRequestTime, + Cycles forwardRequestTime, Cycles firstResponseTime, + Cycles completionTime); - void missLatencyDir(Time issuedTime, - Time initialRequestTime, - Time forwardRequestTime, - Time firstResponseTime, - Time completionTime); + void missLatencyDir(Cycles issuedTime, Cycles initialRequestTime, + Cycles forwardRequestTime, Cycles firstResponseTime, + Cycles completionTime); - void swPrefetchLatency(Time t, - RubyRequestType type, + void swPrefetchLatency(Cycles t, RubyRequestType type, const GenericMachineType respondingMach); void sequencerRequests(int num) { m_sequencer_requests.add(num); } @@ -158,11 +152,7 @@ bool watchAddress(Address addr); // return Ruby's start time - Time - getRubyStartTime() - { - return m_ruby_start; - } + Cycles getRubyStartTime() { return m_ruby_start; } // added by SS bool getHotLines() { return m_hot_lines; } @@ -186,7 +176,7 @@ std::ostream* m_periodic_output_file_ptr; int64_t m_stats_period; - Time m_ruby_start; + Cycles m_ruby_start; time_t m_real_time_start_time; int64_t m_busyBankCount; diff -r 276ad773bc71 -r 33dc5a179d7c src/mem/ruby/profiler/Profiler.cc --- a/src/mem/ruby/profiler/Profiler.cc Tue Jan 29 22:29:16 2013 -0600 +++ b/src/mem/ruby/profiler/Profiler.cc Tue Jan 29 22:29:56 2013 -0600 @@ -270,7 +270,7 @@ double minutes = seconds / 60.0; double hours = minutes / 60.0; double days = hours / 24.0; - Time ruby_cycles = g_system_ptr->getTime()-m_ruby_start; + Cycles ruby_cycles = g_system_ptr->getTime()-m_ruby_start; if (!short_stats) { out << "Elapsed_time_in_seconds: " << seconds << endl; @@ -609,7 +609,7 @@ } void -Profiler::profilePFWait(Time waitTime) +Profiler::profilePFWait(Cycles waitTime) { m_prefetchWaitHistogram.add(waitTime); } @@ -622,7 +622,7 @@ // non-zero cycle demand request void -Profiler::missLatency(Time cycles, +Profiler::missLatency(Cycles cycles, RubyRequestType type, const GenericMachineType respondingMach) { @@ -633,11 +633,11 @@ } void -Profiler::missLatencyWcc(Time issuedTime, - Time initialRequestTime, - Time forwardRequestTime, - Time firstResponseTime, - Time completionTime) +Profiler::missLatencyWcc(Cycles issuedTime, + Cycles initialRequestTime, + Cycles forwardRequestTime, + Cycles firstResponseTime, + Cycles completionTime) { if ((issuedTime <= initialRequestTime) && (initialRequestTime <= forwardRequestTime) && @@ -659,11 +659,11 @@ } void -Profiler::missLatencyDir(Time issuedTime, - Time initialRequestTime, - Time forwardRequestTime, - Time firstResponseTime, - Time completionTime) +Profiler::missLatencyDir(Cycles issuedTime, + Cycles initialRequestTime, + Cycles forwardRequestTime, + Cycles firstResponseTime, + Cycles completionTime) { if ((issuedTime <= initialRequestTime) && (initialRequestTime <= forwardRequestTime) && @@ -686,13 +686,13 @@ // non-zero cycle prefetch request void -Profiler::swPrefetchLatency(Time cycles, - RubyRequestType type, +Profiler::swPrefetchLatency(Cycles cycles, RubyRequestType type, const GenericMachineType respondingMach) { m_allSWPrefetchLatencyHistogram.add(cycles); m_SWPrefetchLatencyHistograms[type].add(cycles); m_SWPrefetchMachLatencyHistograms[respondingMach].add(cycles); + if (respondingMach == GenericMachineType_Directory || respondingMach == GenericMachineType_NUM) { m_SWPrefetchL2MissLatencyHistogram.add(cycles); diff -r 276ad773bc71 -r 33dc5a179d7c src/mem/ruby/slicc_interface/RubySlicc_Util.hh --- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh Tue Jan 29 22:29:16 2013 -0600 +++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh Tue Jan 29 22:29:56 2013 -0600 @@ -46,12 +46,7 @@ return random() % n; } -inline Time -zero_time() -{ - return 0; -} - +inline Cycles zero_time() { return Cycles(0); } inline Cycles TimeToCycles(Time t) { return Cycles(t); } inline NodeID @@ -68,33 +63,6 @@ return nodenum; } -inline Time -getTimeModInt(Time time, int modulus) -{ - return time % modulus; -} - -inline Time -getTimePlusInt(Time addend1, int addend2) -{ - return (Time) addend1 + addend2; -} - -inline Time -getTimeMinusTime(Time t1, Time t2) -{ - assert(t1 >= t2); - return t1 - t2; -} - -// Return type for time_to_int is "Time" and not "int" so we get a -// 64-bit integer -inline Time -time_to_int(Time time) -{ - return time; -} - // Appends an offset to an address inline Address setOffset(Address addr, int offset) diff -r 276ad773bc71 -r 33dc5a179d7c src/mem/ruby/system/Sequencer.hh --- a/src/mem/ruby/system/Sequencer.hh Tue Jan 29 22:29:16 2013 -0600 +++ b/src/mem/ruby/system/Sequencer.hh Tue Jan 29 22:29:56 2013 -0600 @@ -69,29 +69,29 @@ void writeCallback(const Address& address, DataBlock& data); - void writeCallback(const Address& address, - GenericMachineType mach, + void writeCallback(const Address& address, + GenericMachineType mach, DataBlock& data); - void writeCallback(const Address& address, - GenericMachineType mach, + void writeCallback(const Address& address, + GenericMachineType mach, DataBlock& data, - Time initialRequestTime, - Time forwardRequestTime, - Time firstResponseTime); + Cycles initialRequestTime, + Cycles forwardRequestTime, + Cycles firstResponseTime); void readCallback(const Address& address, DataBlock& data); - void readCallback(const Address& address, - GenericMachineType mach, + void readCallback(const Address& address, + GenericMachineType mach, DataBlock& data); - void readCallback(const Address& address, - GenericMachineType mach, + void readCallback(const Address& address, + GenericMachineType mach, DataBlock& data, - Time initialRequestTime, - Time forwardRequestTime, - Time firstResponseTime); + Cycles initialRequestTime, + Cycles forwardRequestTime, + Cycles firstResponseTime); RequestStatus makeRequest(PacketPtr pkt); bool empty() const; @@ -121,13 +121,13 @@ private: void issueRequest(PacketPtr pkt, RubyRequestType type); - void hitCallback(SequencerRequest* request, + void hitCallback(SequencerRequest* request, GenericMachineType mach, DataBlock& data, bool success, - Time initialRequestTime, - Time forwardRequestTime, - Time firstResponseTime); + Cycles initialRequestTime, + Cycles forwardRequestTime, + Cycles firstResponseTime); RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type); @@ -151,10 +151,10 @@ int m_outstanding_count; bool m_deadlock_check_scheduled; - int m_store_waiting_on_load_cycles; - int m_store_waiting_on_store_cycles; - int m_load_waiting_on_store_cycles; - int m_load_waiting_on_load_cycles; + uint32_t m_store_waiting_on_load_cycles; + uint32_t m_store_waiting_on_store_cycles; + uint32_t m_load_waiting_on_store_cycles; + uint32_t m_load_waiting_on_load_cycles; bool m_usingNetworkTester; diff -r 276ad773bc71 -r 33dc5a179d7c src/mem/ruby/system/Sequencer.cc --- a/src/mem/ruby/system/Sequencer.cc Tue Jan 29 22:29:16 2013 -0600 +++ b/src/mem/ruby/system/Sequencer.cc Tue Jan 29 22:29:56 2013 -0600 @@ -359,19 +359,19 @@ void Sequencer::writeCallback(const Address& address, - GenericMachineType mach, + GenericMachineType mach, DataBlock& data) { - writeCallback(address, mach, data, 0, 0, 0); + writeCallback(address, mach, data, Cycles(0), Cycles(0), Cycles(0)); } void Sequencer::writeCallback(const Address& address, - GenericMachineType mach, + GenericMachineType mach, DataBlock& data, - Time initialRequestTime, - Time forwardRequestTime, - Time firstResponseTime) + Cycles initialRequestTime, + Cycles forwardRequestTime, + Cycles firstResponseTime) { assert(address == line_address(address)); assert(m_writeRequestTable.count(line_address(address))); @@ -410,7 +410,7 @@ m_controller->unblock(address); } - hitCallback(request, mach, data, success, + hitCallback(request, mach, data, success, initialRequestTime, forwardRequestTime, firstResponseTime); } @@ -425,16 +425,16 @@ GenericMachineType mach, DataBlock& data) { - readCallback(address, mach, data, 0, 0, 0); + readCallback(address, mach, data, Cycles(0), Cycles(0), Cycles(0)); } void Sequencer::readCallback(const Address& address, GenericMachineType mach, DataBlock& data, - Time initialRequestTime, - Time forwardRequestTime, - Time firstResponseTime) + Cycles initialRequestTime, + Cycles forwardRequestTime, + Cycles firstResponseTime) { assert(address == line_address(address)); assert(m_readRequestTable.count(line_address(address))); @@ -449,7 +449,7 @@ assert((request->m_type == RubyRequestType_LD) || (request->m_type == RubyRequestType_IFETCH)); - hitCallback(request, mach, data, true, + hitCallback(request, mach, data, true, initialRequestTime, forwardRequestTime, firstResponseTime); } @@ -458,16 +458,16 @@ GenericMachineType mach, DataBlock& data, bool success, - Time initialRequestTime, - Time forwardRequestTime, - Time firstResponseTime) + Cycles initialRequestTime, + Cycles forwardRequestTime, + Cycles firstResponseTime) { PacketPtr pkt = srequest->pkt; Address request_address(pkt->getAddr()); Address request_line_address(pkt->getAddr()); request_line_address.makeLineAddress(); RubyRequestType type = srequest->m_type; - Time issued_time = srequest->issue_time; + Cycles issued_time = srequest->issue_time; // Set this cache entry to the most recently used if (type == RubyRequestType_IFETCH) { @@ -477,7 +477,7 @@ } assert(curCycle() >= issued_time); - Time miss_latency = curCycle() - issued_time; + Cycles miss_latency = curCycle() - issued_time; // Profile the miss latency for all non-zero demand misses if (miss_latency != 0) { diff -r 276ad773bc71 -r 33dc5a179d7c src/mem/ruby/system/TBETable.hh --- a/src/mem/ruby/system/TBETable.hh Tue Jan 29 22:29:16 2013 -0600 +++ b/src/mem/ruby/system/TBETable.hh Tue Jan 29 22:29:56 2013 -0600 @@ -33,9 +33,6 @@ #include "base/hashmap.hh" #include "mem/ruby/common/Address.hh" -#include "mem/ruby/common/Global.hh" -#include "mem/ruby/profiler/Profiler.hh" -#include "mem/ruby/system/System.hh" template class TBETable