diff -r 33dc5a179d7c -r 4ac7d8489e65 src/mem/protocol/RubySlicc_Exports.sm
--- a/src/mem/protocol/RubySlicc_Exports.sm	Tue Jan 29 22:29:56 2013 -0600
+++ b/src/mem/protocol/RubySlicc_Exports.sm	Tue Jan 29 22:30:58 2013 -0600
@@ -33,7 +33,6 @@
 external_type(std::string, primitive="yes");
 external_type(uint32_t, primitive="yes");
 external_type(uint64, primitive="yes");
-external_type(Time, primitive="yes", default="0");
 external_type(PacketPtr, primitive="yes");
 external_type(Packet, primitive="yes");
 external_type(Address);
diff -r 33dc5a179d7c -r 4ac7d8489e65 src/mem/protocol/RubySlicc_Profiler.sm
--- a/src/mem/protocol/RubySlicc_Profiler.sm	Tue Jan 29 22:29:56 2013 -0600
+++ b/src/mem/protocol/RubySlicc_Profiler.sm	Tue Jan 29 22:30:58 2013 -0600
@@ -47,4 +47,4 @@
 void profile_average_latency_estimate(int latency);
 
 // profile the total message delay of a message across a virtual network
-void profileMsgDelay(int virtualNetwork, Time delayCycles);
+void profileMsgDelay(int virtualNetwork, Cycles delayCycles);
diff -r 33dc5a179d7c -r 4ac7d8489e65 src/mem/protocol/RubySlicc_Types.sm
--- a/src/mem/protocol/RubySlicc_Types.sm	Tue Jan 29 22:29:56 2013 -0600
+++ b/src/mem/protocol/RubySlicc_Types.sm	Tue Jan 29 22:30:58 2013 -0600
@@ -41,7 +41,7 @@
 structure(InPort, external = "yes", primitive="yes") {
   bool isReady();
   void dequeue();
-  Time dequeue_getDelayCycles();
+  Cycles dequeue_getDelayCycles();
   void recycle();
   bool isEmpty();
 }
diff -r 33dc5a179d7c -r 4ac7d8489e65 src/mem/protocol/RubySlicc_Util.sm
--- a/src/mem/protocol/RubySlicc_Util.sm	Tue Jan 29 22:29:56 2013 -0600
+++ b/src/mem/protocol/RubySlicc_Util.sm	Tue Jan 29 22:30:58 2013 -0600
@@ -33,7 +33,6 @@
 void assert(bool condition);
 int random(int number);
 Cycles zero_time();
-Cycles TimeToCycles(Time t);
 NodeID intToID(int nodenum);
 int IDToInt(NodeID id);
 void procProfileCoherenceRequest(NodeID node, bool needCLB);
diff -r 33dc5a179d7c -r 4ac7d8489e65 src/mem/ruby/common/TypeDefines.hh
--- a/src/mem/ruby/common/TypeDefines.hh	Tue Jan 29 22:29:56 2013 -0600
+++ b/src/mem/ruby/common/TypeDefines.hh	Tue Jan 29 22:30:58 2013 -0600
@@ -31,7 +31,6 @@
 #define TYPEDEFINES_H
 
 typedef unsigned long long uint64;
-
 typedef long long int64;
 
 typedef int64 Time;
diff -r 33dc5a179d7c -r 4ac7d8489e65 src/mem/ruby/slicc_interface/AbstractController.hh
--- a/src/mem/ruby/slicc_interface/AbstractController.hh	Tue Jan 29 22:29:56 2013 -0600
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh	Tue Jan 29 22:30:58 2013 -0600
@@ -101,7 +101,7 @@
     //! Profiles original cache requests including PUTs
     void profileRequest(const std::string &request);
     //! Profiles the delay associated with messages.
-    void profileMsgDelay(uint32_t virtualNetwork, Time delay);
+    void profileMsgDelay(uint32_t virtualNetwork, Cycles delay);
 
   protected:
     int m_transitions_per_cycle;
diff -r 33dc5a179d7c -r 4ac7d8489e65 src/mem/ruby/slicc_interface/AbstractController.cc
--- a/src/mem/ruby/slicc_interface/AbstractController.cc	Tue Jan 29 22:29:56 2013 -0600
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc	Tue Jan 29 22:30:58 2013 -0600
@@ -73,7 +73,7 @@
 }
 
 void
-AbstractController::profileMsgDelay(uint32_t virtualNetwork, Time delay)
+AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
 {
     assert(virtualNetwork < m_delayVCHistogram.size());
     m_delayHistogram.add(delay);
diff -r 33dc5a179d7c -r 4ac7d8489e65 src/mem/ruby/structures/Prefetcher.cc
--- a/src/mem/ruby/structures/Prefetcher.cc	Tue Jan 29 22:29:56 2013 -0600
+++ b/src/mem/ruby/structures/Prefetcher.cc	Tue Jan 29 22:30:58 2013 -0600
@@ -257,7 +257,7 @@
 Prefetcher::getLRUindex(void)
 {
     uint32_t lru_index = 0;
-    Time lru_access = m_array[lru_index].m_use_time;
+    Cycles lru_access = m_array[lru_index].m_use_time;
 
     for (uint32_t i = 0; i < m_num_streams; i++) {
         if (!m_array[i].m_is_valid) {
diff -r 33dc5a179d7c -r 4ac7d8489e65 src/mem/ruby/system/TimerTable.hh
--- a/src/mem/ruby/system/TimerTable.hh	Tue Jan 29 22:29:56 2013 -0600
+++ b/src/mem/ruby/system/TimerTable.hh	Tue Jan 29 22:30:58 2013 -0600
@@ -85,7 +85,7 @@
     typedef std::map<Address, Cycles> AddressMap;
     AddressMap m_map;
     mutable bool m_next_valid;
-    mutable Time m_next_time; // Only valid if m_next_valid is true
+    mutable Cycles m_next_time; // Only valid if m_next_valid is true
     mutable Address m_next_address;  // Only valid if m_next_valid is true
 
     //! Object used for querying time.
diff -r 33dc5a179d7c -r 4ac7d8489e65 src/mem/ruby/system/TimerTable.cc
--- a/src/mem/ruby/system/TimerTable.cc	Tue Jan 29 22:29:56 2013 -0600
+++ b/src/mem/ruby/system/TimerTable.cc	Tue Jan 29 22:30:58 2013 -0600
@@ -31,13 +31,13 @@
 #include "mem/ruby/system/TimerTable.hh"
 
 TimerTable::TimerTable()
+    : m_next_time(0)
 {
     m_consumer_ptr  = NULL;
     m_clockobj_ptr = NULL;
 
     m_next_valid = false;
     m_next_address = Address(0);
-    m_next_time = 0;
 }
 
 bool
diff -r 33dc5a179d7c -r 4ac7d8489e65 src/mem/slicc/ast/InfixOperatorExprAST.py
--- a/src/mem/slicc/ast/InfixOperatorExprAST.py	Tue Jan 29 22:29:56 2013 -0600
+++ b/src/mem/slicc/ast/InfixOperatorExprAST.py	Tue Jan 29 22:30:58 2013 -0600
@@ -66,7 +66,6 @@
                                   ("Cycles", "int", "Cycles")]
             elif self.op in ("+", "-", "*", "/"):
                 expected_types = [("int", "int", "int"),
-                                  ("Time", "Time", "Time"),
                                   ("Cycles", "Cycles", "Cycles"),
                                   ("Cycles", "int", "Cycles"),
                                   ("int", "Cycles", "Cycles")]