diff -r 3a8a984feca6 -r d8e3bd9d3fc2 src/dev/arm/timer_cpulocal.hh --- a/src/dev/arm/timer_cpulocal.hh Mon Feb 18 13:45:36 2013 +0000 +++ b/src/dev/arm/timer_cpulocal.hh Mon Feb 18 13:55:17 2013 +0000 @@ -103,9 +103,6 @@ /** Cpu this timer is attached to */ uint32_t cpuNum; - /** Number of ticks in a clock input */ - Tick clock; - /** Control register as specified above */ TimerCtrl timerControl; WatchdogCtrl watchdogControl; diff -r 3a8a984feca6 -r d8e3bd9d3fc2 src/dev/arm/timer_cpulocal.cc --- a/src/dev/arm/timer_cpulocal.cc Mon Feb 18 13:45:36 2013 +0000 +++ b/src/dev/arm/timer_cpulocal.cc Mon Feb 18 13:55:17 2013 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2011 ARM Limited + * Copyright (c) 2010-2013 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -58,7 +58,6 @@ localTimer[i].parent = this; localTimer[i].intNumTimer = p->int_num_timer; localTimer[i].intNumWatchdog = p->int_num_watchdog; - localTimer[i].clock = clock; localTimer[i].cpuNum = i; } pioSize = 0x38; @@ -104,9 +103,11 @@ break; case TimerCounterReg: DPRINTF(Timer, "Event schedule for timer %d, clock=%d, prescale=%d\n", - timerZeroEvent.when(), clock, timerControl.prescalar); + timerZeroEvent.when(), parent->clockPeriod(), + timerControl.prescalar); time = timerZeroEvent.when() - curTick(); - time = time / clock / power(16, timerControl.prescalar); + time = time / parent->clockPeriod() / + power(16, timerControl.prescalar); DPRINTF(Timer, "-- returning counter at %d\n", time); pkt->set(time); break; @@ -120,10 +121,13 @@ pkt->set(watchdogLoadValue); break; case WatchdogCounterReg: - DPRINTF(Timer, "Event schedule for watchdog %d, clock=%d, prescale=%d\n", - watchdogZeroEvent.when(), clock, watchdogControl.prescalar); + DPRINTF(Timer, + "Event schedule for watchdog %d, clock=%d, prescale=%d\n", + watchdogZeroEvent.when(), parent->clockPeriod(), + watchdogControl.prescalar); time = watchdogZeroEvent.when() - curTick(); - time = time / clock / power(16, watchdogControl.prescalar); + time = time / parent->clockPeriod() / + power(16, watchdogControl.prescalar); DPRINTF(Timer, "-- returning counter at %d\n", time); pkt->set(time); break; @@ -249,7 +253,7 @@ if (!timerControl.enable) return; - Tick time = clock * power(16, timerControl.prescalar); + Tick time = parent->clockPeriod() * power(16, timerControl.prescalar); time *= val; if (timerZeroEvent.scheduled()) { @@ -267,7 +271,7 @@ if (!watchdogControl.enable) return; - Tick time = clock * power(16, watchdogControl.prescalar); + Tick time = parent->clockPeriod() * power(16, watchdogControl.prescalar); time *= val; if (watchdogZeroEvent.scheduled()) { diff -r 3a8a984feca6 -r d8e3bd9d3fc2 src/mem/bus.hh --- a/src/mem/bus.hh Mon Feb 18 13:45:36 2013 +0000 +++ b/src/mem/bus.hh Mon Feb 18 13:55:17 2013 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012 ARM Limited + * Copyright (c) 2011-2013 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -105,9 +105,8 @@ * * @param _bus the bus this layer belongs to * @param _name the layer's name - * @param _clock clock period in ticks */ - Layer(BaseBus& _bus, const std::string& _name, Tick _clock); + Layer(BaseBus& _bus, const std::string& _name); /** * Drain according to the normal semantics, so that the bus @@ -203,9 +202,6 @@ /** track the state of the bus layer */ State state; - /** the clock speed for the bus layer */ - Tick clock; - /** manager to signal when drained */ DrainManager *drainManager; diff -r 3a8a984feca6 -r d8e3bd9d3fc2 src/mem/bus.cc --- a/src/mem/bus.cc Mon Feb 18 13:45:36 2013 +0000 +++ b/src/mem/bus.cc Mon Feb 18 13:55:17 2013 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012 ARM Limited + * Copyright (c) 2011-2013 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -132,37 +132,33 @@ Tick BaseBus::calcPacketTiming(PacketPtr pkt) { - // determine the current time rounded to the closest following + // determine the header time rounded to the closest following // clock edge - Tick now = nextCycle(); - - Tick headerTime = now + headerCycles * clock; + Tick headerTime = clockEdge(headerCycles); // The packet will be sent. Figure out how long it occupies the bus, and // how much of that time is for the first "word", aka bus width. - int numCycles = 0; + Cycles numCycles(0); if (pkt->hasData()) { // If a packet has data, it needs ceil(size/width) cycles to send it - int dataSize = pkt->getSize(); - numCycles += dataSize/width; - if (dataSize % width) - numCycles++; + unsigned dataSize = pkt->getSize(); + numCycles = Cycles(divCeil(dataSize, width)); } - // The first word will be delivered after the current tick, the delivery - // of the address if any, and one bus cycle to deliver the data - pkt->firstWordTime = headerTime + clock; + // The first word will be delivered on the cycle after the header. + pkt->firstWordTime = headerTime + clockPeriod(); - pkt->finishTime = headerTime + numCycles * clock; + // Note that currently finishTime can be smaller than + // firstWordTime if the packet has no data + pkt->finishTime = headerTime + numCycles * clockPeriod(); return headerTime; } template -BaseBus::Layer::Layer(BaseBus& _bus, const std::string& _name, - Tick _clock) : +BaseBus::Layer::Layer(BaseBus& _bus, const std::string& _name) : Drainable(), - bus(_bus), _name(_name), state(IDLE), clock(_clock), drainManager(NULL), + bus(_bus), _name(_name), state(IDLE), drainManager(NULL), releaseEvent(this) { } @@ -306,11 +302,8 @@ // snoop responses state = BUSY; - // determine the current time rounded to the closest following - // clock edge - Tick now = bus.nextCycle(); - - occupyLayer(now + clock); + // occupy the bus layer until the next cycle ends + occupyLayer(bus.clockEdge(Cycles(1))); } } diff -r 3a8a984feca6 -r d8e3bd9d3fc2 src/mem/cache/cache_impl.hh --- a/src/mem/cache/cache_impl.hh Mon Feb 18 13:45:36 2013 +0000 +++ b/src/mem/cache/cache_impl.hh Mon Feb 18 13:55:17 2013 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012 ARM Limited + * Copyright (c) 2010-2013 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -898,7 +898,7 @@ // responseLatency is the latency of the return path // from lower level caches/memory to an upper level cache or // the core. - completion_time = responseLatency * clock + + completion_time = responseLatency * clockPeriod() + (transfer_offset ? pkt->finishTime : pkt->firstWordTime); assert(!target->pkt->req->isUncacheable()); @@ -914,13 +914,15 @@ // responseLatency is the latency of the return path // from lower level caches/memory to an upper level cache or // the core. - completion_time = responseLatency * clock + pkt->finishTime; + completion_time = responseLatency * clockPeriod() + + pkt->finishTime; target->pkt->req->setExtraData(0); } else { // not a cache fill, just forwarding response // responseLatency is the latency of the return path // from lower level cahces/memory to the core. - completion_time = responseLatency * clock + pkt->finishTime; + completion_time = responseLatency * clockPeriod() + + pkt->finishTime; if (pkt->isRead() && !is_error) { target->pkt->setData(pkt->getPtr()); } diff -r 3a8a984feca6 -r d8e3bd9d3fc2 src/mem/cache/prefetch/base.cc --- a/src/mem/cache/prefetch/base.cc Mon Feb 18 13:45:36 2013 +0000 +++ b/src/mem/cache/prefetch/base.cc Mon Feb 18 13:55:17 2013 +0000 @@ -241,7 +241,7 @@ prefetch->req->setThreadContext(pkt->req->contextId(), pkt->req->threadId()); - prefetch->time = time + clock * *delayIter; + prefetch->time = time + clockPeriod() * *delayIter; // We just remove the head if we are full if (pf.size() == size) { diff -r 3a8a984feca6 -r d8e3bd9d3fc2 src/mem/coherent_bus.hh --- a/src/mem/coherent_bus.hh Mon Feb 18 13:45:36 2013 +0000 +++ b/src/mem/coherent_bus.hh Mon Feb 18 13:55:17 2013 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012 ARM Limited + * Copyright (c) 2011-2013 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall diff -r 3a8a984feca6 -r d8e3bd9d3fc2 src/mem/coherent_bus.cc --- a/src/mem/coherent_bus.cc Mon Feb 18 13:45:36 2013 +0000 +++ b/src/mem/coherent_bus.cc Mon Feb 18 13:55:17 2013 +0000 @@ -55,9 +55,9 @@ #include "sim/system.hh" CoherentBus::CoherentBus(const CoherentBusParams *p) - : BaseBus(p), reqLayer(*this, ".reqLayer", p->clock), - respLayer(*this, ".respLayer", p->clock), - snoopRespLayer(*this, ".snoopRespLayer", p->clock), + : BaseBus(p), reqLayer(*this, ".reqLayer"), + respLayer(*this, ".respLayer"), + snoopRespLayer(*this, ".snoopRespLayer"), system(p->system) { // create the ports based on the size of the master and slave diff -r 3a8a984feca6 -r d8e3bd9d3fc2 src/mem/noncoherent_bus.hh --- a/src/mem/noncoherent_bus.hh Mon Feb 18 13:45:36 2013 +0000 +++ b/src/mem/noncoherent_bus.hh Mon Feb 18 13:55:17 2013 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012 ARM Limited + * Copyright (c) 2011-2013 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall diff -r 3a8a984feca6 -r d8e3bd9d3fc2 src/mem/noncoherent_bus.cc --- a/src/mem/noncoherent_bus.cc Mon Feb 18 13:45:36 2013 +0000 +++ b/src/mem/noncoherent_bus.cc Mon Feb 18 13:55:17 2013 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012 ARM Limited + * Copyright (c) 2011-2013 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -55,8 +55,8 @@ #include "mem/noncoherent_bus.hh" NoncoherentBus::NoncoherentBus(const NoncoherentBusParams *p) - : BaseBus(p), reqLayer(*this, ".reqLayer", p->clock), - respLayer(*this, ".respLayer", p->clock) + : BaseBus(p), reqLayer(*this, ".reqLayer"), + respLayer(*this, ".respLayer") { // create the ports based on the size of the master and slave // vector ports, and the presence of the default port, the ports diff -r 3a8a984feca6 -r d8e3bd9d3fc2 src/mem/ruby/system/RubyMemoryControl.cc --- a/src/mem/ruby/system/RubyMemoryControl.cc Mon Feb 18 13:45:36 2013 +0000 +++ b/src/mem/ruby/system/RubyMemoryControl.cc Mon Feb 18 13:55:17 2013 +0000 @@ -557,7 +557,7 @@ bank, m_event.scheduled() ? 'Y':'N'); if (req.m_msgptr) { // don't enqueue L3 writebacks - enqueueToDirectory(req, m_mem_ctl_latency + m_mem_fixed_delay); + enqueueToDirectory(req, Cycles(m_mem_ctl_latency + m_mem_fixed_delay)); } m_oldRequest[bank] = 0; markTfaw(rank); @@ -702,7 +702,7 @@ m_idleCount--; if (m_idleCount > 0) { assert(!m_event.scheduled()); - schedule(m_event, curTick() + clock); + schedule(m_event, clockEdge(Cycles(1))); } } diff -r 3a8a984feca6 -r d8e3bd9d3fc2 src/sim/clocked_object.hh --- a/src/sim/clocked_object.hh Mon Feb 18 13:45:36 2013 +0000 +++ b/src/sim/clocked_object.hh Mon Feb 18 13:55:17 2013 +0000 @@ -103,11 +103,11 @@ tick += elapsedCycles * clock; } - protected: - // Clock period in ticks Tick clock; + protected: + /** * Create a clocked object and set the clock based on the * parameters.