diff -r 9b580403507a -r 351034b23e3b src/mem/cache/cache.hh
--- a/src/mem/cache/cache.hh	Thu Feb 14 09:58:01 2013 +0000
+++ b/src/mem/cache/cache.hh	Thu Feb 14 09:58:16 2013 +0000
@@ -234,6 +234,54 @@
     BlkType *handleFill(PacketPtr pkt, BlkType *blk,
                         PacketList &writebacks);
 
+
+    /**
+     * Performs the access specified by the request.
+     * @param pkt The request to perform.
+     * @return The result of the access.
+     */
+    bool recvTimingReq(PacketPtr pkt);
+
+    /**
+     * Handles a response (cache line fill/write ack) from the bus.
+     * @param pkt The response packet
+     */
+    void recvTimingResp(PacketPtr pkt);
+
+    /**
+     * Snoops bus transactions to maintain coherence.
+     * @param pkt The current bus transaction.
+     */
+    void recvTimingSnoopReq(PacketPtr pkt);
+
+    /**
+     * Handle a snoop response.
+     * @param pkt Snoop response packet
+     */
+    void recvTimingSnoopResp(PacketPtr pkt);
+
+    /**
+     * Performs the access specified by the request.
+     * @param pkt The request to perform.
+     * @return The number of cycles required for the access.
+     */
+    Cycles recvAtomic(PacketPtr pkt);
+
+    /**
+     * Snoop for the provided request in the cache and return the estimated
+     * time of completion.
+     * @param pkt The memory request to snoop
+     * @return The number of cycles required for the snoop.
+     */
+    Cycles recvAtomicSnoop(PacketPtr pkt);
+
+    /**
+     * Performs the access specified by the request.
+     * @param pkt The request to perform.
+     * @param fromCpuSide from the CPU side port or the memory side port
+     */
+    void functionalAccess(PacketPtr pkt, bool fromCpuSide);
+
     void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
                                bool deferred_response = false,
                                bool pending_downgrade = false);
@@ -291,47 +339,6 @@
     void uncacheableFlush(PacketPtr pkt);
 
     /**
-     * Performs the access specified by the request.
-     * @param pkt The request to perform.
-     * @return The result of the access.
-     */
-    bool timingAccess(PacketPtr pkt);
-
-    /**
-     * Performs the access specified by the request.
-     * @param pkt The request to perform.
-     * @return The number of ticks required for the access.
-     */
-    Tick atomicAccess(PacketPtr pkt);
-
-    /**
-     * Performs the access specified by the request.
-     * @param pkt The request to perform.
-     * @param fromCpuSide from the CPU side port or the memory side port
-     */
-    void functionalAccess(PacketPtr pkt, bool fromCpuSide);
-
-    /**
-     * Handles a response (cache line fill/write ack) from the bus.
-     * @param pkt The request being responded to.
-     */
-    void handleResponse(PacketPtr pkt);
-
-    /**
-     * Snoops bus transactions to maintain coherence.
-     * @param pkt The current bus transaction.
-     */
-    void snoopTiming(PacketPtr pkt);
-
-    /**
-     * Snoop for the provided request in the cache and return the estimated
-     * time of completion.
-     * @param pkt The memory request to snoop
-     * @return The number of cycles required for the snoop.
-     */
-    Cycles snoopAtomic(PacketPtr pkt);
-
-    /**
      * Squash all requests associated with specified thread.
      * intended for use by I-cache.
      * @param threadNum The thread to squash.
diff -r 9b580403507a -r 351034b23e3b src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh	Thu Feb 14 09:58:01 2013 +0000
+++ b/src/mem/cache/cache_impl.hh	Thu Feb 14 09:58:16 2013 +0000
@@ -367,10 +367,36 @@
     }
 };
 
+template<class TagStore>
+void
+Cache<TagStore>::recvTimingSnoopResp(PacketPtr pkt)
+{
+    Tick time = clockEdge(hitLatency);
+
+    assert(pkt->isResponse());
+
+    // must be cache-to-cache response from upper to lower level
+    ForwardResponseRecord *rec =
+        dynamic_cast<ForwardResponseRecord *>(pkt->senderState);
+
+    if (rec == NULL) {
+        assert(pkt->cmd == MemCmd::HardPFResp);
+        // Check if it's a prefetch response and handle it. We shouldn't
+        // get any other kinds of responses without FRRs.
+        DPRINTF(Cache, "Got prefetch response from above for addr %#x\n",
+                pkt->getAddr());
+        recvTimingResp(pkt);
+        return;
+    }
+
+    rec->restore(pkt, this);
+    delete rec;
+    memSidePort->schedTimingSnoopResp(pkt, time);
+}
 
 template<class TagStore>
 bool
-Cache<TagStore>::timingAccess(PacketPtr pkt)
+Cache<TagStore>::recvTimingReq(PacketPtr pkt)
 {
 //@todo Add back in MemDebug Calls
 //    MemDebug::cacheAccess(pkt);
@@ -385,27 +411,6 @@
     // we charge hitLatency for doing just about anything here
     Tick time = clockEdge(hitLatency);
 
-    if (pkt->isResponse()) {
-        // must be cache-to-cache response from upper to lower level
-        ForwardResponseRecord *rec =
-            dynamic_cast<ForwardResponseRecord *>(pkt->senderState);
-
-        if (rec == NULL) {
-            assert(pkt->cmd == MemCmd::HardPFResp);
-            // Check if it's a prefetch response and handle it. We shouldn't
-            // get any other kinds of responses without FRRs.
-            DPRINTF(Cache, "Got prefetch response from above for addr %#x\n",
-                    pkt->getAddr());
-            handleResponse(pkt);
-            return true;
-        }
-
-        rec->restore(pkt, this);
-        delete rec;
-        memSidePort->schedTimingSnoopResp(pkt, time);
-        return true;
-    }
-
     assert(pkt->isRequest());
 
     if (pkt->memInhibitAsserted()) {
@@ -620,8 +625,8 @@
 
 
 template<class TagStore>
-Tick
-Cache<TagStore>::atomicAccess(PacketPtr pkt)
+Cycles
+Cache<TagStore>::recvAtomic(PacketPtr pkt)
 {
     Cycles lat = hitLatency;
 
@@ -805,8 +810,10 @@
 
 template<class TagStore>
 void
-Cache<TagStore>::handleResponse(PacketPtr pkt)
+Cache<TagStore>::recvTimingResp(PacketPtr pkt)
 {
+    assert(pkt->isResponse());
+
     Tick time = clockEdge(hitLatency);
     MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
     bool is_error = pkt->isError();
@@ -1355,7 +1362,7 @@
 
 template<class TagStore>
 void
-Cache<TagStore>::snoopTiming(PacketPtr pkt)
+Cache<TagStore>::recvTimingSnoopReq(PacketPtr pkt)
 {
     // Note that some deferred snoops don't have requests, since the
     // original access may have already completed
@@ -1433,13 +1440,13 @@
 Cache<TagStore>::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
 {
     // Express snoop responses from master to slave, e.g., from L1 to L2
-    cache->timingAccess(pkt);
+    cache->recvTimingSnoopResp(pkt);
     return true;
 }
 
 template<class TagStore>
 Cycles
-Cache<TagStore>::snoopAtomic(PacketPtr pkt)
+Cache<TagStore>::recvAtomicSnoop(PacketPtr pkt)
 {
     if (pkt->req->isUncacheable() || pkt->cmd == MemCmd::Writeback) {
         // Can't get a hit on an uncacheable address
@@ -1561,7 +1568,7 @@
         pkt->cmd = MemCmd::UpgradeFailResp;
         pkt->senderState = mshr;
         pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
-        handleResponse(pkt);
+        recvTimingResp(pkt);
         return NULL;
     } else if (mshr->isForwardNoResponse()) {
         // no response expected, just forward packet as it is
@@ -1691,7 +1698,7 @@
         return false;
     }
 
-    cache->timingAccess(pkt);
+    cache->recvTimingReq(pkt);
     return true;
 }
 
@@ -1699,8 +1706,9 @@
 Tick
 Cache<TagStore>::CpuSidePort::recvAtomic(PacketPtr pkt)
 {
-    // atomic request
-    return cache->atomicAccess(pkt);
+    // @todo: Note that this is currently using cycles instead of
+    // ticks and will be fixed in a future patch
+    return cache->recvAtomic(pkt);
 }
 
 template<class TagStore>
@@ -1729,7 +1737,7 @@
 bool
 Cache<TagStore>::MemSidePort::recvTimingResp(PacketPtr pkt)
 {
-    cache->handleResponse(pkt);
+    cache->recvTimingResp(pkt);
     return true;
 }
 
@@ -1739,15 +1747,16 @@
 Cache<TagStore>::MemSidePort::recvTimingSnoopReq(PacketPtr pkt)
 {
     // handle snooping requests
-    cache->snoopTiming(pkt);
+    cache->recvTimingSnoopReq(pkt);
 }
 
 template<class TagStore>
 Tick
 Cache<TagStore>::MemSidePort::recvAtomicSnoop(PacketPtr pkt)
 {
-    // atomic snoop
-    return cache->snoopAtomic(pkt);
+    // @todo: Note that this is using cycles and not ticks and will be
+    // fixed in a future patch
+    return cache->recvAtomicSnoop(pkt);
 }
 
 template<class TagStore>