diff -r 351034b23e3b -r 523d0e0d4f36 src/dev/io_device.cc --- a/src/dev/io_device.cc Thu Feb 14 09:58:16 2013 +0000 +++ b/src/dev/io_device.cc Thu Feb 14 09:58:31 2013 +0000 @@ -54,6 +54,9 @@ Tick PioPort::recvAtomic(PacketPtr pkt) { + // @todo: We need to pay for this and not just zero it out + pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; + return pkt->isRead() ? device->read(pkt) : device->write(pkt); } diff -r 351034b23e3b -r 523d0e0d4f36 src/dev/pcidev.cc --- a/src/dev/pcidev.cc Thu Feb 14 09:58:16 2013 +0000 +++ b/src/dev/pcidev.cc Thu Feb 14 09:58:31 2013 +0000 @@ -67,6 +67,8 @@ { assert(pkt->getAddr() >= configAddr && pkt->getAddr() < configAddr + PCI_CONFIG_SIZE); + // @todo someone should pay for this + pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; return pkt->isRead() ? device->readConfig(pkt) : device->writeConfig(pkt); } diff -r 351034b23e3b -r 523d0e0d4f36 src/dev/x86/intdev.hh --- a/src/dev/x86/intdev.hh Thu Feb 14 09:58:16 2013 +0000 +++ b/src/dev/x86/intdev.hh Thu Feb 14 09:58:31 2013 +0000 @@ -81,6 +81,8 @@ Tick recvMessage(PacketPtr pkt) { + // @todo someone should pay for this + pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; return device->recvMessage(pkt); } }; diff -r 351034b23e3b -r 523d0e0d4f36 src/mem/bridge.cc --- a/src/mem/bridge.cc Thu Feb 14 09:58:16 2013 +0000 +++ b/src/mem/bridge.cc Thu Feb 14 09:58:31 2013 +0000 @@ -141,6 +141,9 @@ DPRINTF(Bridge, "Request queue size: %d\n", transmitList.size()); + // @todo: We need to pay for this and not just zero it out + pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; + slavePort.schedTimingResp(pkt, bridge.clockEdge(delay)); return true; @@ -171,6 +174,10 @@ assert(outstandingResponses != respQueueLimit); ++outstandingResponses; retryReq = false; + + // @todo: We need to pay for this and not just zero it out + pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; + masterPort.schedTimingReq(pkt, bridge.clockEdge(delay)); } } diff -r 351034b23e3b -r 523d0e0d4f36 src/mem/bus.cc --- a/src/mem/bus.cc Thu Feb 14 09:58:16 2013 +0000 +++ b/src/mem/bus.cc Thu Feb 14 09:58:31 2013 +0000 @@ -140,6 +140,13 @@ // determine how many cycles are needed to send the data unsigned dataCycles = pkt->hasData() ? divCeil(pkt->getSize(), width) : 0; + // before setting the bus delay fields of the packet, ensure that + // the delay from any previous bus has been accounted for + if (pkt->busFirstWordDelay != 0 || pkt->busLastWordDelay != 0) + panic("Packet %s already has bus delay (%d, %d) that should be " + "accounted for.\n", pkt->cmdString(), pkt->busFirstWordDelay, + pkt->busLastWordDelay); + // The first word will be delivered on the cycle after the header. pkt->busFirstWordDelay = (headerCycles + 1) * clockPeriod() + offset; diff -r 351034b23e3b -r 523d0e0d4f36 src/mem/cache/cache_impl.hh --- a/src/mem/cache/cache_impl.hh Thu Feb 14 09:58:16 2013 +0000 +++ b/src/mem/cache/cache_impl.hh Thu Feb 14 09:58:31 2013 +0000 @@ -391,6 +391,8 @@ rec->restore(pkt, this); delete rec; + // @todo someone should pay for this + pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; memSidePort->schedTimingSnoopResp(pkt, time); } @@ -423,6 +425,9 @@ // supplier had exclusive copy to begin with. if (pkt->needsExclusive() && !pkt->isSupplyExclusive()) { Packet *snoopPkt = new Packet(pkt, true); // clear flags + // also reset the bus time that the original packet has + // not yet paid for + snoopPkt->busFirstWordDelay = snoopPkt->busLastWordDelay = 0; snoopPkt->setExpressSnoop(); snoopPkt->assertMemInhibit(); memSidePort->sendTimingReq(snoopPkt); @@ -441,6 +446,9 @@ if (pkt->req->isUncacheable()) { uncacheableFlush(pkt); + // @todo: someone should pay for this + pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; + // writes go in write buffer, reads use MSHR if (pkt->isWrite() && !pkt->isRead()) { allocateWriteBuffer(pkt, time, true); @@ -493,6 +501,8 @@ if (needsResponse) { pkt->makeTimingResponse(); + // @todo: Make someone pay for this + pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; cpuSidePort->schedTimingResp(pkt, clockEdge(lat)); } else { /// @todo nominally we should just delete the packet here, @@ -503,6 +513,9 @@ } else { // miss + // @todo: Make someone pay for this + pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; + Addr blk_addr = blockAlign(pkt->getAddr()); MSHR *mshr = mshrQueue.findMatch(blk_addr); @@ -935,6 +948,8 @@ // isInvalidate() set otherwise. target->pkt->cmd = MemCmd::ReadRespWithInvalidate; } + // reset the bus additional time as it is now accounted for + target->pkt->busFirstWordDelay = target->pkt->busLastWordDelay = 0; cpuSidePort->schedTimingResp(target->pkt, completion_time); break; @@ -1239,6 +1254,8 @@ assert(req_pkt->isInvalidate() || pkt->sharedAsserted()); pkt->allocate(); pkt->makeTimingResponse(); + // @todo Make someone pay for this + pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; if (pkt->isRead()) { pkt->setDataFromBlock(blk_data, blkSize); } @@ -1282,6 +1299,9 @@ Packet snoopPkt(pkt, true); // clear flags snoopPkt.setExpressSnoop(); snoopPkt.senderState = new ForwardResponseRecord(pkt, this); + // the snoop packet does not need to wait any additional + // time + snoopPkt.busFirstWordDelay = snoopPkt.busLastWordDelay = 0; cpuSidePort->sendTimingSnoopReq(&snoopPkt); if (snoopPkt.memInhibitAsserted()) { // cache-to-cache response from some upper cache diff -r 351034b23e3b -r 523d0e0d4f36 src/mem/coherent_bus.cc --- a/src/mem/coherent_bus.cc Thu Feb 14 09:58:16 2013 +0000 +++ b/src/mem/coherent_bus.cc Thu Feb 14 09:58:31 2013 +0000 @@ -177,6 +177,9 @@ if (add_outstanding) outstandingReq.erase(pkt->req); + // undo the calculation so we can check for 0 again + pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; + DPRINTF(CoherentBus, "recvTimingReq: src %s %s 0x%x RETRY\n", src_port->name(), pkt->cmdString(), pkt->getAddr()); diff -r 351034b23e3b -r 523d0e0d4f36 src/mem/noncoherent_bus.cc --- a/src/mem/noncoherent_bus.cc Thu Feb 14 09:58:16 2013 +0000 +++ b/src/mem/noncoherent_bus.cc Thu Feb 14 09:58:31 2013 +0000 @@ -124,6 +124,9 @@ DPRINTF(NoncoherentBus, "recvTimingReq: src %s %s 0x%x RETRY\n", src_port->name(), pkt->cmdString(), pkt->getAddr()); + // undo the calculation so we can check for 0 again + pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; + // occupy until the header is sent reqLayer.failedTiming(src_port, clockEdge(Cycles(headerCycles))); diff -r 351034b23e3b -r 523d0e0d4f36 src/mem/simple_dram.cc --- a/src/mem/simple_dram.cc Thu Feb 14 09:58:16 2013 +0000 +++ b/src/mem/simple_dram.cc Thu Feb 14 09:58:31 2013 +0000 @@ -741,6 +741,9 @@ // access already turned the packet into a response assert(pkt->isResponse()); + // @todo someone should pay for this + pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; + // queue the packet in the response queue to be sent out the // next tick port.schedTimingResp(pkt, curTick() + 1); diff -r 351034b23e3b -r 523d0e0d4f36 src/mem/simple_mem.cc --- a/src/mem/simple_mem.cc Thu Feb 14 09:58:16 2013 +0000 +++ b/src/mem/simple_mem.cc Thu Feb 14 09:58:31 2013 +0000 @@ -121,6 +121,9 @@ return false; } + // @todo someone should pay for this + pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; + // update the release time according to the bandwidth limit, and // do so with respect to the time it takes to finish this request // rather than long term as it is the short term data rate that is