diff -r 9934883ab246 -r b2c1502e2508 configs/example/se.py --- a/configs/example/se.py Sat Feb 23 00:40:44 2013 -0600 +++ b/configs/example/se.py Sat Feb 23 00:40:54 2013 -0600 @@ -187,6 +187,9 @@ print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" sys.exit(1) + # Set the option for physmem so that it is not allocated any space + system.physmem.null = True + options.use_map = True Ruby.create_system(options, system) assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) diff -r 9934883ab246 -r b2c1502e2508 src/mem/ruby/system/Sequencer.py --- a/src/mem/ruby/system/Sequencer.py Sat Feb 23 00:40:44 2013 -0600 +++ b/src/mem/ruby/system/Sequencer.py Sat Feb 23 00:40:54 2013 -0600 @@ -41,7 +41,7 @@ pio_port = MasterPort("Ruby_pio_port") using_ruby_tester = Param.Bool(False, "") using_network_tester = Param.Bool(False, "") - access_phys_mem = Param.Bool(True, + access_phys_mem = Param.Bool(False, "should the rubyport atomically update phys_mem") ruby_system = Param.RubySystem("") system = Param.System(Parent.any, "system object") @@ -52,6 +52,7 @@ class RubyPortProxy(RubyPort): type = 'RubyPortProxy' cxx_header = "mem/ruby/system/RubyPortProxy.hh" + access_phys_mem = True class RubySequencer(RubyPort): type = 'RubySequencer' @@ -67,3 +68,4 @@ class DMASequencer(RubyPort): type = 'DMASequencer' cxx_header = "mem/ruby/system/DMASequencer.hh" + access_phys_mem = True diff -r 9934883ab246 -r b2c1502e2508 tests/configs/memtest-ruby.py --- a/tests/configs/memtest-ruby.py Sat Feb 23 00:40:44 2013 -0600 +++ b/tests/configs/memtest-ruby.py Sat Feb 23 00:40:54 2013 -0600 @@ -79,8 +79,8 @@ # system simulated system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), - funcbus = NoncoherentBus(), - physmem = SimpleMemory()) + physmem = SimpleMemory(null = True), + funcbus = NoncoherentBus()) Ruby.create_system(options, system) @@ -100,12 +100,6 @@ # ruby_port.deadlock_threshold = 1000000 - # - # Ruby doesn't need the backing image of memory when running with - # the tester. - # - ruby_port.access_phys_mem = False - # connect reference memory to funcbus system.funcmem.port = system.funcbus.master diff -r 9934883ab246 -r b2c1502e2508 tests/configs/pc-simple-timing-ruby.py --- a/tests/configs/pc-simple-timing-ruby.py Sat Feb 23 00:40:44 2013 -0600 +++ b/tests/configs/pc-simple-timing-ruby.py Sat Feb 23 00:40:54 2013 -0600 @@ -74,5 +74,8 @@ cpu.interrupts.int_slave = system.piobus.master cpu.clock = '2GHz' + # Set access_phys_mem to True for ruby port + system.ruby._cpu_ruby_ports[i].access_phys_mem = True + root = Root(full_system = True, system = system) m5.ticks.setGlobalFrequency('1THz') diff -r 9934883ab246 -r b2c1502e2508 tests/configs/rubytest-ruby.py --- a/tests/configs/rubytest-ruby.py Sat Feb 23 00:40:44 2013 -0600 +++ b/tests/configs/rubytest-ruby.py Sat Feb 23 00:40:54 2013 -0600 @@ -77,7 +77,7 @@ tester = RubyTester(check_flush = check_flush, checks_to_complete = 100, wakeup_frequency = 10, num_cpus = options.num_cpus) -system = System(tester = tester, physmem = SimpleMemory()) +system = System(tester = tester, physmem = SimpleMemory(null = True)) Ruby.create_system(options, system) @@ -104,12 +104,6 @@ # ruby_port.using_ruby_tester = True - # - # Ruby doesn't need the backing image of memory when running with - # the tester. - # - ruby_port.access_phys_mem = False - # ----------------------- # run simulation # ----------------------- diff -r 9934883ab246 -r b2c1502e2508 tests/configs/simple-timing-ruby.py --- a/tests/configs/simple-timing-ruby.py Sat Feb 23 00:40:44 2013 -0600 +++ b/tests/configs/simple-timing-ruby.py Sat Feb 23 00:40:54 2013 -0600 @@ -67,7 +67,7 @@ options.num_cpus = 1 cpu = TimingSimpleCPU(cpu_id=0) -system = System(cpu = cpu, physmem = SimpleMemory()) +system = System(cpu = cpu, physmem = SimpleMemory(null = True)) Ruby.create_system(options, system)