diff -r 8149223cd7db -r 8ce21a3abbfe src/arch/arm/isa/templates/mem.isa
--- a/src/arch/arm/isa/templates/mem.isa	Fri Feb 15 17:40:14 2013 -0500
+++ b/src/arch/arm/isa/templates/mem.isa	Mon Feb 25 12:59:12 2013 -0500
@@ -1122,7 +1122,7 @@
 #if %(use_uops)d
         assert(numMicroops >= 2);
         uops = new StaticInstPtr[numMicroops];
-        if (_dest == INTREG_PC) {
+        if (_dest == INTREG_PC && !isFloating()) {
             IntRegIndex wbIndexReg = index;
             uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
                                        _shiftAmt, _shiftType, _index);
@@ -1156,7 +1156,7 @@
 
         }
 #else
-        if (_dest == INTREG_PC) {
+        if (_dest == INTREG_PC && !isFloating()) {
             flags[IsControl] = true;
             flags[IsIndirectControl] = true;
             if (conditional)
@@ -1185,7 +1185,7 @@
 #if %(use_uops)d
         assert(numMicroops >= 2);
         uops = new StaticInstPtr[numMicroops];
-        if (_dest == INTREG_PC) {
+        if (_dest == INTREG_PC && !isFloating()) {
             uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
                                    _imm);
             uops[0]->setDelayedCommit();
@@ -1208,7 +1208,7 @@
             uops[1]->setLastMicroop();
         }
 #else
-        if (_dest == INTREG_PC) {
+        if (_dest == INTREG_PC && !isFloating()) {
             flags[IsControl] = true;
             flags[IsIndirectControl] = true;
             if (conditional)
diff -r 8149223cd7db -r 8ce21a3abbfe src/arch/arm/isa/templates/pred.isa
--- a/src/arch/arm/isa/templates/pred.isa	Fri Feb 15 17:40:14 2013 -0500
+++ b/src/arch/arm/isa/templates/pred.isa	Mon Feb 25 12:59:12 2013 -0500
@@ -77,7 +77,7 @@
             }
         }
 
-        if (%(is_branch)s){
+        if (%(is_branch)s && !isFloating()){
             flags[IsControl] = true;
             flags[IsIndirectControl] = true;
             if (condCode == COND_AL || condCode == COND_UC)
@@ -117,7 +117,7 @@
             }
         }
 
-        if (%(is_branch)s){
+        if (%(is_branch)s && !isFloating()){
             flags[IsControl] = true;
             flags[IsIndirectControl] = true;
             if (condCode == COND_AL || condCode == COND_UC)