diff -r b9af1c29615b -r 84fb0f960efe src/arch/arm/isa/templates/mem.isa
--- a/src/arch/arm/isa/templates/mem.isa	Fri Aug 13 11:51:51 2010 -0500
+++ b/src/arch/arm/isa/templates/mem.isa	Fri Aug 13 11:52:20 2010 -0500
@@ -69,6 +69,8 @@
             if (fault == NoFault) {
                 %(op_wb)s;
             }
+        } else {
+            xc->setPredicatedFalse(true);
         }
 
         if (fault == NoFault && machInst.itstateMask != 0) {
@@ -103,6 +105,8 @@
             if (fault == NoFault) {
                 %(op_wb)s;
             }
+        } else {
+            xc->setPredicatedFalse(true);
         }
 
         if (fault == NoFault && machInst.itstateMask != 0) {
@@ -164,6 +168,8 @@
             if (fault == NoFault) {
                 %(op_wb)s;
             }
+        } else {
+            xc->setPredicatedFalse(true);
         }
 
         if (fault == NoFault && machInst.itstateMask != 0) {
@@ -200,6 +206,8 @@
             if (fault == NoFault) {
                 %(op_wb)s;
             }
+        } else {
+            xc->setPredicatedFalse(true);
         }
 
         if (fault == NoFault && machInst.itstateMask != 0) {
@@ -242,6 +250,8 @@
             if (fault == NoFault) {
                 %(op_wb)s;
             }
+        } else {
+            xc->setPredicatedFalse(true);
         }
 
         if (fault == NoFault && machInst.itstateMask != 0) {
@@ -279,6 +289,8 @@
             if (fault == NoFault) {
                 %(op_wb)s;
             }
+        } else {
+            xc->setPredicatedFalse(true);
         }
 
         if (fault == NoFault && machInst.itstateMask != 0) {
@@ -316,6 +328,8 @@
             if (fault == NoFault) {
                 %(op_wb)s;
             }
+        } else {
+            xc->setPredicatedFalse(true);
         }
 
         if (fault == NoFault && machInst.itstateMask != 0) {
@@ -342,8 +356,11 @@
             if (fault == NoFault) {
                 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
             }
-        } else if (fault == NoFault && machInst.itstateMask != 0) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
+        } else {
+            xc->setPredicatedFalse(true);
+            if (fault == NoFault && machInst.itstateMask != 0) {
+                xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
+            }
         }
 
         return fault;
diff -r b9af1c29615b -r 84fb0f960efe src/arch/arm/isa/templates/pred.isa
--- a/src/arch/arm/isa/templates/pred.isa	Fri Aug 13 11:51:51 2010 -0500
+++ b/src/arch/arm/isa/templates/pred.isa	Fri Aug 13 11:52:20 2010 -0500
@@ -142,6 +142,8 @@
             {
                 %(op_wb)s;
             }
+        } else {
+            xc->setPredicatedFalse(true);
         }
 
         if (fault == NoFault && machInst.itstateMask != 0) {
diff -r b9af1c29615b -r 84fb0f960efe src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh	Fri Aug 13 11:51:51 2010 -0500
+++ b/src/cpu/base_dyn_inst.hh	Fri Aug 13 11:52:20 2010 -0500
@@ -246,6 +246,9 @@
     /** Micro PC of this instruction. */
     Addr microPC;
 
+    /** This instruction is predicated false */
+    bool predicatedFalse;
+
   protected:
     /** Next non-speculative PC.  It is not filled in at fetch, but rather
      *  once the target of the branch is truly known (either decode or
@@ -794,6 +797,16 @@
         nextMicroPC = val;
     }
 
+    bool readPredicatedFalse()
+    {
+        return predicatedFalse;
+    }
+
+    void setPredicatedFalse(bool val)
+    {
+        predicatedFalse = val;
+    }
+
     /** Sets the ASID. */
     void setASID(short addr_space_id) { asid = addr_space_id; }
 
diff -r b9af1c29615b -r 84fb0f960efe src/cpu/base_dyn_inst_impl.hh
--- a/src/cpu/base_dyn_inst_impl.hh	Fri Aug 13 11:51:51 2010 -0500
+++ b/src/cpu/base_dyn_inst_impl.hh	Fri Aug 13 11:52:20 2010 -0500
@@ -154,6 +154,7 @@
 
     eaCalcDone = false;
     memOpDone = false;
+    predicatedFalse = false;
 
     lqIdx = -1;
     sqIdx = -1;
diff -r b9af1c29615b -r 84fb0f960efe src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh	Fri Aug 13 11:51:51 2010 -0500
+++ b/src/cpu/o3/lsq_unit_impl.hh	Fri Aug 13 11:52:20 2010 -0500
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2004-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -439,9 +451,9 @@
 
     load_fault = inst->initiateAcc();
 
-    // If the instruction faulted, then we need to send it along to commit
-    // without the instruction completing.
-    if (load_fault != NoFault) {
+    // If the instruction faulted or predicated false, then we need to send it
+    // along to commit without the instruction completing.
+    if (load_fault != NoFault || inst->readPredicatedFalse()) {
         // Send this instruction to commit, also make sure iew stage
         // realizes there is activity.
         // Mark it as executed unless it is an uncached load that
diff -r b9af1c29615b -r 84fb0f960efe src/cpu/simple/base.hh
--- a/src/cpu/simple/base.hh	Fri Aug 13 11:51:51 2010 -0500
+++ b/src/cpu/simple/base.hh	Fri Aug 13 11:52:20 2010 -0500
@@ -287,12 +287,15 @@
     uint64_t readNextPC() { return thread->readNextPC(); }
     uint64_t readNextMicroPC() { return thread->readNextMicroPC(); }
     uint64_t readNextNPC() { return thread->readNextNPC(); }
+    bool readPredicatedFalse() { return thread->readPredicatedFalse(); }
 
     void setPC(uint64_t val) { thread->setPC(val); }
     void setMicroPC(uint64_t val) { thread->setMicroPC(val); }
     void setNextPC(uint64_t val) { thread->setNextPC(val); }
     void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
     void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
+    void setPredicatedFalse(bool val)
+    { return thread->setPredicatedFalse(val); }
 
     MiscReg readMiscRegNoEffect(int misc_reg)
     {
diff -r b9af1c29615b -r 84fb0f960efe src/cpu/simple_thread.hh
--- a/src/cpu/simple_thread.hh	Fri Aug 13 11:51:51 2010 -0500
+++ b/src/cpu/simple_thread.hh	Fri Aug 13 11:52:20 2010 -0500
@@ -128,6 +128,9 @@
      */
     Addr nextNPC;
 
+    /** This instruction is predicated false */
+    bool predicatedFalse;
+
   public:
     // pointer to CPU associated with this SimpleThread
     BaseCPU *cpu;
@@ -371,6 +374,16 @@
 #endif
     }
 
+    bool readPredicatedFalse()
+    {
+        return predicatedFalse;
+    }
+
+    void setPredicatedFalse(bool val)
+    {
+        predicatedFalse = val;
+    }
+
     MiscReg
     readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
     {
diff -r b9af1c29615b -r 84fb0f960efe src/cpu/thread_context.hh
--- a/src/cpu/thread_context.hh	Fri Aug 13 11:51:51 2010 -0500
+++ b/src/cpu/thread_context.hh	Fri Aug 13 11:52:20 2010 -0500
@@ -404,6 +404,11 @@
 
     void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); }
 
+    bool readPredicatedFalse() { return actualTC->readPredicatedFalse(); }
+
+    void setPredicatedFalse(bool val)
+    { actualTC->setPredicatedFalse(val); }
+
     MiscReg readMiscRegNoEffect(int misc_reg)
     { return actualTC->readMiscRegNoEffect(misc_reg); }