diff -r b0201499d299 -r 8a28abceaef2 src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh	Fri Aug 13 11:53:01 2010 -0500
+++ b/src/cpu/base_dyn_inst.hh	Fri Aug 13 11:53:19 2010 -0500
@@ -805,6 +805,10 @@
     void setPredicatedFalse(bool val)
     {
         predicatedFalse = val;
+
+        if (traceData) {
+            traceData->setPredicatedFalse(val);
+        }
     }
 
     /** Sets the ASID. */
diff -r b0201499d299 -r 8a28abceaef2 src/cpu/exetrace.cc
--- a/src/cpu/exetrace.cc	Fri Aug 13 11:53:01 2010 -0500
+++ b/src/cpu/exetrace.cc	Fri Aug 13 11:53:19 2010 -0500
@@ -111,6 +111,10 @@
             outs << Enums::OpClassStrings[inst->opClass()] << " : ";
         }
 
+        if (IsOn(ExecResult) && predicatedFalse) {
+            outs << "Predicated False";
+        }
+
         if (IsOn(ExecResult) && data_status != DataInvalid) {
             ccprintf(outs, " D=%#018x", data.as_int);
         }
diff -r b0201499d299 -r 8a28abceaef2 src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh	Fri Aug 13 11:53:01 2010 -0500
+++ b/src/cpu/o3/lsq_unit_impl.hh	Fri Aug 13 11:53:19 2010 -0500
@@ -458,6 +458,9 @@
         // realizes there is activity.
         // Mark it as executed unless it is an uncached load that
         // needs to hit the head of commit.
+        DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n",
+                inst->seqNum,
+                (load_fault != NoFault ? "fault" : "predication"));
         if (!(inst->hasRequest() && inst->uncacheable()) ||
             inst->isAtCommit()) {
             inst->setExecuted();
diff -r b0201499d299 -r 8a28abceaef2 src/cpu/simple/base.hh
--- a/src/cpu/simple/base.hh	Fri Aug 13 11:53:01 2010 -0500
+++ b/src/cpu/simple/base.hh	Fri Aug 13 11:53:19 2010 -0500
@@ -295,7 +295,12 @@
     void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
     void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
     void setPredicatedFalse(bool val)
-    { return thread->setPredicatedFalse(val); }
+    {
+        thread->setPredicatedFalse(val);
+        if (traceData) {
+            traceData->setPredicatedFalse(val);
+        }
+    }
 
     MiscReg readMiscRegNoEffect(int misc_reg)
     {
diff -r b0201499d299 -r 8a28abceaef2 src/sim/insttracer.hh
--- a/src/sim/insttracer.hh	Fri Aug 13 11:53:01 2010 -0500
+++ b/src/sim/insttracer.hh	Fri Aug 13 11:53:19 2010 -0500
@@ -58,6 +58,7 @@
     StaticInstPtr macroStaticInst;
     MicroPC upc;
     bool misspeculating;
+    bool predicatedFalse;
 
     // The remaining fields are only valid for particular instruction
     // types (e.g, addresses for memory ops) or when particular
@@ -102,6 +103,7 @@
 
         fetch_seq_valid = false;
         cp_seq_valid = false;
+        predicatedFalse = false;
     }
 
     virtual ~InstRecord() { }
@@ -128,6 +130,8 @@
     void setCPSeq(InstSeqNum seq)
     { cp_seq = seq; cp_seq_valid = true; }
 
+    void setPredicatedFalse(bool val) { predicatedFalse = val; }
+
     virtual void dump() = 0;
     
   public: