diff -r ba4933c9a1b9 -r e5f0194b3034 src/mem/SimpleDRAM.py
--- a/src/mem/SimpleDRAM.py	Thu Mar 28 10:36:53 2013 +0000
+++ b/src/mem/SimpleDRAM.py	Thu Mar 28 10:37:19 2013 +0000
@@ -43,10 +43,12 @@
 # First-Served and a First-Row Hit then First-Come First-Served
 class MemSched(Enum): vals = ['fcfs', 'frfcfs']
 
-# Enum for the address mapping, currently corresponding to either
+# Enum for the address mapping. With Ra, Co, Ba and Ch denoting rank,
+# column, bank and channel, respectively, and going from MSB to LSB,
+# the two schemes available are RaBaChCo and CoRaBaCh, either
 # optimising for sequential accesses hitting in the open row, or
-# striping across banks.
-class AddrMap(Enum): vals = ['openmap', 'closemap']
+# maximising parallelism.
+class AddrMap(Enum): vals = ['RaBaChCo', 'CoRaBaCh']
 
 # Enum for the page policy, either open or close.
 class PageManage(Enum): vals = ['open', 'close']
@@ -105,7 +107,7 @@
 
     # scheduler, address map and page policy
     mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
-    addr_mapping = Param.AddrMap('openmap', "Address mapping policy")
+    addr_mapping = Param.AddrMap('RaBaChCo', "Address mapping policy")
     page_policy = Param.PageManage('open', "Page closure management policy")
 
     # the physical organisation of the DRAM
diff -r ba4933c9a1b9 -r e5f0194b3034 src/mem/simple_dram.cc
--- a/src/mem/simple_dram.cc	Thu Mar 28 10:36:53 2013 +0000
+++ b/src/mem/simple_dram.cc	Thu Mar 28 10:37:19 2013 +0000
@@ -112,15 +112,15 @@
             panic("%s has %d interleaved address stripes but %d channel(s)\n",
                   name(), range.stripes(), channels);
 
-        if (addrMapping == Enums::openmap) {
+        if (addrMapping == Enums::RaBaChCo) {
             if (bytesPerCacheLine * linesPerRowBuffer !=
                 range.granularity()) {
-                panic("Interleaving of %s doesn't match open address map\n",
+                panic("Interleaving of %s doesn't match RaBaChCo address map\n",
                       name());
             }
-        } else if (addrMapping == Enums::closemap) {
+        } else if (addrMapping == Enums::CoRaBaCh) {
             if (bytesPerCacheLine != range.granularity())
-                panic("Interleaving of %s doesn't match closed address map\n",
+                panic("Interleaving of %s doesn't match CoRaBaCh address map\n",
                       name());
         }
     }
@@ -175,9 +175,9 @@
 {
     // decode the address based on the address mapping scheme
     //
-    // with R, C, B and K denoting rank, column, bank and rank,
+    // with Ra, Co, Ba and Ch denoting rank, column, bank and channel,
     // respectively, and going from MSB to LSB, the two schemes are
-    // RKBC (openmap) and RCKB (closedmap)
+    // RaBaChCo and CoRaBaCh
     uint8_t rank;
     uint16_t bank;
     uint16_t row;
@@ -191,7 +191,7 @@
     // position within the cache line, proceed and select the
     // appropriate bits for bank, rank and row (no column address is
     // needed)
-    if (addrMapping == Enums::openmap) {
+    if (addrMapping == Enums::RaBaChCo) {
         // the lowest order bits denote the column to ensure that
         // sequential cache lines occupy the same row
         addr = addr / linesPerRowBuffer;
@@ -201,7 +201,7 @@
         // controllers in the address mapping
         addr = addr / channels;
 
-        // after the column bits, we get the bank bits to interleave
+        // after the channel bits, we get the bank bits to interleave
         // over the banks
         bank = addr % banksPerRank;
         addr = addr / banksPerRank;
@@ -214,7 +214,7 @@
         // lastly, get the row bits
         row = addr % rowsPerBank;
         addr = addr / rowsPerBank;
-    } else if (addrMapping == Enums::closemap) {
+    } else if (addrMapping == Enums::CoRaBaCh) {
         // optimise for closed page mode and utilise maximum
         // parallelism of the DRAM (at the cost of power)
 
@@ -473,8 +473,8 @@
             linesPerRowBuffer * rowsPerBank * banksPerRank * ranksPerChannel);
 
     string scheduler =  memSchedPolicy == Enums::fcfs ? "FCFS" : "FR-FCFS";
-    string address_mapping = addrMapping == Enums::openmap ? "OPENMAP" :
-        "CLOSEMAP";
+    string address_mapping = addrMapping == Enums::RaBaChCo ? "RaBaChCo" :
+        "CoRaBaCh";
     string page_policy = pageMgmt == Enums::open ? "OPEN" : "CLOSE";
 
     DPRINTF(DRAM,