diff -r f858281a4060 -r 1aa1ea2c0c9b src/mem/cache/cache_impl.hh --- a/src/mem/cache/cache_impl.hh Tue Apr 16 17:41:55 2013 -0700 +++ b/src/mem/cache/cache_impl.hh Tue Apr 16 18:01:53 2013 -0700 @@ -526,14 +526,16 @@ pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; cpuSidePort->schedTimingResp(pkt, clockEdge(lat)); // Mark the corresponding bank in service - bank[bankId]->markInService(clockEdge(lat)); + if (enableBankModel) + bank[bankId]->markInService(clockEdge(lat)); } else { /// @todo nominally we should just delete the packet here, /// however, until 4-phase stuff we can't because sending /// cache is still relying on it pendingDelete.push_back(pkt); // Mark the corresponding bank in service - bank[bankId]->markInService(clockEdge(lat)); + if (enableBankModel) + bank[bankId]->markInService(clockEdge(lat)); } } else { // miss @@ -919,12 +921,14 @@ blk = handleFill(pkt, blk, writebacks); assert(blk != NULL); - // mark the corresponding bank in service - unsigned bankId = getBankId(pkt->getAddr()); - if (bank[bankId]->isBusy()) { - bank[bankId]->extendService(writeLatency * clockPeriod()); - } else { - bank[bankId]->markInService(clockEdge(writeLatency)); + if (enableBankModel) { + // mark the corresponding bank in service + unsigned bankId = getBankId(pkt->getAddr()); + if (bank[bankId]->isBusy()) { + bank[bankId]->extendService(writeLatency * clockPeriod()); + } else { + bank[bankId]->markInService(clockEdge(writeLatency)); + } } } @@ -1771,12 +1775,14 @@ // nextIdleTick expires, but we will need to create new events to do that. // Instead, we only check-and-unmark the inService bit before we really // want to know the bank status. - for (unsigned i = 0; i < cache->bank.size(); ++i) - if (cache->bank[i]->serviceDone()) - cache->bank[i]->clearInService(); + if (cache->enableBankModel) + for (unsigned i = 0; i < cache->bank.size(); ++i) + if (cache->bank[i]->serviceDone()) + cache->bank[i]->clearInService(); unsigned bankId = cache->getBankId(pkt->getAddr()); - bool inService = cache->bank[bankId]->isBusy(); + bool inService = cache->enableBankModel && cache->bank[bankId]->isBusy(); + // always let inhibited requests through even if blocked if (!pkt->memInhibitAsserted() && (blocked || inService)) { assert(!cache->system->bypassCaches()); @@ -1839,9 +1845,10 @@ // nextIdleTick expires, but we will need to create new events to do that. // Instead, we only check-and-unmark the inService bit before we really // want to know the bank status. - for (unsigned i = 0; i < cache->bank.size(); ++i) - if (cache->bank[i]->serviceDone()) - cache->bank[i]->clearInService(); + if (cache->enableBankModel) + for (unsigned i = 0; i < cache->bank.size(); ++i) + if (cache->bank[i]->serviceDone()) + cache->bank[i]->clearInService(); cache->recvTimingResp(pkt); return true; diff -r f858281a4060 -r 1aa1ea2c0c9b src/mem/cache/base.cc --- a/src/mem/cache/base.cc Tue Apr 16 17:41:55 2013 -0700 +++ b/src/mem/cache/base.cc Tue Apr 16 18:01:53 2013 -0700 @@ -73,6 +73,7 @@ hitLatency(p->hit_latency), writeLatency(p->write_latency), responseLatency(p->response_latency), + enableBankModel(p->enable_bank_model), numBanks(p->num_banks), bankIntlvHighBit(p->bank_intlv_high_bit), numTarget(p->tgts_per_mshr), diff -r f858281a4060 -r 1aa1ea2c0c9b src/mem/cache/BaseCache.py --- a/src/mem/cache/BaseCache.py Tue Apr 16 17:41:55 2013 -0700 +++ b/src/mem/cache/BaseCache.py Tue Apr 16 18:01:53 2013 -0700 @@ -53,6 +53,8 @@ write_latency = Param.Cycles("The write latency for this cache") response_latency = Param.Cycles( "Additional cache latency for the return path to core on a miss") + enable_bank_model = Param.Bool(False, + "knob to control if the bank model is used") num_banks = Param.Int(2, "Number of cache data array banks") bank_intlv_high_bit = Param.Int(6, "Cache data array bank interleave highest bit") diff -r f858281a4060 -r 1aa1ea2c0c9b src/mem/cache/base.hh --- a/src/mem/cache/base.hh Tue Apr 16 17:41:55 2013 -0700 +++ b/src/mem/cache/base.hh Tue Apr 16 18:01:53 2013 -0700 @@ -305,6 +305,11 @@ const Cycles responseLatency; /** + * The knob to turn on/off cache data array bank model + */ + const bool enableBankModel; + + /** * The number of cache data array banks. */ const unsigned numBanks; diff -r f858281a4060 -r 1aa1ea2c0c9b configs/common/Options.py --- a/configs/common/Options.py Tue Apr 16 17:41:55 2013 -0700 +++ b/configs/common/Options.py Tue Apr 16 18:01:53 2013 -0700 @@ -74,6 +74,12 @@ help="L2 write latency.") parser.add_option("--l3_write_lat", type="int", default="40", help="L3 write latency.") + parser.add_option("--l1-enable-bank", action="store_true", + help="Enable L1 bank model") + parser.add_option("--l2-enable-bank", action="store_true", + help="Enable L2 bank model") + parser.add_option("--l3-enable-bank", action="store_true", + help="Enable L3 bank model") parser.add_option("--l1_num_banks", type="int", default="2", help="L1 bank count.") parser.add_option("--l2_num_banks", type="int", default="2", diff -r f858281a4060 -r 1aa1ea2c0c9b configs/common/CacheConfig.py --- a/configs/common/CacheConfig.py Tue Apr 16 17:41:55 2013 -0700 +++ b/configs/common/CacheConfig.py Tue Apr 16 18:01:53 2013 -0700 @@ -69,6 +69,7 @@ assoc=options.l2_assoc, hit_latency=options.l2_read_lat, write_latency=options.l2_write_lat, + enable_bank_model=options.l2_enable_bank, num_banks=options.l2_num_banks, bank_intlv_high_bit = options.l2_intlv_bit, block_size=options.cacheline_size) @@ -83,6 +84,7 @@ assoc=options.l1i_assoc, hit_latency=options.l1_read_lat, write_latency=options.l1_write_lat, + enable_bank_model=options.l1_enable_bank, num_banks=options.l1_num_banks, bank_intlv_high_bit = options.l1_intlv_bit, block_size=options.cacheline_size) @@ -90,6 +92,7 @@ assoc=options.l1d_assoc, hit_latency=options.l1_read_lat, write_latency=options.l1_write_lat, + enable_bank_model=options.l1_enable_bank, num_banks=options.l1_num_banks, bank_intlv_high_bit = options.l1_intlv_bit, block_size=options.cacheline_size)