diff -r 112382ddf96d -r 01ac53525db4 tests/SConscript
--- a/tests/SConscript	Wed Apr 17 16:09:37 2013 -0500
+++ b/tests/SConscript	Thu Apr 18 11:51:49 2013 -0500
@@ -323,7 +323,8 @@
 if env['TARGET_ISA'] == 'x86':
     configs += ['pc-simple-atomic',
                 'pc-simple-timing',
-                'pc-o3-timing']
+                'pc-o3-timing',
+                'pc-switcheroo-full']
 
 configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest',
             'simple-atomic-mp', 'simple-timing-mp', 'o3-timing-mp',
diff -r 112382ddf96d -r 01ac53525db4 tests/configs/base_config.py
--- a/tests/configs/base_config.py	Wed Apr 17 16:09:37 2013 -0500
+++ b/tests/configs/base_config.py	Thu Apr 18 11:51:49 2013 -0500
@@ -102,14 +102,18 @@
         system.l2c.mem_side = system.membus.slave
         return system.toL2Bus
 
-    def init_cpu(self, system, cpu):
+    def init_cpu(self, system, cpu, sha_bus):
         """Initialize a CPU.
 
         Arguments:
           system -- System to work on.
           cpu -- CPU to initialize.
         """
-        cpu.createInterruptController()
+        if not cpu.switched_out:
+            self.create_caches_private(cpu)
+            cpu.createInterruptController()
+            cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
+                                system.membus)
 
     def init_system(self, system):
         """Initialize a system.
@@ -118,16 +122,10 @@
           system -- System to initialize.
         """
         system.cpu = self.create_cpus()
+        sha_bus = self.create_caches_shared(system)
 
-        sha_bus = self.create_caches_shared(system)
         for cpu in system.cpu:
-            if not cpu.switched_out:
-                self.create_caches_private(cpu)
-                self.init_cpu(system, cpu)
-                cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
-                                    system.membus)
-            else:
-                self.init_cpu(system, cpu)
+            self.init_cpu(system, cpu, sha_bus)
 
     @abstractmethod
     def create_system(self):
diff -r 112382ddf96d -r 01ac53525db4 tests/configs/pc-switcheroo-full.py
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/configs/pc-switcheroo-full.py	Thu Apr 18 11:51:49 2013 -0500
@@ -0,0 +1,50 @@
+# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2013 Mark D. Hill and David A. Wood
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+#          Nilay Vaish
+
+from m5.objects import *
+from x86_generic import *
+import switcheroo
+
+root = LinuxX86FSSwitcheroo(
+    cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
+    ).create_root()
+
+# Setup a custom test method that uses the switcheroo tester that
+# switches between CPU models.
+run_test = switcheroo.run_test
diff -r 112382ddf96d -r 01ac53525db4 tests/configs/x86_generic.py
--- a/tests/configs/x86_generic.py	Wed Apr 17 16:09:37 2013 -0500
+++ b/tests/configs/x86_generic.py	Thu Apr 18 11:51:49 2013 -0500
@@ -106,3 +106,11 @@
                                       L2Cache(size='4MB', assoc=8),
                                       PageTableWalkerCache(),
                                       PageTableWalkerCache())
+
+
+class LinuxX86FSSwitcheroo(LinuxX86SystemBuilder, BaseFSSwitcheroo):
+    """Uniprocessor X86 system prepared for CPU switching"""
+
+    def __init__(self, **kwargs):
+        BaseFSSwitcheroo.__init__(self, **kwargs)
+        LinuxX86SystemBuilder.__init__(self)