diff -r ff812ed6879f -r 4eadb37db02e configs/ruby/MOESI_CMP_directory.py --- a/configs/ruby/MOESI_CMP_directory.py Sun May 12 12:43:28 2013 -0500 +++ b/configs/ruby/MOESI_CMP_directory.py Mon May 13 11:24:51 2013 -0500 @@ -154,7 +154,8 @@ cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, - size = dir_size), + size = dir_size, + use_map = options.use_map), memBuffer = mem_cntrl, ruby_system = ruby_system) diff -r ff812ed6879f -r 4eadb37db02e configs/ruby/MOESI_CMP_token.py --- a/configs/ruby/MOESI_CMP_token.py Sun May 12 12:43:28 2013 -0500 +++ b/configs/ruby/MOESI_CMP_token.py Mon May 13 11:24:51 2013 -0500 @@ -175,7 +175,8 @@ cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, - size = dir_size), + use_map = options.use_map, + size = dir_size), memBuffer = mem_cntrl, l2_select_num_bits = l2_bits, ruby_system = ruby_system) diff -r ff812ed6879f -r 4eadb37db02e src/mem/protocol/MESI_CMP_directory-L1cache.sm --- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm Sun May 12 12:43:28 2013 -0500 +++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm Mon May 13 11:24:51 2013 -0500 @@ -874,15 +874,27 @@ wakeUpBuffers(address); } - action(uu_profileInstMiss, "\ui", desc="Profile the demand miss") { + action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") { peek(mandatoryQueue_in, RubyRequest) { - L1IcacheMemory.profileMiss(in_msg); + ++L1IcacheMemory.demand_misses; } } - action(uu_profileDataMiss, "\ud", desc="Profile the demand miss") { + action(uu_profileInstHit, "\uih", desc="Profile the demand hit") { peek(mandatoryQueue_in, RubyRequest) { - L1DcacheMemory.profileMiss(in_msg); + ++L1IcacheMemory.demand_hits; + } + } + + action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") { + peek(mandatoryQueue_in, RubyRequest) { + ++L1DcacheMemory.demand_misses; + } + } + + action(uu_profileDataHit, "\udh", desc="Profile the demand hit") { + peek(mandatoryQueue_in, RubyRequest) { + ++L1DcacheMemory.demand_hits; } } @@ -1024,8 +1036,15 @@ } // Transitions from Shared - transition(S, {Load,Ifetch}) { + transition({S,E,M}, Load) { h_load_hit; + uu_profileDataHit; + k_popMandatoryQueue; + } + + transition({S,E,M}, Ifetch) { + h_load_hit; + uu_profileInstHit; k_popMandatoryQueue; } @@ -1049,13 +1068,9 @@ // Transitions from Exclusive - transition(E, {Load, Ifetch}) { - h_load_hit; - k_popMandatoryQueue; - } - - transition(E, Store, M) { + transition({E,M}, Store, M) { hh_store_hit; + uu_profileDataHit; k_popMandatoryQueue; } @@ -1087,15 +1102,6 @@ } // Transitions from Modified - transition(M, {Load, Ifetch}) { - h_load_hit; - k_popMandatoryQueue; - } - - transition(M, Store) { - hh_store_hit; - k_popMandatoryQueue; - } transition(M, L1_Replacement, M_I) { forward_eviction_to_cpu; diff -r ff812ed6879f -r 4eadb37db02e src/mem/protocol/MESI_CMP_directory-L2cache.sm --- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm Sun May 12 12:43:28 2013 -0500 +++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm Mon May 13 11:24:51 2013 -0500 @@ -720,25 +720,15 @@ } } - GenericRequestType convertToGenericType(CoherenceRequestType type) { - if(type == CoherenceRequestType:GETS) { - return GenericRequestType:GETS; - } else if(type == CoherenceRequestType:GETX) { - return GenericRequestType:GETX; - } else if(type == CoherenceRequestType:GET_INSTR) { - return GenericRequestType:GET_INSTR; - } else if(type == CoherenceRequestType:UPGRADE) { - return GenericRequestType:UPGRADE; - } else { - DPRINTF(RubySlicc, "%s\n", type); - error("Invalid CoherenceRequestType\n"); + action(uu_profileMiss, "\um", desc="Profile the demand miss") { + peek(L1RequestIntraChipL2Network_in, RequestMsg) { + ++L2cacheMemory.demand_misses; } } - action(uu_profileMiss, "\u", desc="Profile the demand miss") { + action(uu_profileHit, "\uh", desc="Profile the demand hit") { peek(L1RequestIntraChipL2Network_in, RequestMsg) { - L2cacheMemory.profileGenericRequest(convertToGenericType(in_msg.Type), - in_msg.AccessMode, in_msg.Prefetch); + ++L2cacheMemory.demand_hits; } } @@ -922,6 +912,7 @@ ds_sendSharedDataToRequestor; nn_addSharer; set_setMRU; + uu_profileHit; jj_popL1RequestQueue; } @@ -931,6 +922,7 @@ // fw_sendFwdInvToSharers; fwm_sendFwdInvToSharersMinusRequestor; set_setMRU; + uu_profileHit; jj_popL1RequestQueue; } @@ -938,6 +930,7 @@ fwm_sendFwdInvToSharersMinusRequestor; ts_sendInvAckToUpgrader; set_setMRU; + uu_profileHit; jj_popL1RequestQueue; } @@ -957,6 +950,7 @@ transition(M, L1_GETX, MT_MB) { d_sendDataToRequestor; set_setMRU; + uu_profileHit; jj_popL1RequestQueue; } @@ -964,12 +958,14 @@ d_sendDataToRequestor; nn_addSharer; set_setMRU; + uu_profileHit; jj_popL1RequestQueue; } transition(M, L1_GETS, MT_MB) { dd_sendExclusiveDataToRequestor; set_setMRU; + uu_profileHit; jj_popL1RequestQueue; } diff -r ff812ed6879f -r 4eadb37db02e src/mem/protocol/MI_example-cache.sm --- a/src/mem/protocol/MI_example-cache.sm Sun May 12 12:43:28 2013 -0500 +++ b/src/mem/protocol/MI_example-cache.sm Mon May 13 11:24:51 2013 -0500 @@ -335,9 +335,15 @@ profileMsgDelay(2, forwardRequestNetwork_in.dequeue_getDelayCycles()); } - action(p_profileMiss, "p", desc="Profile cache miss") { + action(p_profileMiss, "pi", desc="Profile cache miss") { peek(mandatoryQueue_in, RubyRequest) { - cacheMemory.profileMiss(in_msg); + ++cacheMemory.demand_misses; + } + } + + action(p_profileHit, "ph", desc="Profile cache miss") { + peek(mandatoryQueue_in, RubyRequest) { + ++cacheMemory.demand_hits; } } @@ -427,11 +433,13 @@ transition(M, Store) { s_store_hit; + p_profileHit; m_popMandatoryQueue; } transition(M, {Load, Ifetch}) { r_load_hit; + p_profileHit; m_popMandatoryQueue; } diff -r ff812ed6879f -r 4eadb37db02e src/mem/protocol/MOESI_CMP_directory-L1cache.sm --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Sun May 12 12:43:28 2013 -0500 +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Mon May 13 11:24:51 2013 -0500 @@ -1,4 +1,3 @@ - /* * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood * All rights reserved. @@ -859,9 +858,27 @@ } } - action(uu_profileMiss, "\u", desc="Profile the demand miss") { + action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") { peek(mandatoryQueue_in, RubyRequest) { - // profile_miss(in_msg); + ++L1Icache.demand_misses; + } + } + + action(uu_profileInstHit, "\uih", desc="Profile the demand hit") { + peek(mandatoryQueue_in, RubyRequest) { + ++L1Icache.demand_hits; + } + } + + action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") { + peek(mandatoryQueue_in, RubyRequest) { + ++L1Dcache.demand_misses; + } + } + + action(uu_profileDataHit, "\udh", desc="Profile the demand hit") { + peek(mandatoryQueue_in, RubyRequest) { + ++L1Dcache.demand_hits; } } @@ -899,7 +916,7 @@ ii_allocateL1DCacheBlock; i_allocateTBE; a_issueGETS; - // uu_profileMiss; + uu_profileDataMiss; k_popMandatoryQueue; } @@ -907,7 +924,7 @@ jj_allocateL1ICacheBlock; i_allocateTBE; a_issueGETS; - // uu_profileMiss; + uu_profileInstMiss; k_popMandatoryQueue; } @@ -915,7 +932,7 @@ ii_allocateL1DCacheBlock; i_allocateTBE; b_issueGETX; - // uu_profileMiss; + uu_profileDataMiss; k_popMandatoryQueue; } @@ -928,16 +945,23 @@ l_popForwardQueue; } - // Transitions from Shared - transition({S, SM}, {Load, Ifetch}) { + transition({S, SM, O, OM, MM, MM_W, M, M_W}, Load) { h_load_hit; + uu_profileDataHit; k_popMandatoryQueue; } + transition({S, SM, O, OM, MM, MM_W, M, M_W}, Ifetch) { + h_load_hit; + uu_profileInstHit; + k_popMandatoryQueue; + } + + // Transitions from Shared transition(S, Store, SM) { i_allocateTBE; b_issueGETX; - // uu_profileMiss; + uu_profileDataMiss; k_popMandatoryQueue; } @@ -966,15 +990,10 @@ } // Transitions from Owned - transition({O, OM}, {Load, Ifetch}) { - h_load_hit; - k_popMandatoryQueue; - } - transition(O, Store, OM) { i_allocateTBE; b_issueGETX; - // uu_profileMiss; + uu_profileDataMiss; k_popMandatoryQueue; } @@ -1003,13 +1022,9 @@ } // Transitions from MM - transition({MM, MM_W}, {Load, Ifetch}) { - h_load_hit; - k_popMandatoryQueue; - } - transition({MM, MM_W}, Store) { hh_store_hit; + uu_profileDataHit; k_popMandatoryQueue; } @@ -1039,18 +1054,15 @@ } // Transitions from M - transition({M, M_W}, {Load, Ifetch}) { - h_load_hit; - k_popMandatoryQueue; - } - transition(M, Store, MM) { hh_store_hit; + uu_profileDataHit; k_popMandatoryQueue; } transition(M_W, Store, MM_W) { hh_store_hit; + uu_profileDataHit; k_popMandatoryQueue; } diff -r ff812ed6879f -r 4eadb37db02e src/mem/protocol/MOESI_CMP_directory-L2cache.sm --- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Sun May 12 12:43:28 2013 -0500 +++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Mon May 13 11:24:51 2013 -0500 @@ -1475,10 +1475,15 @@ } } - action(uu_profileMiss, "\u", desc="Profile the demand miss") { + action(uu_profileMiss, "\um", desc="Profile the demand miss") { peek(L1requestNetwork_in, RequestMsg) { - // AccessModeType not implemented - // profile_L2Cache_miss(convertToGenericType(in_msg.Type), in_msg.AccessMode, MessageSizeTypeToInt(in_msg.MessageSize), in_msg.Prefetch, machineIDToNodeID(in_msg.Requestor)); + ++L2cache.demand_misses; + } + } + + action(uu_profileHit, "\uh", desc="Profile the demand hit") { + peek(L1requestNetwork_in, RequestMsg) { + ++L2cache.demand_hits; } } @@ -1909,7 +1914,7 @@ y_copyCacheStateToDir; r_setMRU; rr_deallocateL2CacheBlock; - uu_profileMiss; + uu_profileHit; o_popL1RequestQueue; } @@ -1922,6 +1927,7 @@ transition(OLSX, L1_GETS, OLSXS) { d_sendDataToL1GETS; r_setMRU; + uu_profileHit; o_popL1RequestQueue; } @@ -2311,6 +2317,7 @@ transition(SLS, L1_GETS, SLSS ) { d_sendDataToL1GETS; r_setMRU; + uu_profileHit; o_popL1RequestQueue; } @@ -2333,6 +2340,7 @@ transition(OLS, L1_GETS, OLSS) { d_sendDataToL1GETS; r_setMRU; + uu_profileHit; o_popL1RequestQueue; } @@ -2361,10 +2369,11 @@ i_allocateTBE; // should count 0 of course h_countLocalSharersExceptRequestor; - d_sendDataToL1GETX + d_sendDataToL1GETX; y_copyCacheStateToDir; rr_deallocateL2CacheBlock; s_deallocateTBE; + uu_profileHit; o_popL1RequestQueue; } @@ -2380,12 +2389,14 @@ d_sendDataToL1GETX; r_setMRU; s_deallocateTBE; + uu_profileHit; o_popL1RequestQueue; } transition(S, L1_GETS, SS) { d_sendDataToL1GETS; r_setMRU; + uu_profileHit; o_popL1RequestQueue; } @@ -2397,6 +2408,7 @@ transition(O, L1_GETS, OO) { d_sendDataToL1GETS; r_setMRU; + uu_profileHit; o_popL1RequestQueue; } diff -r ff812ed6879f -r 4eadb37db02e src/mem/protocol/MOESI_CMP_token-L1cache.sm --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sun May 12 12:43:28 2013 -0500 +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Mon May 13 11:24:51 2013 -0500 @@ -1,6 +1,5 @@ - /* - * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood + * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -665,7 +664,8 @@ Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); if (is_valid(L1Icache_entry)) { - // The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion + // The tag matches for the L1, so the L1 fetches the line. + // We know it can't be in the L2 due to exclusion. trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, L1Icache_entry, tbe); } else { @@ -695,7 +695,8 @@ Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); if (is_valid(L1Dcache_entry)) { - // The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion + // The tag matches for the L1, so the L1 fetches the line. + // We know it can't be in the L2 due to exclusion. trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, L1Dcache_entry, tbe); } else { @@ -1534,13 +1535,27 @@ } } - action(uu_profileMiss, "\u", desc="Profile the demand miss") { + action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") { peek(mandatoryQueue_in, RubyRequest) { - if (L1DcacheMemory.isTagPresent(address)) { - L1DcacheMemory.profileMiss(in_msg); - } else { - L1IcacheMemory.profileMiss(in_msg); - } + ++L1IcacheMemory.demand_misses; + } + } + + action(uu_profileInstHit, "\uih", desc="Profile the demand hit") { + peek(mandatoryQueue_in, RubyRequest) { + ++L1IcacheMemory.demand_hits; + } + } + + action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") { + peek(mandatoryQueue_in, RubyRequest) { + ++L1DcacheMemory.demand_misses; + } + } + + action(uu_profileDataHit, "\udh", desc="Profile the demand hit") { + peek(mandatoryQueue_in, RubyRequest) { + ++L1DcacheMemory.demand_hits; } } @@ -1594,7 +1609,7 @@ ii_allocateL1DCacheBlock; i_allocateTBE; a_issueReadRequest; - uu_profileMiss; + uu_profileDataMiss; k_popMandatoryQueue; } @@ -1602,7 +1617,7 @@ pp_allocateL1ICacheBlock; i_allocateTBE; a_issueReadRequest; - uu_profileMiss; + uu_profileInstMiss; k_popMandatoryQueue; } @@ -1610,7 +1625,7 @@ ii_allocateL1DCacheBlock; i_allocateTBE; b_issueWriteRequest; - uu_profileMiss; + uu_profileDataMiss; k_popMandatoryQueue; } @@ -1631,21 +1646,21 @@ transition(I, Load, IS) { i_allocateTBE; a_issueReadRequest; - uu_profileMiss; + uu_profileDataMiss; k_popMandatoryQueue; } transition(I, Ifetch, IS) { i_allocateTBE; a_issueReadRequest; - uu_profileMiss; + uu_profileInstMiss; k_popMandatoryQueue; } transition(I, {Store, Atomic}, IM) { i_allocateTBE; b_issueWriteRequest; - uu_profileMiss; + uu_profileDataMiss; k_popMandatoryQueue; } @@ -1698,15 +1713,22 @@ } // Transitions from Shared - transition({S, SM, S_L, SM_L}, {Load, Ifetch}) { + transition({S, SM, S_L, SM_L}, Load) { h_load_hit; + uu_profileDataHit; + k_popMandatoryQueue; + } + + transition({S, SM, S_L, SM_L}, Ifetch) { + h_load_hit; + uu_profileInstHit; k_popMandatoryQueue; } transition(S, {Store, Atomic}, SM) { i_allocateTBE; b_issueWriteRequest; - uu_profileMiss; + uu_profileDataMiss; k_popMandatoryQueue; } @@ -1779,15 +1801,22 @@ } // Transitions from Owned - transition({O, OM}, {Load, Ifetch}) { + transition({O, OM}, Ifetch) { h_load_hit; + uu_profileInstHit; + k_popMandatoryQueue; + } + + transition({O, OM}, Load) { + h_load_hit; + uu_profileDataHit; k_popMandatoryQueue; } transition(O, {Store, Atomic}, OM) { i_allocateTBE; b_issueWriteRequest; - uu_profileMiss; + uu_profileDataMiss; k_popMandatoryQueue; } @@ -1862,23 +1891,33 @@ } // Transitions from Modified - transition({MM, MM_W}, {Load, Ifetch}) { + transition({MM, MM_W}, Ifetch) { h_load_hit; + uu_profileInstHit; + k_popMandatoryQueue; + } + + transition({MM, MM_W}, Load) { + h_load_hit; + uu_profileDataHit; k_popMandatoryQueue; } transition({MM_W}, {Store, Atomic}) { hh_store_hit; + uu_profileDataHit; k_popMandatoryQueue; } transition(MM, Store) { hh_store_hit; + uu_profileDataHit; k_popMandatoryQueue; } transition(MM, Atomic, M) { hh_store_hit; + uu_profileDataHit; k_popMandatoryQueue; } @@ -1927,28 +1966,39 @@ } // Transitions from Dirty Exclusive - transition({M, M_W}, {Load, Ifetch}) { + transition({M, M_W}, Ifetch) { h_load_hit; + uu_profileInstHit; + k_popMandatoryQueue; + } + + transition({M, M_W}, Load) { + h_load_hit; + uu_profileDataHit; k_popMandatoryQueue; } transition(M, Store, MM) { hh_store_hit; + uu_profileDataHit; k_popMandatoryQueue; } transition(M, Atomic) { hh_store_hit; + uu_profileDataHit; k_popMandatoryQueue; } transition(M_W, Store, MM_W) { hh_store_hit; + uu_profileDataHit; k_popMandatoryQueue; } transition(M_W, Atomic) { hh_store_hit; + uu_profileDataHit; k_popMandatoryQueue; } @@ -2243,7 +2293,7 @@ ii_allocateL1DCacheBlock; i_allocateTBE; a_issueReadRequest; - uu_profileMiss; + uu_profileDataMiss; k_popMandatoryQueue; } @@ -2251,7 +2301,7 @@ pp_allocateL1ICacheBlock; i_allocateTBE; a_issueReadRequest; - uu_profileMiss; + uu_profileInstMiss; k_popMandatoryQueue; } @@ -2259,7 +2309,7 @@ ii_allocateL1DCacheBlock; i_allocateTBE; b_issueWriteRequest; - uu_profileMiss; + uu_profileDataMiss; k_popMandatoryQueue; } @@ -2269,7 +2319,7 @@ transition(S_L, {Store, Atomic}, SM_L) { i_allocateTBE; b_issueWriteRequest; - uu_profileMiss; + uu_profileDataMiss; k_popMandatoryQueue; } diff -r ff812ed6879f -r 4eadb37db02e src/mem/protocol/MOESI_CMP_token-L2cache.sm --- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm Sun May 12 12:43:28 2013 -0500 +++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm Mon May 13 11:24:51 2013 -0500 @@ -296,17 +296,6 @@ } } - GenericRequestType convertToGenericType(CoherenceRequestType type) { - if(type == CoherenceRequestType:GETS) { - return GenericRequestType:GETS; - } else if(type == CoherenceRequestType:GETX) { - return GenericRequestType:GETX; - } else { - DPRINTF(RubySlicc, "%s\n", type); - error("invalid CoherenceRequestType"); - } - } - // ** OUT_PORTS ** out_port(globalRequestNetwork_out, RequestMsg, GlobalRequestFromL2Cache); out_port(localRequestNetwork_out, RequestMsg, L1RequestFromL2Cache); @@ -976,14 +965,17 @@ unset_cache_entry(); } - action(uu_profileMiss, "\u", desc="Profile the demand miss") { + action(uu_profileMiss, "\um", desc="Profile the demand miss") { peek(L1requestNetwork_in, RequestMsg) { - L2cacheMemory.profileGenericRequest(convertToGenericType(in_msg.Type), - in_msg.AccessMode, - in_msg.Prefetch); + ++L2cacheMemory.demand_misses; } } + action(uu_profileHit, "\uh", desc="Profile the demand hit") { + peek(L1requestNetwork_in, RequestMsg) { + ++L2cacheMemory.demand_hits; + } + } action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the incoming data and the data in the cache match") { peek(responseNetwork_in, ResponseMsg) { @@ -1257,6 +1249,7 @@ k_dataFromL2CacheToL1Requestor; r_markNewSharer; r_setMRU; + uu_profileHit; o_popL1RequestQueue; } @@ -1265,6 +1258,7 @@ k_dataFromL2CacheToL1Requestor; r_markNewSharer; r_setMRU; + uu_profileHit; o_popL1RequestQueue; } @@ -1351,6 +1345,7 @@ k_dataFromL2CacheToL1Requestor; r_markNewSharer; r_setMRU; + uu_profileHit; o_popL1RequestQueue; } @@ -1358,6 +1353,7 @@ k_dataOwnerFromL2CacheToL1Requestor; r_markNewSharer; r_setMRU; + uu_profileHit; o_popL1RequestQueue; } @@ -1394,6 +1390,7 @@ k_dataFromL2CacheToL1Requestor; r_markNewSharer; r_setMRU; + uu_profileHit; o_popL1RequestQueue; } @@ -1401,6 +1398,7 @@ k_dataAndAllTokensFromL2CacheToL1Requestor; r_markNewSharer; r_setMRU; + uu_profileHit; o_popL1RequestQueue; } @@ -1471,6 +1469,7 @@ k_dataFromL2CacheToL1Requestor; r_markNewSharer; r_setMRU; + uu_profileHit; o_popL1RequestQueue; } @@ -1478,6 +1477,7 @@ k_dataFromL2CacheToL1Requestor; r_markNewSharer; r_setMRU; + uu_profileHit; o_popL1RequestQueue; } diff -r ff812ed6879f -r 4eadb37db02e src/mem/protocol/MOESI_hammer-cache.sm --- a/src/mem/protocol/MOESI_hammer-cache.sm Sun May 12 12:43:28 2013 -0500 +++ b/src/mem/protocol/MOESI_hammer-cache.sm Mon May 13 11:24:51 2013 -0500 @@ -1231,16 +1231,39 @@ } } - action(uu_profileMiss, "\u", desc="Profile the demand miss") { + action(uu_profileL1DataMiss, "\udm", desc="Profile the demand miss") { peek(mandatoryQueue_in, RubyRequest) { - if (L1IcacheMemory.isTagPresent(address)) { - L1IcacheMemory.profileMiss(in_msg); - } else if (L1DcacheMemory.isTagPresent(address)) { - L1DcacheMemory.profileMiss(in_msg); - } - if (L2cacheMemory.isTagPresent(address) == false) { - L2cacheMemory.profileMiss(in_msg); - } + ++L1DcacheMemory.demand_misses; + } + } + + action(uu_profileL1DataHit, "\udh", desc="Profile the demand hits") { + peek(mandatoryQueue_in, RubyRequest) { + ++L1DcacheMemory.demand_hits; + } + } + + action(uu_profileL1InstMiss, "\uim", desc="Profile the demand miss") { + peek(mandatoryQueue_in, RubyRequest) { + ++L1IcacheMemory.demand_misses; + } + } + + action(uu_profileL1InstHit, "\uih", desc="Profile the demand hits") { + peek(mandatoryQueue_in, RubyRequest) { + ++L1IcacheMemory.demand_hits; + } + } + + action(uu_profileL2Miss, "\um", desc="Profile the demand miss") { + peek(mandatoryQueue_in, RubyRequest) { + ++L2cacheMemory.demand_misses; + } + } + + action(uu_profileL2Hit, "\uh", desc="Profile the demand hits ") { + peek(mandatoryQueue_in, RubyRequest) { + ++L2cacheMemory.demand_hits; } } @@ -1317,7 +1340,7 @@ ii_allocateL1DCacheBlock; nb_copyFromTBEToL1; // Not really needed for state I s_deallocateTBE; - uu_profileMiss; + uu_profileL1DataMiss; zz_stallAndWaitMandatoryQueue; ll_L2toL1Transfer; } @@ -1328,7 +1351,7 @@ ii_allocateL1DCacheBlock; nb_copyFromTBEToL1; s_deallocateTBE; - uu_profileMiss; + uu_profileL1DataMiss; zz_stallAndWaitMandatoryQueue; ll_L2toL1Transfer; } @@ -1339,7 +1362,7 @@ ii_allocateL1DCacheBlock; nb_copyFromTBEToL1; s_deallocateTBE; - uu_profileMiss; + uu_profileL1DataMiss; zz_stallAndWaitMandatoryQueue; ll_L2toL1Transfer; } @@ -1350,7 +1373,7 @@ ii_allocateL1DCacheBlock; nb_copyFromTBEToL1; s_deallocateTBE; - uu_profileMiss; + uu_profileL1DataMiss; zz_stallAndWaitMandatoryQueue; ll_L2toL1Transfer; } @@ -1361,7 +1384,7 @@ ii_allocateL1DCacheBlock; nb_copyFromTBEToL1; s_deallocateTBE; - uu_profileMiss; + uu_profileL1DataMiss; zz_stallAndWaitMandatoryQueue; ll_L2toL1Transfer; } @@ -1372,7 +1395,7 @@ jj_allocateL1ICacheBlock; nb_copyFromTBEToL1; s_deallocateTBE; - uu_profileMiss; + uu_profileL1InstMiss; zz_stallAndWaitMandatoryQueue; ll_L2toL1Transfer; } @@ -1383,7 +1406,7 @@ jj_allocateL1ICacheBlock; nb_copyFromTBEToL1; s_deallocateTBE; - uu_profileMiss; + uu_profileL1InstMiss; zz_stallAndWaitMandatoryQueue; ll_L2toL1Transfer; } @@ -1394,7 +1417,7 @@ jj_allocateL1ICacheBlock; nb_copyFromTBEToL1; s_deallocateTBE; - uu_profileMiss; + uu_profileL1InstMiss; zz_stallAndWaitMandatoryQueue; ll_L2toL1Transfer; } @@ -1405,7 +1428,7 @@ jj_allocateL1ICacheBlock; nb_copyFromTBEToL1; s_deallocateTBE; - uu_profileMiss; + uu_profileL1InstMiss; zz_stallAndWaitMandatoryQueue; ll_L2toL1Transfer; } @@ -1416,7 +1439,7 @@ jj_allocateL1ICacheBlock; nb_copyFromTBEToL1; s_deallocateTBE; - uu_profileMiss; + uu_profileL1InstMiss; zz_stallAndWaitMandatoryQueue; ll_L2toL1Transfer; } @@ -1447,34 +1470,60 @@ } // Transitions from Idle - transition({I, IR}, Load, IS) { + transition(I, Load, IS) { ii_allocateL1DCacheBlock; i_allocateTBE; a_issueGETS; - uu_profileMiss; + uu_profileL1DataMiss; + uu_profileL2Miss; k_popMandatoryQueue; } - transition({I, IR}, Ifetch, IS) { + transition(IR, Load, IS) { + ii_allocateL1DCacheBlock; + i_allocateTBE; + a_issueGETS; + uu_profileL2Miss; + k_popMandatoryQueue; + } + + transition(I, Ifetch, IS) { jj_allocateL1ICacheBlock; i_allocateTBE; a_issueGETS; - uu_profileMiss; + uu_profileL1InstMiss; + uu_profileL2Miss; k_popMandatoryQueue; } - transition({I, IR}, Store, IM) { + transition(IR, Ifetch, IS) { + jj_allocateL1ICacheBlock; + i_allocateTBE; + a_issueGETS; + uu_profileL2Miss; + k_popMandatoryQueue; + } + + transition(I, Store, IM) { ii_allocateL1DCacheBlock; i_allocateTBE; b_issueGETX; - uu_profileMiss; + uu_profileL1DataMiss; + uu_profileL2Miss; + k_popMandatoryQueue; + } + + transition(IR, Store, IM) { + ii_allocateL1DCacheBlock; + i_allocateTBE; + b_issueGETX; + uu_profileL2Miss; k_popMandatoryQueue; } transition({I, IR}, Flush_line, IM_F) { it_allocateTBE; bf_issueGETF; - uu_profileMiss; k_popMandatoryQueue; } @@ -1489,28 +1538,43 @@ } // Transitions from Shared - transition({S, SM, ISM}, {Load, Ifetch}) { + transition({S, SM, ISM}, Load) { h_load_hit; + uu_profileL1DataHit; + k_popMandatoryQueue; + } + + transition({S, SM, ISM}, Ifetch) { + h_load_hit; + uu_profileL1InstHit; k_popMandatoryQueue; } transition(SR, {Load, Ifetch}, S) { h_load_hit; + uu_profileL2Hit; k_popMandatoryQueue; ka_wakeUpAllDependents; } - transition({S, SR}, Store, SM) { + transition(S, Store, SM) { i_allocateTBE; b_issueGETX; - uu_profileMiss; + uu_profileL1DataMiss; + uu_profileL2Miss; + k_popMandatoryQueue; + } + + transition(SR, Store, SM) { + i_allocateTBE; + b_issueGETX; + uu_profileL2Miss; k_popMandatoryQueue; } transition({S, SR}, Flush_line, SM_F) { i_allocateTBE; bf_issueGETF; - uu_profileMiss; forward_eviction_to_cpu; gg_deallocateL1CacheBlock; k_popMandatoryQueue; @@ -1534,29 +1598,46 @@ } // Transitions from Owned - transition({O, OM, SS, MM_W, M_W}, {Load, Ifetch}) { + transition({O, OM, SS, MM_W, M_W}, {Load}) { h_load_hit; + uu_profileL1DataHit; + k_popMandatoryQueue; + } + + transition({O, OM, SS, MM_W, M_W}, {Ifetch}) { + h_load_hit; + uu_profileL1InstHit; k_popMandatoryQueue; } transition(OR, {Load, Ifetch}, O) { h_load_hit; + uu_profileL2Hit; k_popMandatoryQueue; ka_wakeUpAllDependents; } - transition({O, OR}, Store, OM) { + transition(O, Store, OM) { i_allocateTBE; b_issueGETX; p_decrementNumberOfMessagesByOne; - uu_profileMiss; + uu_profileL1DataMiss; + uu_profileL2Miss; k_popMandatoryQueue; } + + transition(OR, Store, OM) { + i_allocateTBE; + b_issueGETX; + p_decrementNumberOfMessagesByOne; + uu_profileL2Miss; + k_popMandatoryQueue; + } + transition({O, OR}, Flush_line, OM_F) { i_allocateTBE; bf_issueGETF; p_decrementNumberOfMessagesByOne; - uu_profileMiss; forward_eviction_to_cpu; gg_deallocateL1CacheBlock; k_popMandatoryQueue; @@ -1587,24 +1668,34 @@ } // Transitions from Modified - transition({MM, M}, {Load, Ifetch}) { + transition({MM, M}, {Ifetch}) { h_load_hit; + uu_profileL1InstHit; + k_popMandatoryQueue; + } + + transition({MM, M}, {Load}) { + h_load_hit; + uu_profileL1DataHit; k_popMandatoryQueue; } transition(MM, Store) { hh_store_hit; + uu_profileL1DataHit; k_popMandatoryQueue; } transition(MMR, {Load, Ifetch}, MM) { h_load_hit; + uu_profileL2Hit; k_popMandatoryQueue; ka_wakeUpAllDependents; } transition(MMR, Store, MM) { hh_store_hit; + uu_profileL2Hit; k_popMandatoryQueue; ka_wakeUpAllDependents; } @@ -1662,17 +1753,20 @@ // Transitions from Dirty Exclusive transition(M, Store, MM) { hh_store_hit; + uu_profileL1DataHit; k_popMandatoryQueue; } transition(MR, {Load, Ifetch}, M) { h_load_hit; + uu_profileL2Hit; k_popMandatoryQueue; ka_wakeUpAllDependents; } transition(MR, Store, MM) { hh_store_hit; + uu_profileL2Hit; k_popMandatoryQueue; ka_wakeUpAllDependents; } @@ -1947,6 +2041,7 @@ transition(MM_W, Store) { hh_store_hit; + uu_profileL1DataHit; k_popMandatoryQueue; } @@ -1972,6 +2067,7 @@ transition(M_W, Store, MM_W) { hh_store_hit; + uu_profileL1DataHit; k_popMandatoryQueue; } diff -r ff812ed6879f -r 4eadb37db02e src/mem/protocol/RubySlicc_Exports.sm --- a/src/mem/protocol/RubySlicc_Exports.sm Sun May 12 12:43:28 2013 -0500 +++ b/src/mem/protocol/RubySlicc_Exports.sm Mon May 13 11:24:51 2013 -0500 @@ -144,39 +144,6 @@ NULL, desc="Invalid request type"; } -enumeration(GenericRequestType, desc="...", default="GenericRequestType_NULL") { - GETS, desc="gets request"; - GET_INSTR, desc="get instr request"; - GETX, desc="getx request"; - UPGRADE, desc="upgrade request"; - DOWNGRADE, desc="downgrade request"; - INV, desc="invalidate request"; - INV_S, desc="invalidate shared copy request"; - PUTS, desc="puts request"; - PUTO, desc="puto request"; - PUTX, desc="putx request"; - L2_PF, desc="L2 prefetch"; - LD, desc="Load"; - ST, desc="Store"; - ATOMIC, desc="Atomic Load/Store"; - IFETCH, desc="Instruction fetch"; - IO, desc="I/O"; - NACK, desc="Nack"; - REPLACEMENT, desc="Replacement"; - WB_ACK, desc="WriteBack ack"; - EXE_ACK, desc="Execlusive ack"; - COMMIT, desc="Commit version"; - LD_XACT, desc="Transactional Load"; - LDX_XACT, desc="Transactional Load-Intend-Modify"; - ST_XACT, desc="Transactional Store"; - BEGIN_XACT, desc="Begin Transaction"; - COMMIT_XACT, desc="Commit Transaction"; - ABORT_XACT, desc="Abort Transaction"; - DMA_READ, desc="DMA READ"; - DMA_WRITE, desc="DMA WRITE"; - NULL, desc="null request type"; -} - enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") { DataArrayRead, desc="Read access to the cache's data array"; DataArrayWrite, desc="Write access to the cache's data array"; diff -r ff812ed6879f -r 4eadb37db02e src/mem/protocol/RubySlicc_Types.sm --- a/src/mem/protocol/RubySlicc_Types.sm Sun May 12 12:43:28 2013 -0500 +++ b/src/mem/protocol/RubySlicc_Types.sm Mon May 13 11:24:51 2013 -0500 @@ -37,6 +37,7 @@ external_type(MessageBuffer, buffer="yes", inport="yes", outport="yes"); external_type(OutPort, primitive="yes"); +external_type(Scalar, primitive="yes"); structure(InPort, external = "yes", primitive="yes") { bool isReady(); @@ -148,15 +149,12 @@ void deallocate(Address); AbstractCacheEntry lookup(Address); bool isTagPresent(Address); - void profileMiss(RubyRequest); - - void profileGenericRequest(GenericRequestType, - RubyAccessMode, - PrefetchBit); - void setMRU(Address); void recordRequestType(CacheRequestType); bool checkResourceAvailable(CacheResourceType, Address); + + Scalar demand_misses; + Scalar demand_hits; } structure (WireBuffer, inport="yes", outport="yes", external = "yes") { diff -r ff812ed6879f -r 4eadb37db02e src/mem/ruby/profiler/CacheProfiler.hh --- a/src/mem/ruby/profiler/CacheProfiler.hh Sun May 12 12:43:28 2013 -0500 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,88 +0,0 @@ -/* - * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __MEM_RUBY_PROFILER_CACHEPROFILER_HH__ -#define __MEM_RUBY_PROFILER_CACHEPROFILER_HH__ - -#include -#include -#include - -#include "mem/protocol/GenericRequestType.hh" -#include "mem/protocol/PrefetchBit.hh" -#include "mem/protocol/RubyAccessMode.hh" -#include "mem/protocol/RubyRequestType.hh" -#include "mem/ruby/common/Global.hh" -#include "mem/ruby/common/Histogram.hh" - -class CacheProfiler -{ - public: - CacheProfiler(const std::string& description); - ~CacheProfiler(); - - void printStats(std::ostream& out) const; - void clearStats(); - - void addCacheStatSample(RubyRequestType requestType, - RubyAccessMode type, - PrefetchBit pfBit); - - void addGenericStatSample(GenericRequestType requestType, - RubyAccessMode type, - PrefetchBit pfBit); - - void print(std::ostream& out) const; - - private: - // Private copy constructor and assignment operator - CacheProfiler(const CacheProfiler& obj); - CacheProfiler& operator=(const CacheProfiler& obj); - void addStatSample(RubyAccessMode type, PrefetchBit pfBit); - - std::string m_description; - int64 m_misses; - int64 m_demand_misses; - int64 m_prefetches; - int64 m_sw_prefetches; - int64 m_hw_prefetches; - int64 m_accessModeTypeHistogram[RubyAccessMode_NUM]; - - std::vector m_cacheRequestType; - std::vector m_genericRequestType; -}; - -inline std::ostream& -operator<<(std::ostream& out, const CacheProfiler& obj) -{ - obj.print(out); - out << std::flush; - return out; -} - -#endif // __MEM_RUBY_PROFILER_CACHEPROFILER_HH__ diff -r ff812ed6879f -r 4eadb37db02e src/mem/ruby/profiler/CacheProfiler.cc --- a/src/mem/ruby/profiler/CacheProfiler.cc Sun May 12 12:43:28 2013 -0500 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,165 +0,0 @@ -/* - * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "mem/ruby/profiler/CacheProfiler.hh" -#include "mem/ruby/profiler/Profiler.hh" -#include "mem/ruby/system/System.hh" - -using namespace std; - -CacheProfiler::CacheProfiler(const string& description) - : m_cacheRequestType(int(RubyRequestType_NUM)), m_genericRequestType(int(GenericRequestType_NUM)) -{ - m_description = description; - - clearStats(); -} - -CacheProfiler::~CacheProfiler() -{ -} - -void -CacheProfiler::printStats(ostream& out) const -{ - out << "Cache Stats: " << m_description << endl; - string description = " " + m_description; - - out << description << "_total_misses: " << m_misses << endl; - out << description << "_total_demand_misses: " << m_demand_misses << endl; - out << description << "_total_prefetches: " << m_prefetches << endl; - out << description << "_total_sw_prefetches: " << m_sw_prefetches << endl; - out << description << "_total_hw_prefetches: " << m_hw_prefetches << endl; - out << endl; - - int requests = 0; - - for (int i = 0; i < int(RubyRequestType_NUM); i++) { - requests += m_cacheRequestType[i]; - } - - for (int i = 0; i < int(GenericRequestType_NUM); i++) { - requests += m_genericRequestType[i]; - } - - assert(m_misses == requests); - - if (requests > 0) { - for (int i = 0; i < int(RubyRequestType_NUM); i++) { - if (m_cacheRequestType[i] > 0) { - out << description << "_request_type_" - << RubyRequestType_to_string(RubyRequestType(i)) - << ": " - << 100.0 * (double)m_cacheRequestType[i] / - (double)requests - << "%" << endl; - } - } - - for (int i = 0; i < int(GenericRequestType_NUM); i++) { - if (m_genericRequestType[i] > 0) { - out << description << "_request_type_" - << GenericRequestType_to_string(GenericRequestType(i)) - << ": " - << 100.0 * (double)m_genericRequestType[i] / - (double)requests - << "%" << endl; - } - } - - out << endl; - - for (int i = 0; i < RubyAccessMode_NUM; i++){ - if (m_accessModeTypeHistogram[i] > 0) { - out << description << "_access_mode_type_" - << (RubyAccessMode) i << ": " - << m_accessModeTypeHistogram[i] << " " - << 100.0 * m_accessModeTypeHistogram[i] / requests - << "%" << endl; - } - } - } - - out << endl; -} - -void -CacheProfiler::clearStats() -{ - for (int i = 0; i < int(RubyRequestType_NUM); i++) { - m_cacheRequestType[i] = 0; - } - for (int i = 0; i < int(GenericRequestType_NUM); i++) { - m_genericRequestType[i] = 0; - } - m_misses = 0; - m_demand_misses = 0; - m_prefetches = 0; - m_sw_prefetches = 0; - m_hw_prefetches = 0; - for (int i = 0; i < RubyAccessMode_NUM; i++) { - m_accessModeTypeHistogram[i] = 0; - } -} - -void -CacheProfiler::addCacheStatSample(RubyRequestType requestType, - RubyAccessMode accessType, - PrefetchBit pfBit) -{ - m_cacheRequestType[requestType]++; - addStatSample(accessType, pfBit); -} - -void -CacheProfiler::addGenericStatSample(GenericRequestType requestType, - RubyAccessMode accessType, - PrefetchBit pfBit) -{ - m_genericRequestType[requestType]++; - addStatSample(accessType, pfBit); -} - -void -CacheProfiler::addStatSample(RubyAccessMode accessType, - PrefetchBit pfBit) -{ - m_misses++; - - m_accessModeTypeHistogram[accessType]++; - if (pfBit == PrefetchBit_No) { - m_demand_misses++; - } else if (pfBit == PrefetchBit_Yes) { - m_prefetches++; - m_sw_prefetches++; - } else { - // must be L1_HW || L2_HW prefetch - m_prefetches++; - m_hw_prefetches++; - } -} diff -r ff812ed6879f -r 4eadb37db02e src/mem/ruby/profiler/Profiler.hh --- a/src/mem/ruby/profiler/Profiler.hh Sun May 12 12:43:28 2013 -0500 +++ b/src/mem/ruby/profiler/Profiler.hh Mon May 13 11:24:51 2013 -0500 @@ -53,7 +53,6 @@ #include "base/hashmap.hh" #include "mem/protocol/AccessType.hh" #include "mem/protocol/GenericMachineType.hh" -#include "mem/protocol/GenericRequestType.hh" #include "mem/protocol/PrefetchBit.hh" #include "mem/protocol/RubyAccessMode.hh" #include "mem/protocol/RubyRequestType.hh" diff -r ff812ed6879f -r 4eadb37db02e src/mem/ruby/profiler/SConscript --- a/src/mem/ruby/profiler/SConscript Sun May 12 12:43:28 2013 -0500 +++ b/src/mem/ruby/profiler/SConscript Mon May 13 11:24:51 2013 -0500 @@ -37,7 +37,6 @@ Source('AccessTraceForAddress.cc') Source('AddressProfiler.cc') -Source('CacheProfiler.cc') Source('MemCntrlProfiler.cc') Source('Profiler.cc') Source('StoreTrace.cc') diff -r ff812ed6879f -r 4eadb37db02e src/mem/ruby/system/CacheMemory.hh --- a/src/mem/ruby/system/CacheMemory.hh Sun May 12 12:43:28 2013 -0500 +++ b/src/mem/ruby/system/CacheMemory.hh Mon May 13 11:24:51 2013 -0500 @@ -36,10 +36,8 @@ #include "base/statistics.hh" #include "mem/protocol/CacheResourceType.hh" #include "mem/protocol/CacheRequestType.hh" -#include "mem/protocol/GenericRequestType.hh" #include "mem/protocol/RubyRequest.hh" #include "mem/ruby/common/DataBlock.hh" -#include "mem/ruby/profiler/CacheProfiler.hh" #include "mem/ruby/recorder/CacheRecorder.hh" #include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" @@ -100,34 +98,37 @@ // Set this address to most recently used void setMRU(const Address& address); - void profileMiss(const RubyRequest & msg); - - void profileGenericRequest(GenericRequestType requestType, - RubyAccessMode accessType, - PrefetchBit pfBit); - void setLocked (const Address& addr, int context); void clearLocked (const Address& addr); bool isLocked (const Address& addr, int context); + // Print cache contents void print(std::ostream& out) const; void printData(std::ostream& out) const; - void clearStats() const; - void printStats(std::ostream& out) const; + void regStats(); + bool checkResourceAvailable(CacheResourceType res, Address addr); + void recordRequestType(CacheRequestType requestType); - void recordRequestType(CacheRequestType requestType); - void regStats(); + public: + Stats::Scalar m_demand_hits; + Stats::Scalar m_demand_misses; + Stats::Formula m_demand_accesses; + + Stats::Scalar m_sw_prefetches; + Stats::Scalar m_hw_prefetches; + Stats::Formula m_prefetches; + + Stats::Vector m_accessModeType; Stats::Scalar numDataArrayReads; Stats::Scalar numDataArrayWrites; Stats::Scalar numTagArrayReads; Stats::Scalar numTagArrayWrites; - bool checkResourceAvailable(CacheResourceType res, Address addr); - Stats::Scalar numTagArrayStalls; Stats::Scalar numDataArrayStalls; + private: // convert a Address to its location in the cache Index addressToCacheSet(const Address& address) const; @@ -156,8 +157,6 @@ AbstractReplacementPolicy *m_replacementPolicy_ptr; - CacheProfiler* m_profiler_ptr; - BankedArray dataArray; BankedArray tagArray; diff -r ff812ed6879f -r 4eadb37db02e src/mem/ruby/system/CacheMemory.cc --- a/src/mem/ruby/system/CacheMemory.cc Sun May 12 12:43:28 2013 -0500 +++ b/src/mem/ruby/system/CacheMemory.cc Mon May 13 11:24:51 2013 -0500 @@ -60,7 +60,6 @@ m_latency = p->latency; m_cache_assoc = p->assoc; m_policy = p->replacement_policy; - m_profiler_ptr = new CacheProfiler(name()); m_start_index_bit = p->start_index_bit; m_is_instruction_only_cache = p->is_icache; m_resource_stalls = p->resourceStalls; @@ -97,7 +96,6 @@ { if (m_replacementPolicy_ptr != NULL) delete m_replacementPolicy_ptr; - delete m_profiler_ptr; for (int i = 0; i < m_cache_num_sets; i++) { for (int j = 0; j < m_cache_assoc; j++) { delete m_cache[i][j]; @@ -325,24 +323,6 @@ } void -CacheMemory::profileMiss(const RubyRequest& msg) -{ - m_profiler_ptr->addCacheStatSample(msg.getType(), - msg.getAccessMode(), - msg.getPrefetch()); -} - -void -CacheMemory::profileGenericRequest(GenericRequestType requestType, - RubyAccessMode accessType, - PrefetchBit pfBit) -{ - m_profiler_ptr->addGenericStatSample(requestType, - accessType, - pfBit); -} - -void CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const { uint64 warmedUpBlocks = 0; @@ -407,18 +387,6 @@ } void -CacheMemory::clearStats() const -{ - m_profiler_ptr->clearStats(); -} - -void -CacheMemory::printStats(ostream& out) const -{ - m_profiler_ptr->printStats(out); -} - -void CacheMemory::setLocked(const Address& address, int context) { DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context); @@ -453,31 +421,53 @@ } void -CacheMemory::recordRequestType(CacheRequestType requestType) { - DPRINTF(RubyStats, "Recorded statistic: %s\n", - CacheRequestType_to_string(requestType)); - switch(requestType) { - case CacheRequestType_DataArrayRead: - numDataArrayReads++; - return; - case CacheRequestType_DataArrayWrite: - numDataArrayWrites++; - return; - case CacheRequestType_TagArrayRead: - numTagArrayReads++; - return; - case CacheRequestType_TagArrayWrite: - numTagArrayWrites++; - return; - default: - warn("CacheMemory access_type not found: %s", - CacheRequestType_to_string(requestType)); +CacheMemory::regStats() +{ + m_demand_hits + .name(name() + ".demand_hits") + .desc("Number of cache demand hits") + ; + + m_demand_misses + .name(name() + ".demand_misses") + .desc("Number of cache demand misses") + ; + + m_demand_accesses + .name(name() + ".demand_accesses") + .desc("Number of cache demand accesses") + ; + + m_demand_accesses = m_demand_hits + m_demand_misses; + + m_sw_prefetches + .name(name() + ".total_sw_prefetches") + .desc("Number of software prefetches") + ; + + m_hw_prefetches + .name(name() + ".total_hw_prefetches") + .desc("Number of hardware prefetches") + ; + + m_prefetches + .name(name() + ".total_prefetches") + .desc("Number of prefetches") + ; + + m_prefetches = m_sw_prefetches + m_hw_prefetches; + + m_accessModeType + .init(RubyRequestType_NUM) + .name(name() + ".access_mode") + .flags(Stats::pdf | Stats::total) + ; + for (int i = 0; i < RubyAccessMode_NUM; i++) { + m_accessModeType + .subname(i, RubyAccessMode_to_string(RubyAccessMode(i))) + .flags(Stats::nozero) + ; } -} - -void -CacheMemory::regStats() { - using namespace Stats; numDataArrayReads .name(name() + ".num_data_array_reads") @@ -510,6 +500,30 @@ ; } +void +CacheMemory::recordRequestType(CacheRequestType requestType) +{ + DPRINTF(RubyStats, "Recorded statistic: %s\n", + CacheRequestType_to_string(requestType)); + switch(requestType) { + case CacheRequestType_DataArrayRead: + numDataArrayReads++; + return; + case CacheRequestType_DataArrayWrite: + numDataArrayWrites++; + return; + case CacheRequestType_TagArrayRead: + numTagArrayReads++; + return; + case CacheRequestType_TagArrayWrite: + numTagArrayWrites++; + return; + default: + warn("CacheMemory access_type not found: %s", + CacheRequestType_to_string(requestType)); + } +} + bool CacheMemory::checkResourceAvailable(CacheResourceType res, Address addr) { @@ -520,14 +534,18 @@ if (res == CacheResourceType_TagArray) { if (tagArray.tryAccess(addressToCacheSet(addr))) return true; else { - DPRINTF(RubyResourceStalls, "Tag array stall on addr %s in set %d\n", addr, addressToCacheSet(addr)); + DPRINTF(RubyResourceStalls, + "Tag array stall on addr %s in set %d\n", + addr, addressToCacheSet(addr)); numTagArrayStalls++; return false; } } else if (res == CacheResourceType_DataArray) { if (dataArray.tryAccess(addressToCacheSet(addr))) return true; else { - DPRINTF(RubyResourceStalls, "Data array stall on addr %s in set %d\n", addr, addressToCacheSet(addr)); + DPRINTF(RubyResourceStalls, + "Data array stall on addr %s in set %d\n", + addr, addressToCacheSet(addr)); numDataArrayStalls++; return false; } diff -r ff812ed6879f -r 4eadb37db02e src/mem/slicc/ast/InfixOperatorExprAST.py --- a/src/mem/slicc/ast/InfixOperatorExprAST.py Sun May 12 12:43:28 2013 -0500 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,91 +0,0 @@ -# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood -# Copyright (c) 2009 The Hewlett-Packard Development Company -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -from slicc.ast.ExprAST import ExprAST -from slicc.symbols import Type - -class InfixOperatorExprAST(ExprAST): - def __init__(self, slicc, left, op, right): - super(InfixOperatorExprAST, self).__init__(slicc) - - self.left = left - self.op = op - self.right = right - - def __repr__(self): - return "[InfixExpr: %r %s %r]" % (self.left, self.op, self.right) - - def generate(self, code): - lcode = self.slicc.codeFormatter() - rcode = self.slicc.codeFormatter() - - ltype = self.left.generate(lcode) - rtype = self.right.generate(rcode) - - # Figure out what the input and output types should be - if self.op in ("==", "!=", ">=", "<=", ">", "<"): - output = "bool" - if (ltype != rtype): - self.error("Type mismatch: left and right operands of " + - "operator '%s' must be the same type. " + - "left: '%s', right: '%s'", - self.op, ltype, rtype) - else: - expected_types = [] - output = None - - if self.op in ("&&", "||"): - # boolean inputs and output - expected_types = [("bool", "bool", "bool")] - elif self.op in ("<<", ">>"): - expected_types = [("int", "int", "int"), - ("Cycles", "int", "Cycles")] - elif self.op in ("+", "-", "*", "/"): - expected_types = [("int", "int", "int"), - ("Cycles", "Cycles", "Cycles"), - ("Cycles", "int", "Cycles"), - ("int", "Cycles", "Cycles")] - else: - self.error("No operator matched with {0}!" .format(self.op)) - - for expected_type in expected_types: - left_input_type = self.symtab.find(expected_type[0], Type) - right_input_type = self.symtab.find(expected_type[1], Type) - - if (left_input_type == ltype) and (right_input_type == rtype): - output = expected_type[2] - - if output == None: - self.error("Type mismatch: operands ({0}, {1}) for operator " \ - "'{2}' failed to match with the expected types" . - format(ltype, rtype, self.op)) - - # All is well - fix = code.nofix() - code("($lcode ${{self.op}} $rcode)") - code.fix(fix) - return self.symtab.find(output, Type) diff -r ff812ed6879f -r 4eadb37db02e src/mem/slicc/ast/OperatorExprAST.py --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/mem/slicc/ast/OperatorExprAST.py Mon May 13 11:24:51 2013 -0500 @@ -0,0 +1,112 @@ +# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood +# Copyright (c) 2009 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from slicc.ast.ExprAST import ExprAST +from slicc.symbols import Type + +class InfixOperatorExprAST(ExprAST): + def __init__(self, slicc, left, op, right): + super(InfixOperatorExprAST, self).__init__(slicc) + + self.left = left + self.op = op + self.right = right + + def __repr__(self): + return "[InfixExpr: %r %s %r]" % (self.left, self.op, self.right) + + def generate(self, code): + lcode = self.slicc.codeFormatter() + rcode = self.slicc.codeFormatter() + + ltype = self.left.generate(lcode) + rtype = self.right.generate(rcode) + + # Figure out what the input and output types should be + if self.op in ("==", "!=", ">=", "<=", ">", "<"): + output = "bool" + if (ltype != rtype): + self.error("Type mismatch: left and right operands of " + + "operator '%s' must be the same type. " + + "left: '%s', right: '%s'", + self.op, ltype, rtype) + else: + expected_types = [] + output = None + + if self.op in ("&&", "||"): + # boolean inputs and output + expected_types = [("bool", "bool", "bool")] + elif self.op in ("<<", ">>"): + expected_types = [("int", "int", "int"), + ("Cycles", "int", "Cycles")] + elif self.op in ("+", "-", "*", "/"): + expected_types = [("int", "int", "int"), + ("Cycles", "Cycles", "Cycles"), + ("Cycles", "int", "Cycles"), + ("Scalar", "int", "Scalar"), + ("int", "Cycles", "Cycles")] + else: + self.error("No operator matched with {0}!" .format(self.op)) + + for expected_type in expected_types: + left_input_type = self.symtab.find(expected_type[0], Type) + right_input_type = self.symtab.find(expected_type[1], Type) + + if (left_input_type == ltype) and (right_input_type == rtype): + output = expected_type[2] + + if output == None: + self.error("Type mismatch: operands ({0}, {1}) for operator " \ + "'{2}' failed to match with the expected types" . + format(ltype, rtype, self.op)) + + # All is well + fix = code.nofix() + code("($lcode ${{self.op}} $rcode)") + code.fix(fix) + return self.symtab.find(output, Type) + +class PrefixOperatorExprAST(ExprAST): + def __init__(self, slicc, op, operand): + super(PrefixOperatorExprAST, self).__init__(slicc) + + self.op = op + self.operand = operand + + def __repr__(self): + return "[PrefixExpr: %s %r]" % (self.op, self.operand) + + def generate(self, code): + opcode = self.slicc.codeFormatter() + optype = self.operand.generate(opcode) + + fix = code.nofix() + code("(${{self.op}} $opcode)") + code.fix(fix) + + return self.symtab.find("void", Type) diff -r ff812ed6879f -r 4eadb37db02e src/mem/slicc/ast/__init__.py --- a/src/mem/slicc/ast/__init__.py Sun May 12 12:43:28 2013 -0500 +++ b/src/mem/slicc/ast/__init__.py Mon May 13 11:24:51 2013 -0500 @@ -43,7 +43,6 @@ from slicc.ast.FuncDeclAST import * from slicc.ast.IfStatementAST import * from slicc.ast.InPortDeclAST import * -from slicc.ast.InfixOperatorExprAST import * from slicc.ast.IsValidPtrExprAST import * from slicc.ast.LiteralExprAST import * from slicc.ast.LocalVariableAST import * @@ -53,6 +52,7 @@ from slicc.ast.NewExprAST import * from slicc.ast.OodAST import * from slicc.ast.ObjDeclAST import * +from slicc.ast.OperatorExprAST import * from slicc.ast.OutPortDeclAST import * from slicc.ast.PairAST import * from slicc.ast.PairListAST import * diff -r ff812ed6879f -r 4eadb37db02e src/mem/slicc/parser.py --- a/src/mem/slicc/parser.py Sun May 12 12:43:28 2013 -0500 +++ b/src/mem/slicc/parser.py Mon May 13 11:24:51 2013 -0500 @@ -132,6 +132,7 @@ 'LEFTSHIFT', 'RIGHTSHIFT', 'NOT', 'AND', 'OR', 'PLUS', 'DASH', 'STAR', 'SLASH', + 'INCR', 'DECR', 'DOUBLE_COLON', 'SEMI', 'ASSIGN', 'DOT', 'IDENT', 'LIT_BOOL', 'FLOATNUMBER', 'NUMBER', 'STRING' ] @@ -156,8 +157,11 @@ t_SEMI = r';' t_ASSIGN = r':=' t_DOT = r'\.' + t_INCR = r'\+\+' + t_DECR = r'--' precedence = ( + ('left', 'INCR', 'DECR'), ('left', 'AND', 'OR'), ('left', 'EQ', 'NE'), ('left', 'LT', 'GT', 'LE', 'GE'), @@ -670,8 +674,10 @@ # FIXME - unary not def p_expr__unary_op(self, p): """expr : NOT expr + | INCR expr + | DECR expr | DASH expr %prec UMINUS""" - p[0] = PrefixOperatorExpr(p[1], p[2]) + p[0] = ast.PrefixOperatorExprAST(self, p[1], p[2]) def p_expr__parens(self, p): "aexpr : '(' expr ')'" diff -r ff812ed6879f -r 4eadb37db02e src/mem/slicc/symbols/StateMachine.py --- a/src/mem/slicc/symbols/StateMachine.py Sun May 12 12:43:28 2013 -0500 +++ b/src/mem/slicc/symbols/StateMachine.py Mon May 13 11:24:51 2013 -0500 @@ -768,8 +768,7 @@ # them. Print out these stats before dumping state transition stats. # for param in self.config_parameters: - if param.type_ast.type.ident == "CacheMemory" or \ - param.type_ast.type.ident == "DirectoryMemory" or \ + if param.type_ast.type.ident == "DirectoryMemory" or \ param.type_ast.type.ident == "MemoryControl": assert(param.pointer) code(' m_${{param.ident}}_ptr->printStats(out);') @@ -787,8 +786,7 @@ # them. These stats must be cleared too. # for param in self.config_parameters: - if param.type_ast.type.ident == "CacheMemory" or \ - param.type_ast.type.ident == "MemoryControl": + if param.type_ast.type.ident == "MemoryControl": assert(param.pointer) code(' m_${{param.ident}}_ptr->clearStats();')