diff -r 5708a2e568c9 -r 7e85a13bd4a7 src/arch/arm/isa/formats/m5ops.isa --- a/src/arch/arm/isa/formats/m5ops.isa Tue May 07 14:47:58 2013 +0200 +++ b/src/arch/arm/isa/formats/m5ops.isa Tue May 07 14:48:31 2013 +0200 @@ -53,6 +53,7 @@ case 0x11: return new Deprecated_ivle(machInst); case 0x20: return new Deprecated_exit (machInst); case 0x21: return new M5exit(machInst); + case 0x22: return new M5fail(machInst); case 0x31: return new Loadsymbol(machInst); case 0x30: return new Initparam(machInst); case 0x40: return new Resetstats(machInst); diff -r 5708a2e568c9 -r 7e85a13bd4a7 src/arch/arm/isa/insts/m5ops.isa --- a/src/arch/arm/isa/insts/m5ops.isa Tue May 07 14:47:58 2013 +0200 +++ b/src/arch/arm/isa/insts/m5ops.isa Tue May 07 14:48:31 2013 +0200 @@ -179,6 +179,17 @@ decoder_output += BasicConstructor.subst(m5exitIop) exec_output += PredOpExecute.subst(m5exitIop) + m5fail_code = ''' + PseudoInst::m5fail(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); + ''' + m5failIop = InstObjParams("m5fail", "M5fail", "PredOp", + { "code": m5fail_code, + "predicate_test": predicateTest }, + ["No_OpClass", "IsNonSpeculative"]) + header_output += BasicDeclare.subst(m5failIop) + decoder_output += BasicConstructor.subst(m5failIop) + exec_output += PredOpExecute.subst(m5failIop) + loadsymbolCode = ''' PseudoInst::loadsymbol(xc->tcBase()); ''' diff -r 5708a2e568c9 -r 7e85a13bd4a7 util/m5/m5op_arm.S --- a/util/m5/m5op_arm.S Tue May 07 14:47:58 2013 +0200 +++ b/util/m5/m5op_arm.S Tue May 07 14:48:31 2013 +0200 @@ -90,6 +90,7 @@ SIMPLE_OP(rpns, rpns_func, 0) SIMPLE_OP(wakeCPU, wakecpu_func, 0) SIMPLE_OP(m5_exit, exit_func, 0) +SIMPLE_OP(m5_fail, fail_func, 0) SIMPLE_OP(m5_initparam, initparam_func, 0) SIMPLE_OP(m5_loadsymbol, loadsymbol_func, 0) SIMPLE_OP(m5_reset_stats, resetstats_func, 0)