diff -r e13fcf4f00d3 -r 8b4148f5c356 src/arch/arm/table_walker.hh
--- a/src/arch/arm/table_walker.hh	Fri Aug 13 11:58:44 2010 -0500
+++ b/src/arch/arm/table_walker.hh	Fri Aug 13 11:59:07 2010 -0500
@@ -106,13 +106,13 @@
         /** Is the translation global (no asid used)? */
         bool global() const
         {
-            return bits(data, 4);
+            return bits(data, 17);
         }
 
         /** Is the translation not allow execution? */
         bool xn() const
         {
-            return bits(data, 17);
+            return bits(data, 4);
         }
 
         /** Three bit access protection flags */
diff -r e13fcf4f00d3 -r 8b4148f5c356 src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc	Fri Aug 13 11:58:44 2010 -0500
+++ b/src/arch/arm/table_walker.cc	Fri Aug 13 11:59:07 2010 -0500
@@ -166,8 +166,12 @@
         assert(stateQueue.size() < 5);
         currState = NULL;
     } else {
+        Request::Flags flag = 0;
+        if (currState->sctlr.c == 0){
+           flag = Request::UNCACHEABLE;
+        }
         port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
-                NULL, (uint8_t*)&currState->l1Desc.data, (Tick)0);
+                NULL, (uint8_t*)&currState->l1Desc.data, (Tick)0, flag);
         doL1Descriptor();
         f = currState->fault;
     }
diff -r e13fcf4f00d3 -r 8b4148f5c356 src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc	Fri Aug 13 11:58:44 2010 -0500
+++ b/src/arch/arm/tlb.cc	Fri Aug 13 11:59:07 2010 -0500
@@ -363,6 +363,10 @@
        req->setFlags(Request::UNCACHEABLE);
        return NoFault;
     }
+    if ((req->isInstFetch() && (!sctlr.i)) ||
+        ((!req->isInstFetch()) && (!sctlr.c))){
+       req->setFlags(Request::UNCACHEABLE);
+    }
     if (!is_fetch) {
         assert(flags & MustBeOne);
         if (sctlr.a || !(flags & AllowUnaligned)) {