diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,249 +0,0 @@ -[root] -type=Root -children=system -full_system=false -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -boot_osflags=a -clock=1000 -init_param=0 -kernel= -load_addr_mask=1099511627775 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.cpu] -type=InOrderCPU -children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -activity=0 -branchPred=system.cpu.branchPred -cachePorts=2 -checker=Null -clock=500 -cpu_id=0 -div16Latency=1 -div16RepeatRate=1 -div24Latency=1 -div24RepeatRate=1 -div32Latency=1 -div32RepeatRate=1 -div8Latency=1 -div8RepeatRate=1 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -fetchBuffSize=4 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -memBlockSize=64 -multLatency=1 -multRepeatRate=1 -numThreads=1 -profile=0 -progress_interval=0 -stageTracing=false -stageWidth=4 -switched_out=false -system=system -threadModel=SMT -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=BranchPredictor -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -instShiftAmt=2 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -predType=tournament - -[system.cpu.dcache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=262144 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.icache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=131072 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.interrupts] -type=AlphaInterrupts - -[system.cpu.isa] -type=AlphaISA - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.l2cache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -size=2097152 -system=system -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.toL2Bus] -type=CoherentBus -block_size=64 -clock=500 -header_cycles=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleDRAM -activation_limit=4 -addr_mapping=openmap -banks_per_rank=8 -channels=1 -clock=1000 -conf_table_reported=false -in_addr_map=true -lines_per_rowbuffer=32 -mem_sched_policy=frfcfs -null=false -page_policy=open -range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -tBURST=5000 -tCL=13750 -tRCD=13750 -tREFI=7800000 -tRFC=300000 -tRP=13750 -tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_thresh_perc=70 -zero=false -port=system.membus.master[0] - diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,44 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Mar 26 2013 14:38:52 -gem5 started Mar 26 2013 22:56:38 -gem5 executing on ribera.cs.wisc.edu -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 269668883500 because target called exit() diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,733 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.269776 # Number of seconds simulated -sim_ticks 269776023500 # Number of ticks simulated -final_tick 269776023500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123588 # Simulator instruction rate (inst/s) -host_op_rate 123588 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55396938 # Simulator tick rate (ticks/s) -host_mem_usage 225204 # Number of bytes of host memory used -host_seconds 4869.87 # Real time elapsed on the host -sim_insts 601856964 # Number of instructions simulated -sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1628992 # Number of bytes read from this memory -system.physmem.bytes_read::total 1682816 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 53824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 53824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 64896 # Number of bytes written to this memory -system.physmem.bytes_written::total 64896 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 841 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25453 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 199514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6038313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6237826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199514 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199514 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 240555 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 240555 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 240555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6038313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6478382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26294 # Total number of read requests seen -system.physmem.writeReqs 1014 # Total number of write requests seen -system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1682816 # Total number of bytes read from memory -system.physmem.bytesWritten 64896 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1682816 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 64896 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1579 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1690 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1680 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1732 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1719 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1812 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1867 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1570 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1650 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1658 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1444 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1493 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1505 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 49 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 70 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 71 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 70 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 82 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 95 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 79 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 54 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 64 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 89 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 35 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 33 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 38 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 48 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 269775950500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26294 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1014 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 17586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 443 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 8692 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 200.548550 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.216936 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 827.222643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 7745 89.10% 89.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 118 1.36% 90.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 74 0.85% 91.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 56 0.64% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 40 0.46% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 23 0.26% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 20 0.23% 92.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 390 4.49% 97.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 4 0.05% 97.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 9 0.10% 97.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 7 0.08% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 6 0.07% 97.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 2 0.02% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 4 0.05% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 7 0.08% 97.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 4 0.05% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 3 0.03% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 2 0.02% 97.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 1 0.01% 97.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 9 0.10% 98.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 1 0.01% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 2 0.02% 98.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.05% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 2 0.02% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.01% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 2 0.02% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 3 0.03% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 4 0.05% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 3 0.03% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 4 0.05% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 3 0.03% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.01% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 2 0.02% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 3 0.03% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.01% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 2 0.02% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 2 0.02% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 2 0.02% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.01% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 2 0.02% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 4 0.05% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.01% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 1 0.01% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 2 0.02% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.02% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.01% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 1 0.01% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.01% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.01% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.01% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 2 0.02% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 3 0.03% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.01% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.01% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 2 0.02% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 1 0.01% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 1 0.01% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 2 0.02% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 1 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 1 0.01% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 2 0.02% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 1 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 1 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.02% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 2 0.02% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 4 0.05% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.01% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.02% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 1 0.01% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 44 0.51% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 9 0.10% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 5 0.06% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.02% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 11 0.13% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8577 2 0.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 8692 # Bytes accessed per row activation -system.physmem.totQLat 330414750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 997597250 # Sum of mem lat for all requests -system.physmem.totBusLat 131400000 # Total cycles spent in databus access -system.physmem.totBankLat 535782500 # Total cycles spent in bank access -system.physmem.avgQLat 12572.86 # Average queueing delay per request -system.physmem.avgBankLat 20387.46 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 37960.32 # Average memory access latency -system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.24 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 12.19 # Average write queue length over time -system.physmem.readRowHits 18015 # Number of row buffer hits during reads -system.physmem.writeRowHits 585 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.69 # Row buffer hit rate for writes -system.physmem.avgGap 9879008.00 # Average gap between requests -system.membus.throughput 6478382 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4966 # Transaction distribution -system.membus.trans_dist::ReadResp 4966 # Transaction distribution -system.membus.trans_dist::Writeback 1014 # Transaction distribution -system.membus.trans_dist::ReadExReq 21328 # Transaction distribution -system.membus.trans_dist::ReadExResp 21328 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 53602 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 53602 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1747712 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 1747712 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1747712 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 40989000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 248829250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 86401390 # Number of BP lookups -system.cpu.branchPred.condPredicted 81471120 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 36340860 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 45048024 # Number of BTB lookups -system.cpu.branchPred.BTBHits 34648140 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 76.913784 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1197609 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114525365 # DTB read hits -system.cpu.dtb.read_misses 2631 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114527996 # DTB read accesses -system.cpu.dtb.write_hits 39457856 # DTB write hits -system.cpu.dtb.write_misses 2302 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39460158 # DTB write accesses -system.cpu.dtb.data_hits 153983221 # DTB hits -system.cpu.dtb.data_misses 4933 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 153988154 # DTB accesses -system.cpu.itb.fetch_hits 24966986 # ITB hits -system.cpu.itb.fetch_misses 22 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 24967008 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 539552048 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 37213742 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49187648 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541069833 # Number of Reads from Int. Register File -system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1004924679 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File -system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255160319 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 154930401 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 34118747 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 2217126 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36335873 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 26212045 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.092858 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 412134922 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed -system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 535777201 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 290203 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 51010433 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 488541615 # Number of cycles cpu stages are processed. -system.cpu.activity 90.545781 # Percentage of cycles cpu is active -system.cpu.comLoads 114514042 # Number of Load instructions committed -system.cpu.comStores 39451321 # Number of Store instructions committed -system.cpu.comBranches 62547159 # Number of Branches instructions committed -system.cpu.comNops 36304520 # Number of Nop instructions committed -system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed -system.cpu.comInts 349039879 # Number of Integer instructions committed -system.cpu.comFloats 24 # Number of Floating Point instructions committed -system.cpu.committedInsts 601856964 # Number of Instructions committed (Per-Thread) -system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) -system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.896479 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.896479 # CPI: Total CPI of All Threads -system.cpu.ipc 1.115475 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.115475 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 200817970 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338734078 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.780612 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 229121433 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310430615 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 57.534878 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 197986938 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341565110 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.305312 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 428172418 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111379630 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.642982 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 192746875 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 346805173 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.276500 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 729.665989 # Cycle average of tags in use -system.cpu.icache.total_refs 24965947 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29199.938012 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 729.665989 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.356282 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.356282 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 24965947 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24965947 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24965947 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24965947 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24965947 # number of overall hits -system.cpu.icache.overall_hits::total 24965947 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1039 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1039 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1039 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1039 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1039 # number of overall misses -system.cpu.icache.overall_misses::total 1039 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 72873000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 72873000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 72873000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 72873000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 72873000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 72873000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24966986 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24966986 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24966986 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24966986 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24966986 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24966986 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70137.632339 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70137.632339 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70137.632339 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70137.632339 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70137.632339 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70137.632339 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 134.500000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 184 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 184 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 184 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 184 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 184 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59756000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59756000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59756000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59756000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59756000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59756000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69890.058480 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69890.058480 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69890.058480 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69890.058480 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69890.058480 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69890.058480 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 211882314 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 202062 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 202062 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 436887 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 254188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 254188 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1710 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1347677 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 1349387 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 57106048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 57160768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 57160768 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 883455500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1449000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 688241749 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.cpu.l2cache.replacements 1042 # number of replacements -system.cpu.l2cache.tagsinuse 22872.993064 # Cycle average of tags in use -system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21677.946828 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 718.787739 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 476.258496 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.661558 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021936 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.014534 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.698028 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 436887 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 436887 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 232860 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 232860 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 429942 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 429956 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 429942 # number of overall hits -system.cpu.l2cache.overall_hits::total 429956 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 841 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4125 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4966 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21328 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21328 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 841 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 25453 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 26294 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses -system.cpu.l2cache.overall_misses::total 26294 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58750500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 555510500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 614261000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1532678750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1532678750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 58750500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2088189250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2146939750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 58750500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2088189250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2146939750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 436887 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 436887 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254188 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254188 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 855 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020501 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.024577 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083906 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083906 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.055892 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.057631 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69857.907253 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 134669.212121 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 123693.314539 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71862.281977 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71862.281977 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69857.907253 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82040.987310 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81651.317791 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69857.907253 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82040.987310 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81651.317791 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1014 # number of writebacks -system.cpu.l2cache.writebacks::total 1014 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 841 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4125 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4966 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21328 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21328 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 841 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 25453 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 26294 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48169500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 502168000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 550337500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1263569750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1263569750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48169500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1765737750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1813907250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48169500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1765737750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1813907250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083906 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083906 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57276.456599 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 121737.696970 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 110821.083367 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59244.643192 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59244.643192 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57276.456599 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69372.480651 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68985.595573 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57276.456599 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69372.480651 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68985.595573 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.035549 # Cycle average of tags in use -system.cpu.dcache.total_refs 151792737 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 333.321044 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 384920250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.035549 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999276 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999276 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114127973 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114127973 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37664764 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37664764 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 151792737 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 151792737 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 151792737 # number of overall hits -system.cpu.dcache.overall_hits::total 151792737 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 386069 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 386069 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1786557 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1786557 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2172626 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2172626 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2172626 # number of overall misses -system.cpu.dcache.overall_misses::total 2172626 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6062745499 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6062745499 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25260713000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25260713000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31323458499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31323458499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31323458499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31323458499 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003371 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003371 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045285 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045285 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014111 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014111 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014111 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014111 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15703.787403 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15703.787403 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14139.326649 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14139.326649 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14417.326544 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14417.326544 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14417.326544 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14417.326544 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 387899 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 964 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 21259 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.246343 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 96.400000 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks -system.cpu.dcache.writebacks::total 436887 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 184837 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 184837 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1532394 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1532394 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1717231 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1717231 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1717231 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1717231 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2728617501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2728617501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4116783250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4116783250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6845400751 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6845400751 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6845400751 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6845400751 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13559.560612 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13559.560612 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16197.413668 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16197.413668 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15031.787242 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15031.787242 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15031.787242 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15031.787242 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,549 +0,0 @@ -[root] -type=Root -children=system -full_system=false -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -boot_osflags=a -clock=1000 -init_param=0 -kernel= -load_addr_mask=1099511627775 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clock=500 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbDepth=1 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=BranchPredictor -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -instShiftAmt=2 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -predType=tournament - -[system.cpu.dcache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=262144 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -issueLat=1 -opClass=SimdAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -issueLat=1 -opClass=SimdAddAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -issueLat=1 -opClass=SimdAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -issueLat=1 -opClass=SimdCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -issueLat=1 -opClass=SimdCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -issueLat=1 -opClass=SimdMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -issueLat=1 -opClass=SimdMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -issueLat=1 -opClass=SimdMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -issueLat=1 -opClass=SimdShift -opLat=1 - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -issueLat=1 -opClass=SimdShiftAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -issueLat=1 -opClass=SimdSqrt -opLat=1 - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -issueLat=1 -opClass=SimdFloatAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -issueLat=1 -opClass=SimdFloatAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -issueLat=1 -opClass=SimdFloatCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -issueLat=1 -opClass=SimdFloatCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -issueLat=1 -opClass=SimdFloatDiv -opLat=1 - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -issueLat=1 -opClass=SimdFloatMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -issueLat=1 -opClass=SimdFloatMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -issueLat=1 -opClass=SimdFloatMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -issueLat=1 -opClass=SimdFloatSqrt -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=131072 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.interrupts] -type=AlphaInterrupts - -[system.cpu.isa] -type=AlphaISA - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.l2cache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -size=2097152 -system=system -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.toL2Bus] -type=CoherentBus -block_size=64 -clock=500 -header_cycles=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleDRAM -activation_limit=4 -addr_mapping=openmap -banks_per_rank=8 -channels=1 -clock=1000 -conf_table_reported=false -in_addr_map=true -lines_per_rowbuffer=32 -mem_sched_policy=frfcfs -null=false -page_policy=open -range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -tBURST=5000 -tCL=13750 -tRCD=13750 -tREFI=7800000 -tRFC=300000 -tRP=13750 -tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_thresh_perc=70 -zero=false -port=system.membus.master[0] - diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,44 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Mar 26 2013 14:38:52 -gem5 started Mar 26 2013 22:56:39 -gem5 executing on ribera.cs.wisc.edu -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 133696809500 because target called exit() diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,951 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.133962 # Number of seconds simulated -sim_ticks 133961951000 # Number of ticks simulated -final_tick 133961951000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 274067 # Simulator instruction rate (inst/s) -host_op_rate 274067 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64918100 # Simulator tick rate (ticks/s) -host_mem_usage 228276 # Number of bytes of host memory used -host_seconds 2063.55 # Real time elapsed on the host -sim_insts 565552443 # Number of instructions simulated -sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1636352 # Number of bytes read from this memory -system.physmem.bytes_read::total 1697728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67200 # Number of bytes written to this memory -system.physmem.bytes_written::total 67200 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 959 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25568 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26527 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 458160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12215051 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12673210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 458160 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 458160 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 501635 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 501635 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 501635 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 458160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12215051 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13174845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26527 # Total number of read requests seen -system.physmem.writeReqs 1050 # Total number of write requests seen -system.physmem.cpureqs 27577 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1697728 # Total number of bytes read from memory -system.physmem.bytesWritten 67200 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1697728 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67200 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1674 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1680 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1699 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1739 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1730 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1816 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1871 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1786 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1570 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1674 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1461 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1441 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1505 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1513 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 64 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 61 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 71 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 72 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 72 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 82 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 95 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 80 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 54 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 66 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 90 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 36 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 35 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 46 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 52 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 133961884500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26527 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1050 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 12186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9749 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 4008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 8247 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 213.038438 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 86.721167 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 848.030298 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 6734 81.65% 81.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 624 7.57% 89.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 110 1.33% 90.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 60 0.73% 91.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 41 0.50% 91.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 35 0.42% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 13 0.16% 92.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 393 4.77% 97.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 7 0.08% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 11 0.13% 97.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 4 0.05% 97.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 7 0.08% 97.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 7 0.08% 97.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 5 0.06% 97.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 10 0.12% 97.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 6 0.07% 97.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 4 0.05% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 3 0.04% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 8 0.10% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.04% 98.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.05% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 5 0.06% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 1 0.01% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.04% 98.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.01% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.01% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.01% 98.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.04% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.01% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 1 0.01% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 3 0.04% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 3 0.04% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.01% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.01% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.01% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.01% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.01% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.01% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.01% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 3 0.04% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.01% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.02% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.01% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 1 0.01% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 2 0.02% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.01% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.01% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 1 0.01% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.01% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.02% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.01% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.01% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.01% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 1 0.01% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.01% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.01% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.01% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.01% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 1 0.01% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.01% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 2 0.02% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 3 0.04% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 1 0.01% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.01% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 1 0.01% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 2 0.02% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.01% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 2 0.02% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 5 0.06% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 2 0.02% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.02% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.01% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.01% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.01% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 2 0.02% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 43 0.52% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 11 0.13% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 4 0.05% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 3 0.04% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 12 0.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 8247 # Bytes accessed per row activation -system.physmem.totQLat 455558500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1106686000 # Sum of mem lat for all requests -system.physmem.totBusLat 132560000 # Total cycles spent in databus access -system.physmem.totBankLat 518567500 # Total cycles spent in bank access -system.physmem.avgQLat 17183.11 # Average queueing delay per request -system.physmem.avgBankLat 19559.73 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 41742.83 # Average memory access latency -system.physmem.avgRdBW 12.67 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 12.67 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.50 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.10 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 11.17 # Average write queue length over time -system.physmem.readRowHits 18728 # Number of row buffer hits during reads -system.physmem.writeRowHits 572 # Number of row buffer hits during writes -system.physmem.readRowHitRate 70.64 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 54.48 # Row buffer hit rate for writes -system.physmem.avgGap 4857739.58 # Average gap between requests -system.membus.throughput 13174845 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 5268 # Transaction distribution -system.membus.trans_dist::ReadResp 5268 # Transaction distribution -system.membus.trans_dist::Writeback 1050 # Transaction distribution -system.membus.trans_dist::ReadExReq 21259 # Transaction distribution -system.membus.trans_dist::ReadExResp 21259 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 54104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 54104 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1764928 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 1764928 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1764928 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 41625500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 247947250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu.branchPred.lookups 76509043 # Number of BP lookups -system.cpu.branchPred.condPredicted 70930421 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2718446 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 43095662 # Number of BTB lookups -system.cpu.branchPred.BTBHits 41957176 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.358235 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1605853 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 222 # Number of incorrect RAS predictions. -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 122636896 # DTB read hits -system.cpu.dtb.read_misses 28788 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 122665684 # DTB read accesses -system.cpu.dtb.write_hits 40758812 # DTB write hits -system.cpu.dtb.write_misses 25696 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40784508 # DTB write accesses -system.cpu.dtb.data_hits 163395708 # DTB hits -system.cpu.dtb.data_misses 54484 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 163450192 # DTB accesses -system.cpu.itb.fetch_hits 65557773 # ITB hits -system.cpu.itb.fetch_misses 41 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 65557814 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 267923903 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 67219000 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 699635337 # Number of instructions fetch has processed -system.cpu.fetch.Branches 76509043 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43563029 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 117876511 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11688673 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 73578965 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 68 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1310 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 65557773 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 934073 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 267604647 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.614436 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.444229 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 149728136 55.95% 55.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10348527 3.87% 59.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11847443 4.43% 64.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10580960 3.95% 68.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7011861 2.62% 70.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2871447 1.07% 71.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3585721 1.34% 73.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3114377 1.16% 74.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 68516175 25.60% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 267604647 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285563 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.611321 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 84364018 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57869635 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 102727619 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13715469 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8927906 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3874613 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 958 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 691619312 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3197 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 8927906 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 92357271 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12821399 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1543 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 103118372 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50378156 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 681414869 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 426 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 38680047 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5488182 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 520970773 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 897485300 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 897482658 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2642 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 57115884 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 65 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 69 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112714351 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 127019920 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42392601 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14865825 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10070553 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 621310849 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 604761655 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 300547 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 55122948 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 30038135 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 267604647 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.259907 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.824800 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52578296 19.65% 19.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 56229325 21.01% 40.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53494767 19.99% 60.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36222009 13.54% 74.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31105293 11.62% 85.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23905187 8.93% 94.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10120737 3.78% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3387024 1.27% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 562009 0.21% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 267604647 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2817680 71.18% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 45 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 729147 18.42% 89.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 411755 10.40% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 439197162 72.62% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7093 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 124364949 20.56% 93.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41192403 6.81% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 604761655 # Type of FU issued -system.cpu.iq.rate 2.257214 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3958627 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006546 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1481383364 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 676436973 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 596614518 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3767 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2292 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1715 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 608718386 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1896 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12281873 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12505878 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 36187 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5474 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2941280 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6430 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 65154 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8927906 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1459993 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 195367 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 664215028 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1703267 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 127019920 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42392601 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 55 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 140811 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13981 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5474 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1342343 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1811272 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3153615 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599619564 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 122665822 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5142091 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 42904124 # number of nop insts executed -system.cpu.iew.exec_refs 163468688 # number of memory reference insts executed -system.cpu.iew.exec_branches 66642559 # Number of branches executed -system.cpu.iew.exec_stores 40802866 # Number of stores executed -system.cpu.iew.exec_rate 2.238022 # Inst execution rate -system.cpu.iew.wb_sent 597556464 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 596616233 # cumulative count of insts written-back -system.cpu.iew.wb_producers 415937743 # num instructions producing a value -system.cpu.iew.wb_consumers 530266115 # num instructions consuming a value -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.226812 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.784394 # average fanout of values written-back -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 62234347 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2717577 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 258676741 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.326676 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.691140 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 79762778 30.83% 30.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72612806 28.07% 58.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 25568978 9.88% 68.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9287586 3.59% 72.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10257528 3.97% 76.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20944264 8.10% 84.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6868189 2.66% 87.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3714019 1.44% 88.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29660593 11.47% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 258676741 # Number of insts commited each cycle -system.cpu.commit.committedInsts 601856963 # Number of instructions committed -system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 153965363 # Number of memory references committed -system.cpu.commit.loads 114514042 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 62547159 # Number of branches committed -system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. -system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. -system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29660593 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 893043069 # The number of ROB reads -system.cpu.rob.rob_writes 1337124776 # The number of ROB writes -system.cpu.timesIdled 34637 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 319256 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 565552443 # Number of Instructions Simulated -system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.473738 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.473738 # CPI: Total CPI of All Threads -system.cpu.ipc 2.110870 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.110870 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 845197373 # number of integer regfile reads -system.cpu.int_regfile_writes 490632112 # number of integer regfile writes -system.cpu.fp_regfile_reads 374 # number of floating regfile reads -system.cpu.fp_regfile_writes 54 # number of floating regfile writes -system.cpu.misc_regfile_reads 1 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 435259591 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 211505 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 211505 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 445033 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 254528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 254528 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1956 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1375143 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 1377099 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 58245632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 58308224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 58308224 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 900566000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1650999 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 701150500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu.icache.replacements 40 # number of replacements -system.cpu.icache.tagsinuse 828.962726 # Cycle average of tags in use -system.cpu.icache.total_refs 65556364 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 978 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67031.047035 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 828.962726 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.404767 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.404767 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 65556364 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 65556364 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 65556364 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 65556364 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 65556364 # number of overall hits -system.cpu.icache.overall_hits::total 65556364 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1408 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1408 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1408 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1408 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1408 # number of overall misses -system.cpu.icache.overall_misses::total 1408 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 92804999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 92804999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 92804999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 92804999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 92804999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 92804999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 65557772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 65557772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 65557772 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 65557772 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 65557772 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 65557772 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65912.641335 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 65912.641335 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 65912.641335 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 65912.641335 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 65912.641335 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 65912.641335 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 250 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 41.666667 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 430 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 430 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 430 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 430 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 430 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 430 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 978 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 978 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 978 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 978 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 978 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 978 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68125001 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 68125001 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68125001 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 68125001 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68125001 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 68125001 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69657.465235 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69657.465235 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69657.465235 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69657.465235 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69657.465235 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69657.465235 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1081 # number of replacements -system.cpu.l2cache.tagsinuse 22917.013747 # Cycle average of tags in use -system.cpu.l2cache.total_refs 547313 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23521 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.269121 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21464.188943 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 820.406080 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 632.418725 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.655035 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.025037 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019300 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.699372 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # 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number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4309 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5268 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21259 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21259 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 959 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 25568 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 26527 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 959 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 25568 # number of overall misses -system.cpu.l2cache.overall_misses::total 26527 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 66945250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 431510250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 498455500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1765516750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1765516750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 66945250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2197027000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2263972250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 66945250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2197027000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2263972250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 978 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 210527 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 211505 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 445033 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 445033 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254528 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254528 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 978 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 465055 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 466033 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 978 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 465055 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 466033 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.980573 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020468 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.024907 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083523 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083523 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.980573 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.054978 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.056921 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.980573 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.054978 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.056921 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69807.351408 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 100141.622186 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 94619.495065 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83047.967919 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83047.967919 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69807.351408 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85928.778160 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 85345.958834 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69807.351408 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85928.778160 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 85345.958834 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1050 # number of writebacks -system.cpu.l2cache.writebacks::total 1050 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 959 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4309 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5268 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21259 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21259 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 959 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 25568 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 26527 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 959 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 25568 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26527 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 54810750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 378377250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 433188000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1499253750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1499253750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 54810750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1877631000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1932441750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 54810750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1877631000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1932441750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.980573 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020468 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024907 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083523 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083523 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.980573 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054978 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.056921 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.980573 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054978 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.056921 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57154.066736 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 87810.919007 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 82230.068337 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70523.248977 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70523.248977 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57154.066736 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73436.756884 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72848.107588 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57154.066736 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73436.756884 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72848.107588 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 460959 # number of replacements -system.cpu.dcache.tagsinuse 4090.584067 # Cycle average of tags in use -system.cpu.dcache.total_refs 146932233 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 465055 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 315.945927 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 315666000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4090.584067 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998678 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998678 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 109283545 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 109283545 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37648677 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37648677 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 146932222 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 146932222 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 146932222 # number of overall hits -system.cpu.dcache.overall_hits::total 146932222 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1008038 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1008038 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1802644 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1802644 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2810682 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2810682 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2810682 # number of overall misses -system.cpu.dcache.overall_misses::total 2810682 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15260657250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15260657250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 27641124866 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 27641124866 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 40000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 40000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42901782116 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42901782116 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42901782116 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42901782116 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 110291583 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 110291583 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 149742904 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 149742904 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 149742904 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 149742904 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009140 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009140 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045693 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045693 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.266667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.266667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018770 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018770 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018770 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018770 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15138.970207 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15138.970207 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15333.657043 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 15333.657043 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15263.833517 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15263.833517 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15263.833517 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15263.833517 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 386823 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2168 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 20286 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.068471 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 180.666667 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 445033 # number of writebacks -system.cpu.dcache.writebacks::total 445033 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 797511 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 797511 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548116 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1548116 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2345627 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2345627 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2345627 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2345627 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210527 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210527 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254528 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254528 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 465055 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 465055 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 465055 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 465055 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2709803250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2709803250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4360123743 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4360123743 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7069926993 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7069926993 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7069926993 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7069926993 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001909 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001909 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003106 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003106 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.523605 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.523605 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17130.232206 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17130.232206 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15202.345944 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15202.345944 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15202.345944 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15202.345944 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,124 +0,0 @@ -[root] -type=Root -children=system -full_system=false -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -boot_osflags=a -clock=1000 -init_param=0 -kernel= -load_addr_mask=1099511627775 -mem_mode=atomic -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clock=500 -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simulate_data_stalls=false -simulate_inst_stalls=false -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts - -[system.cpu.isa] -type=AlphaISA - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic -egid=100 -env= -errout=cerr -euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1000 -conf_table_reported=false -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.master[0] - diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,7 +0,0 @@ -warn: CoherentBus system.membus has no snooping ports attached! -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,44 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:29:25 -gem5 executing on ribera.cs.wisc.edu -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 300930958000 because target called exit() diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,95 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.300931 # Number of seconds simulated -sim_ticks 300930958000 # Number of ticks simulated -final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3984763 # Simulator instruction rate (inst/s) -host_op_rate 3984763 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1992397518 # Simulator tick rate (ticks/s) -host_mem_usage 217612 # Number of bytes of host memory used -host_seconds 151.04 # Real time elapsed on the host -sim_insts 601856964 # Number of instructions simulated -sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 2407447588 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 375543340 # Number of bytes read from this memory -system.physmem.bytes_read::total 2782990928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2407447588 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2407447588 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 152669504 # Number of bytes written to this memory -system.physmem.bytes_written::total 152669504 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 601861897 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 114514042 # Number of read requests responded to by this memory -system.physmem.num_reads::total 716375939 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 39451321 # Number of write requests responded to by this memory -system.physmem.num_writes::total 39451321 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999999747 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1247938539 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9247938286 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999999747 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999999747 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 507324022 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 507324022 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999999747 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1755262561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9755262308 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9755262308 # Throughput (bytes/s) -system.membus.data_through_bus 2935660432 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114514042 # DTB read hits -system.cpu.dtb.read_misses 2631 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114516673 # DTB read accesses -system.cpu.dtb.write_hits 39451321 # DTB write hits -system.cpu.dtb.write_misses 2302 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39453623 # DTB write accesses -system.cpu.dtb.data_hits 153965363 # DTB hits -system.cpu.dtb.data_misses 4933 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 153970296 # DTB accesses -system.cpu.itb.fetch_hits 601861897 # ITB hits -system.cpu.itb.fetch_misses 20 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 601861917 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 601861917 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 601856964 # Number of instructions committed -system.cpu.committedOps 601856964 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses -system.cpu.num_func_calls 2395217 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls -system.cpu.num_int_insts 563959696 # number of integer instructions -system.cpu.num_fp_insts 1520 # number of float instructions -system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read -system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written -system.cpu.num_fp_register_reads 169 # number of times the floating registers were read -system.cpu.num_fp_register_writes 42 # number of times the floating registers were written -system.cpu.num_mem_refs 153970296 # number of memory refs -system.cpu.num_load_insts 114516673 # Number of load instructions -system.cpu.num_store_insts 39453623 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 601861917 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles - ----------- End Simulation Statistics ---------- diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,196 +0,0 @@ -[root] -type=Root -children=system -full_system=false -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -boot_osflags=a -clock=1000 -init_param=0 -kernel= -load_addr_mask=1099511627775 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clock=500 -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=262144 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.icache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=131072 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.interrupts] -type=AlphaInterrupts - -[system.cpu.isa] -type=AlphaISA - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.l2cache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -size=2097152 -system=system -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.toL2Bus] -type=CoherentBus -block_size=64 -clock=500 -header_cycles=1 -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1000 -conf_table_reported=false -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.master[0] - diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,44 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 14:50:54 -gem5 executing on ribera.cs.wisc.edu -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 762403375000 because target called exit() diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,445 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.762403 # Number of seconds simulated -sim_ticks 762403375000 # Number of ticks simulated -final_tick 762403375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1417339 # Simulator instruction rate (inst/s) -host_op_rate 1417339 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1795416637 # Simulator tick rate (ticks/s) -host_mem_usage 225056 # Number of bytes of host memory used -host_seconds 424.64 # Real time elapsed on the host -sim_insts 601856964 # Number of instructions simulated -sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1628864 # Number of bytes read from this memory -system.physmem.bytes_read::total 1678976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 64384 # Number of bytes written to this memory -system.physmem.bytes_written::total 64384 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25451 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26234 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1006 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1006 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 65729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2136486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2202215 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 65729 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 65729 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 84449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 84449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 84449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 65729 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2136486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2286664 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 2286664 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4910 # Transaction distribution -system.membus.trans_dist::ReadResp 4910 # Transaction distribution -system.membus.trans_dist::Writeback 1006 # Transaction distribution -system.membus.trans_dist::ReadExReq 21324 # Transaction distribution -system.membus.trans_dist::ReadExResp 21324 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 53474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 53474 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1743360 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 1743360 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1743360 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 35288000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 236106000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114514042 # DTB read hits -system.cpu.dtb.read_misses 2631 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114516673 # DTB read accesses -system.cpu.dtb.write_hits 39451321 # DTB write hits -system.cpu.dtb.write_misses 2302 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39453623 # DTB write accesses -system.cpu.dtb.data_hits 153965363 # DTB hits -system.cpu.dtb.data_misses 4933 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 153970296 # DTB accesses -system.cpu.itb.fetch_hits 601861898 # ITB hits -system.cpu.itb.fetch_misses 20 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 601861918 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 1524806750 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 601856964 # Number of instructions committed -system.cpu.committedOps 601856964 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses -system.cpu.num_func_calls 2395217 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls -system.cpu.num_int_insts 563959696 # number of integer instructions -system.cpu.num_fp_insts 1520 # number of float instructions -system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read -system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written -system.cpu.num_fp_register_reads 169 # number of times the floating registers were read -system.cpu.num_fp_register_writes 42 # number of times the floating registers were written -system.cpu.num_mem_refs 153970296 # number of memory refs -system.cpu.num_load_insts 114516673 # Number of load instructions -system.cpu.num_store_insts 39453623 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1524806750 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 673.381157 # Cycle average of tags in use -system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 673.381157 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.328799 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.328799 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 601861103 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 601861103 # number of overall hits -system.cpu.icache.overall_hits::total 601861103 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 795 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 795 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 795 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses -system.cpu.icache.overall_misses::total 795 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 43222000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 43222000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 43222000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 43222000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 43222000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 43222000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 601861898 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 601861898 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 601861898 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54367.295597 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54367.295597 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54367.295597 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54367.295597 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54367.295597 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54367.295597 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 795 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 795 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41632000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 41632000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41632000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 41632000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41632000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 41632000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52367.295597 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52367.295597 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52367.295597 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52367.295597 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52367.295597 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52367.295597 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1028 # number of replacements -system.cpu.l2cache.tagsinuse 22854.086849 # Cycle average of tags in use -system.cpu.l2cache.total_refs 531883 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23221 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.905258 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21662.155591 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 666.530347 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 525.400911 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.661077 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.020341 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016034 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.697451 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 197105 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 197117 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 436887 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 436887 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 232839 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 232839 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 429944 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 429956 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 429944 # number of overall hits -system.cpu.l2cache.overall_hits::total 429956 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 783 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4127 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4910 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21324 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21324 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 783 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 25451 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 26234 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 783 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 25451 # number of overall misses -system.cpu.l2cache.overall_misses::total 26234 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40717000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214610000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 255327000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1108848000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1108848000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 40717000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1323458000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1364175000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 40717000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1323458000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1364175000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 795 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 201232 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 202027 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 436887 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 436887 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254163 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254163 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 795 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 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# average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.266829 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52001.277139 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.235747 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.266829 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1006 # number of writebacks -system.cpu.l2cache.writebacks::total 1006 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 783 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4127 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4910 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21324 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21324 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 783 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 25451 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 26234 # number of demand (read+write) MSHR misses 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cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1049367000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31321000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1018046000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1049367000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020509 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024304 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083899 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083899 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055888 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.057507 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055888 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.057507 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.277139 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40001.453841 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.425662 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.277139 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.235747 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.266829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.277139 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.235747 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.266829 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.203488 # Cycle average of tags in use -system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 563363000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.203488 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999561 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999561 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 39197158 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 153509968 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 153509968 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 153509968 # number of overall hits -system.cpu.dcache.overall_hits::total 153509968 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 201232 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 201232 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 254163 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 254163 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 455395 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses -system.cpu.dcache.overall_misses::total 455395 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2789356000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2789356000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4199727000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4199727000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6989083000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6989083000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6989083000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6989083000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001757 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001757 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006442 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006442 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13861.393814 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13861.393814 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16523.754441 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16523.754441 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15347.298499 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15347.298499 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks -system.cpu.dcache.writebacks::total 436887 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386892000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386892000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3691401000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3691401000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6078293000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6078293000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6078293000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6078293000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11861.393814 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11861.393814 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14523.754441 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14523.754441 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 74969406 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 202027 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 202027 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 436887 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 254163 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 254163 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1590 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1347677 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 1349267 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 57106048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 57156928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 57156928 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 883425500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1192500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 683092500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,581 +0,0 @@ -[root] -type=Root -children=system -full_system=false -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -boot_osflags=a -clock=1000 -init_param=0 -kernel= -load_addr_mask=1099511627775 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clock=500 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbDepth=1 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=BranchPredictor -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -instShiftAmt=2 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -predType=tournament - -[system.cpu.dcache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=262144 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dtb] -type=ArmTLB -children=walker -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clock=500 -num_squash_per_cycle=2 -sys=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -issueLat=1 -opClass=SimdAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -issueLat=1 -opClass=SimdAddAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -issueLat=1 -opClass=SimdAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -issueLat=1 -opClass=SimdCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -issueLat=1 -opClass=SimdCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -issueLat=1 -opClass=SimdMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -issueLat=1 -opClass=SimdMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -issueLat=1 -opClass=SimdMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -issueLat=1 -opClass=SimdShift -opLat=1 - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -issueLat=1 -opClass=SimdShiftAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -issueLat=1 -opClass=SimdSqrt -opLat=1 - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -issueLat=1 -opClass=SimdFloatAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -issueLat=1 -opClass=SimdFloatAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -issueLat=1 -opClass=SimdFloatCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -issueLat=1 -opClass=SimdFloatCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -issueLat=1 -opClass=SimdFloatDiv -opLat=1 - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -issueLat=1 -opClass=SimdFloatMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -issueLat=1 -opClass=SimdFloatMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -issueLat=1 -opClass=SimdFloatMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -issueLat=1 -opClass=SimdFloatSqrt -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=131072 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.interrupts] -type=ArmInterrupts - -[system.cpu.isa] -type=ArmISA -fpsid=1090793632 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=3 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=4027589137 -id_pfr0=49 -id_pfr1=1 -midr=890224640 - -[system.cpu.itb] -type=ArmTLB -children=walker -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clock=500 -num_squash_per_cycle=2 -sys=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -size=2097152 -system=system -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.toL2Bus] -type=CoherentBus -block_size=64 -clock=500 -header_cycles=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleDRAM -activation_limit=4 -addr_mapping=openmap -banks_per_rank=8 -channels=1 -clock=1000 -conf_table_reported=false -in_addr_map=true -lines_per_rowbuffer=32 -mem_sched_policy=frfcfs -null=false -page_policy=open -range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -tBURST=5000 -tCL=13750 -tRCD=13750 -tREFI=7800000 -tRFC=300000 -tRP=13750 -tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_thresh_perc=70 -zero=false -port=system.membus.master[0] - diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,43 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Mar 26 2013 15:15:23 -gem5 started Mar 27 2013 01:22:50 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 164562530500 because target called exit() diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,969 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.164713 # Number of seconds simulated -sim_ticks 164712962000 # Number of ticks simulated -final_tick 164712962000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104948 # Simulator instruction rate (inst/s) -host_op_rate 110896 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30324199 # Simulator tick rate (ticks/s) -host_mem_usage 246328 # Number of bytes of host memory used -host_seconds 5431.73 # Real time elapsed on the host -sim_insts 570051585 # Number of instructions simulated -sim_ops 602359791 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 46464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1701696 # Number of bytes read from this memory -system.physmem.bytes_read::total 1748160 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 46464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 46464 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162432 # Number of bytes written to this memory -system.physmem.bytes_written::total 162432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 726 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26589 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27315 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2538 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2538 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 282091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10331282 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10613372 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 282091 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 282091 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 986152 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 986152 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 986152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 282091 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10331282 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11599524 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27316 # Total number of read requests seen -system.physmem.writeReqs 2538 # Total number of write requests seen -system.physmem.cpureqs 29854 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1748160 # Total number of bytes read from memory -system.physmem.bytesWritten 162432 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1748160 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162432 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1620 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1739 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1816 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1711 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1787 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1655 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1639 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1650 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1674 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1648 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 166 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 164 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 163 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 163 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 153 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 158 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 164712945000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27316 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 2538 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8427 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 9344 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 203.958904 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 86.292433 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 804.447838 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 7841 83.91% 83.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 319 3.41% 87.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 187 2.00% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 84 0.90% 90.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 64 0.68% 90.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 69 0.74% 91.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 59 0.63% 92.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 495 5.30% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 4 0.04% 97.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 6 0.06% 97.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2 0.02% 97.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 4 0.04% 97.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 5 0.05% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 3 0.03% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.05% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 7 0.07% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 6 0.06% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 7 0.07% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 5 0.05% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.03% 98.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.03% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 1 0.01% 98.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 2 0.02% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.03% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.04% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.01% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.02% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.02% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 4 0.04% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 2 0.02% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.01% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 1 0.01% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 4 0.04% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.01% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.01% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.02% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.01% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.01% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.01% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 2 0.02% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 6 0.06% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 1 0.01% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 3 0.03% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.01% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 4 0.04% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.01% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 5 0.05% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.01% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 6 0.06% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.01% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 4 0.04% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 2 0.02% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 1 0.01% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 1 0.01% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 4 0.04% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.01% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 1 0.01% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 1 0.01% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 2 0.02% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 4 0.04% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 4 0.04% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 1 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 5 0.05% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 1 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 3 0.03% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.02% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 60 0.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 9344 # Bytes accessed per row activation -system.physmem.totQLat 713159750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1418769750 # Sum of mem lat for all requests -system.physmem.totBusLat 136580000 # Total cycles spent in databus access -system.physmem.totBankLat 569030000 # Total cycles spent in bank access -system.physmem.avgQLat 26107.77 # Average queueing delay per request -system.physmem.avgBankLat 20831.38 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 51939.15 # Average memory access latency -system.physmem.avgRdBW 10.61 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 10.61 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.99 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.09 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 6.37 # Average write queue length over time -system.physmem.readRowHits 18602 # Number of row buffer hits during reads -system.physmem.writeRowHits 1900 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.10 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.86 # Row buffer hit rate for writes -system.physmem.avgGap 5517282.27 # Average gap between requests -system.membus.throughput 11599524 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 5525 # Transaction distribution -system.membus.trans_dist::ReadResp 5524 # Transaction distribution -system.membus.trans_dist::Writeback 2538 # Transaction distribution -system.membus.trans_dist::ReadExReq 21791 # Transaction distribution -system.membus.trans_dist::ReadExResp 21791 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 57169 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 57169 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1910592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 1910592 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1910592 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 57108500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 253687250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu.branchPred.lookups 85141664 # Number of BP lookups -system.cpu.branchPred.condPredicted 79926089 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2339895 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 47171599 # Number of BTB lookups -system.cpu.branchPred.BTBHits 46874379 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.369917 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1426656 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 967 # Number of incorrect RAS predictions. -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 329425925 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 68487406 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 666825489 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85141664 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48301035 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 129620742 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13092220 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119393546 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 197 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 67071685 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 754180 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 328226263 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.164959 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.193799 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 198605759 60.51% 60.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20910392 6.37% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4965000 1.51% 68.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14344867 4.37% 72.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8890127 2.71% 75.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9445559 2.88% 78.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4398270 1.34% 79.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5786671 1.76% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 60879618 18.55% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 328226263 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258455 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.024205 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 92944994 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96252525 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 107931979 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20373876 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10722889 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4735185 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1545 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 703231181 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5882 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10722889 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107145742 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14457552 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 41262 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114028439 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81830379 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 694801887 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 62 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59342385 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20345082 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 637 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 721273666 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3230487326 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3230487198 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627417373 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 93856293 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1652 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1599 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 170596161 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172196764 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80465721 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21514150 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28584655 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 679971897 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2875 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 645597882 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1369415 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 77434544 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 193173185 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 171 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 328226263 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.966929 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.726463 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68204804 20.78% 20.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85458675 26.04% 46.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75776963 23.09% 69.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40830036 12.44% 82.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28801200 8.77% 91.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14906617 4.54% 95.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5593532 1.70% 97.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6439392 1.96% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2215044 0.67% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 328226263 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 217054 5.76% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2693414 71.46% 77.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 858913 22.79% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403366911 62.48% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6571 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 165560670 25.64% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76663727 11.87% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 645597882 # Type of FU issued -system.cpu.iq.rate 1.959766 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3769381 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005839 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1624560787 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 757421551 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 637562005 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 649367243 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30370600 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23244171 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 124258 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12468 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10244708 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12865 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 36070 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10722889 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 827692 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 90632 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 679977792 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 687305 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172196764 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80465721 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1547 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 33202 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14561 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12468 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1356677 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1459783 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2816460 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 641522595 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163491941 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4075287 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3020 # number of nop insts executed -system.cpu.iew.exec_refs 239384720 # number of memory reference insts executed -system.cpu.iew.exec_branches 74670290 # Number of branches executed -system.cpu.iew.exec_stores 75892779 # Number of stores executed -system.cpu.iew.exec_rate 1.947396 # Inst execution rate -system.cpu.iew.wb_sent 638967921 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 637562021 # cumulative count of insts written-back -system.cpu.iew.wb_producers 418575369 # num instructions producing a value -system.cpu.iew.wb_consumers 649883888 # num instructions consuming a value -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.935373 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.644077 # average fanout of values written-back -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 77626317 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2704 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2338430 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 317503374 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.897176 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.237290 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93293822 29.38% 29.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104353243 32.87% 62.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42983974 13.54% 75.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8800031 2.77% 78.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25934980 8.17% 86.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12922444 4.07% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7630865 2.40% 93.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1170892 0.37% 93.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20413123 6.43% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 317503374 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570051636 # Number of instructions committed -system.cpu.commit.committedOps 602359842 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219173606 # Number of memory references committed -system.cpu.commit.loads 148952593 # Number of loads committed -system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70892524 # Number of branches committed -system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533522631 # Number of committed integer instructions. -system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20413123 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 977075798 # The number of ROB reads -system.cpu.rob.rob_writes 1370727069 # The number of ROB writes -system.cpu.timesIdled 46745 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1199662 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570051585 # Number of Instructions Simulated -system.cpu.committedOps 602359791 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570051585 # Number of Instructions Simulated -system.cpu.cpi 0.577888 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.577888 # CPI: Total CPI of All Threads -system.cpu.ipc 1.730439 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.730439 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3204357066 # number of integer regfile reads -system.cpu.int_regfile_writes 663034873 # number of integer regfile writes -system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 234776508 # number of misc regfile reads -system.cpu.misc_regfile_writes 2656 # number of misc regfile writes -system.cpu.toL2Bus.throughput 336905701 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 198323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 198321 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 421595 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247158 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247158 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1310948 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 1312556 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 55441280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 55492672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 55492672 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 855133500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1348998 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 672658492 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.replacements 51 # number of replacements -system.cpu.icache.tagsinuse 684.674146 # Cycle average of tags in use -system.cpu.icache.total_refs 67070538 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 803 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 83524.953923 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 684.674146 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.334314 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.334314 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67070538 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67070538 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67070538 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67070538 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67070538 # number of overall hits -system.cpu.icache.overall_hits::total 67070538 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1147 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1147 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1147 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1147 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1147 # number of overall misses -system.cpu.icache.overall_misses::total 1147 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 71258997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 71258997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 71258997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 71258997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 71258997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 71258997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67071685 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67071685 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67071685 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67071685 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67071685 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67071685 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62126.414124 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62126.414124 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62126.414124 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62126.414124 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62126.414124 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62126.414124 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 458 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57.250000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 342 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 342 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 342 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 342 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 342 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 342 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 805 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 805 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 805 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 805 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 805 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 805 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52105751 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 52105751 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52105751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 52105751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52105751 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 52105751 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64727.640994 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64727.640994 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64727.640994 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 64727.640994 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64727.640994 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 64727.640994 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2560 # number of replacements -system.cpu.l2cache.tagsinuse 22349.425115 # Cycle average of tags in use -system.cpu.l2cache.total_refs 517369 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24160 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.414280 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20751.919158 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 642.855977 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 954.649980 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633298 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.019618 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.029134 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.682050 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 77 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 192711 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 192788 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 421595 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 421595 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 225367 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 225367 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 77 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 418078 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 418155 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 77 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 418078 # number of overall hits -system.cpu.l2cache.overall_hits::total 418155 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 727 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4807 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5534 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21791 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21791 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 727 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26598 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27325 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 727 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26598 # number of overall misses -system.cpu.l2cache.overall_misses::total 27325 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50524000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 713564500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 764088500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1840836750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1840836750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 50524000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2554401250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2604925250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 50524000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2554401250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2604925250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 804 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 197518 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 198322 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 421595 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 421595 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247158 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247158 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 804 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 444676 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 445480 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 804 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 444676 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 445480 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.904229 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024337 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.027904 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088166 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.088166 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.904229 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.059814 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.061338 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.904229 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.059814 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.061338 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69496.561210 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 148442.791762 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 138071.647994 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84476.928548 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84476.928548 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69496.561210 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96037.343033 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 95331.207685 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69496.561210 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96037.343033 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 95331.207685 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2538 # number of writebacks -system.cpu.l2cache.writebacks::total 2538 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 726 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4799 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5525 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21791 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21791 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 726 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26590 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27316 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 726 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26590 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27316 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41290000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 653067500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 694357500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1568513750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1568513750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41290000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2221581250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2262871250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41290000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2221581250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2262871250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.902985 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024297 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027859 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088166 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088166 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.902985 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059796 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.061318 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.902985 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059796 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.061318 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56873.278237 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 136084.080017 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125675.565611 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71979.888486 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71979.888486 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56873.278237 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83549.501692 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82840.505565 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56873.278237 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83549.501692 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82840.505565 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 440579 # number of replacements -system.cpu.dcache.tagsinuse 4091.388618 # Cycle average of tags in use -system.cpu.dcache.total_refs 197559015 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 444675 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 444.277315 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 319919250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4091.388618 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998874 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998874 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 131516152 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 131516152 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 66040207 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 66040207 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 197556359 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 197556359 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 197556359 # number of overall hits -system.cpu.dcache.overall_hits::total 197556359 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 341735 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 341735 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3377324 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3377324 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 20 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 20 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3719059 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3719059 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3719059 # number of overall misses -system.cpu.dcache.overall_misses::total 3719059 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5122452734 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5122452734 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 44273793674 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 44273793674 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 356000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 356000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 49396246408 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 49396246408 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 49396246408 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 49396246408 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 131857887 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 131857887 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1347 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1347 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201275418 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201275418 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201275418 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201275418 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002592 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002592 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048652 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.048652 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.014848 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.014848 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018477 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018477 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018477 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018477 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14989.546678 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14989.546678 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13109.134236 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 13109.134236 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17800 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17800 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13281.920617 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13281.920617 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13281.920617 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13281.920617 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 146707 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 200 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5405 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.142831 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 421595 # number of writebacks -system.cpu.dcache.writebacks::total 421595 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144216 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 144216 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3130166 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3130166 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 20 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 20 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3274382 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3274382 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3274382 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3274382 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197519 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197519 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247158 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247158 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 444677 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 444677 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 444677 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 444677 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2858837258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2858837258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4350262234 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4350262234 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7209099492 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7209099492 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7209099492 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7209099492 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14473.732947 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14473.732947 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17601.138681 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17601.138681 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16211.990933 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16211.990933 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16211.990933 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16211.990933 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,156 +0,0 @@ -[root] -type=Root -children=system -full_system=false -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -boot_osflags=a -clock=1000 -init_param=0 -kernel= -load_addr_mask=1099511627775 -mem_mode=atomic -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clock=500 -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simulate_data_stalls=false -simulate_inst_stalls=false -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=ArmTLB -children=walker -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clock=500 -num_squash_per_cycle=2 -sys=system -port=system.membus.slave[4] - -[system.cpu.interrupts] -type=ArmInterrupts - -[system.cpu.isa] -type=ArmISA -fpsid=1090793632 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=3 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=4027589137 -id_pfr0=49 -id_pfr1=1 -midr=890224640 - -[system.cpu.itb] -type=ArmTLB -children=walker -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clock=500 -num_squash_per_cycle=2 -sys=system -port=system.membus.slave[3] - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -egid=100 -env= -errout=cerr -euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1000 -conf_table_reported=false -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.master[0] - diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,43 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic/simout -Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 19:49:37 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 301191365000 because target called exit() diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,105 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.301191 # Number of seconds simulated -sim_ticks 301191365000 # Number of ticks simulated -final_tick 301191365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1664644 # Simulator instruction rate (inst/s) -host_op_rate 1758990 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 879528148 # Simulator tick rate (ticks/s) -host_mem_usage 233480 # Number of bytes of host memory used -host_seconds 342.45 # Real time elapsed on the host -sim_insts 570051636 # Number of instructions simulated -sim_ops 602359842 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 2280298100 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 399862020 # Number of bytes read from this memory -system.physmem.bytes_read::total 2680160120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2280298100 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2280298100 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 236359611 # Number of bytes written to this memory -system.physmem.bytes_written::total 236359611 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 570074525 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147793178 # Number of read requests responded to by this memory -system.physmem.num_reads::total 717867703 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 69418858 # Number of write requests responded to by this memory -system.physmem.num_writes::total 69418858 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7570927872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1327601208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8898529080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7570927872 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7570927872 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 784748962 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 784748962 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7570927872 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2112350170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9683278042 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9683278042 # Throughput (bytes/s) -system.membus.data_through_bus 2916519731 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 602382731 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 570051636 # Number of instructions committed -system.cpu.committedOps 602359842 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 533522631 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 1995305 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 67050634 # number of instructions that are conditional controls -system.cpu.num_int_insts 533522631 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 2770242967 # number of times the integer registers were read -system.cpu.num_int_register_writes 614470972 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 219173606 # number of memory refs -system.cpu.num_load_insts 148952593 # Number of load instructions -system.cpu.num_store_insts 70221013 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 602382731 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles - ----------- End Simulation Statistics ---------- diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,228 +0,0 @@ -[root] -type=Root -children=system -full_system=false -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -boot_osflags=a -clock=1000 -init_param=0 -kernel= -load_addr_mask=1099511627775 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clock=500 -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=262144 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dtb] -type=ArmTLB -children=walker -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clock=500 -num_squash_per_cycle=2 -sys=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.icache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=131072 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.interrupts] -type=ArmInterrupts - -[system.cpu.isa] -type=ArmISA -fpsid=1090793632 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=3 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=4027589137 -id_pfr0=49 -id_pfr1=1 -midr=890224640 - -[system.cpu.itb] -type=ArmTLB -children=walker -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clock=500 -num_squash_per_cycle=2 -sys=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -size=2097152 -system=system -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.toL2Bus] -type=CoherentBus -block_size=64 -clock=500 -header_cycles=1 -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1000 -conf_table_reported=false -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.master[0] - diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,43 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 19:54:17 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 793670137000 because target called exit() diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,463 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.793670 # Number of seconds simulated -sim_ticks 793670137000 # Number of ticks simulated -final_tick 793670137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 583678 # Simulator instruction rate (inst/s) -host_op_rate 616385 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 814802699 # Simulator tick rate (ticks/s) -host_mem_usage 241980 # Number of bytes of host memory used -host_seconds 974.06 # Real time elapsed on the host -sim_insts 568539335 # Number of instructions simulated -sim_ops 600398272 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 38592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1675072 # Number of bytes read from this memory -system.physmem.bytes_read::total 1713664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 38592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 38592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 159552 # Number of bytes written to this memory -system.physmem.bytes_written::total 159552 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 603 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26173 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26776 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2493 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2493 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 48625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2110539 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2159164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 48625 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 48625 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 201031 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 201031 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 201031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 48625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2110539 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2360195 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 2360195 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4941 # Transaction distribution -system.membus.trans_dist::ReadResp 4941 # Transaction distribution -system.membus.trans_dist::Writeback 2493 # Transaction distribution -system.membus.trans_dist::ReadExReq 21835 # Transaction distribution -system.membus.trans_dist::ReadExResp 21835 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 56045 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 56045 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1873216 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 1873216 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1873216 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 49213000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 240984000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1587340274 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 568539335 # Number of instructions committed -system.cpu.committedOps 600398272 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 533522631 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 1995305 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 67050634 # number of instructions that are conditional controls -system.cpu.num_int_insts 533522631 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 3212467067 # number of times the integer registers were read -system.cpu.num_int_register_writes 614470972 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 219173606 # number of memory refs -system.cpu.num_load_insts 148952593 # Number of load instructions -system.cpu.num_store_insts 70221013 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1587340274 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 12 # number of replacements -system.cpu.icache.tagsinuse 577.773656 # Cycle average of tags in use -system.cpu.icache.total_refs 570073883 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 886584.576983 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 577.773656 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.282116 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.282116 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 570073883 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 570073883 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 570073883 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 570073883 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 570073883 # number of overall hits -system.cpu.icache.overall_hits::total 570073883 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 643 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 643 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 643 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses -system.cpu.icache.overall_misses::total 643 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 33685000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 33685000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 33685000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 33685000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 33685000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 33685000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 570074526 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 570074526 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 570074526 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 570074526 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 570074526 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 570074526 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52387.247278 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52387.247278 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52387.247278 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52387.247278 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52387.247278 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52387.247278 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 643 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 643 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 643 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32399000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32399000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32399000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32399000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32399000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32399000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50387.247278 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50387.247278 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50387.247278 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50387.247278 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50387.247278 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50387.247278 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2512 # number of replacements -system.cpu.l2cache.tagsinuse 22024.775302 # Cycle average of tags in use -system.cpu.l2cache.total_refs 506990 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23599 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.483537 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20978.651717 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 539.196236 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 506.927350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.640218 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.016455 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.015470 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.672143 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 40 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 185478 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 185518 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 418626 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 418626 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 225913 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 225913 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 40 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 411391 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 411431 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 40 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 411391 # number of overall hits -system.cpu.l2cache.overall_hits::total 411431 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 603 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4338 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4941 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21835 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21835 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 603 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26173 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 26776 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 603 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26173 # number of overall misses -system.cpu.l2cache.overall_misses::total 26776 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31356000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 226076000 # number of ReadReq miss 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-system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 418626 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 418626 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 643 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 437564 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 438207 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 643 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 437564 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.937792 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022854 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.025943 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088134 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.088134 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.937792 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.059815 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.061104 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.937792 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.059815 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.061104 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52115.260489 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52101.194090 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52019.103656 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52018.673439 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52019.103656 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52018.673439 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2493 # number of writebacks -system.cpu.l2cache.writebacks::total 2493 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 603 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4338 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4941 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21835 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21835 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 603 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 26776 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 603 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26173 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26776 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 174020000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198140000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 873400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 873400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1047420000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1071540000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1047420000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1071540000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022854 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.025943 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088134 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088134 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059815 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.061104 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059815 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.061104 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40115.260489 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40101.194090 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40019.103656 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40018.673439 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40019.103656 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40018.673439 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 433468 # number of replacements -system.cpu.dcache.tagsinuse 4094.241219 # Cycle average of tags in use -system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 529622000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.241219 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999571 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999571 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 216771818 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 216771818 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 216771818 # number of overall hits -system.cpu.dcache.overall_hits::total 216771818 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 247748 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 437564 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses -system.cpu.dcache.overall_misses::total 437564 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2650304000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2650304000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4137794000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4137794000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6788098000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6788098000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6788098000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6788098000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 217209382 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 217209382 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 217209382 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 217209382 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003569 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13962.489990 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13962.489990 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16701.624231 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16701.624231 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15513.383185 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15513.383185 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 418626 # number of writebacks -system.cpu.dcache.writebacks::total 418626 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 437564 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2270672000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2270672000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3642298000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3642298000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5912970000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5912970000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5912970000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5912970000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003569 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11962.489990 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11962.489990 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14701.624231 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14701.624231 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 69093329 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 190459 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 190459 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 418626 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247748 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247748 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1286 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1293754 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 1295040 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 41152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 54796160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 54837312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 54837312 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 847042500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 964500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 656346000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,549 +0,0 @@ -[root] -type=Root -children=system -full_system=false -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -boot_osflags=a -clock=1000 -init_param=0 -kernel= -load_addr_mask=1099511627775 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clock=500 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbDepth=1 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=BranchPredictor -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -instShiftAmt=2 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -predType=tournament - -[system.cpu.dcache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=262144 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dtb] -type=SparcTLB -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -issueLat=1 -opClass=SimdAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -issueLat=1 -opClass=SimdAddAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -issueLat=1 -opClass=SimdAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -issueLat=1 -opClass=SimdCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -issueLat=1 -opClass=SimdCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -issueLat=1 -opClass=SimdMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -issueLat=1 -opClass=SimdMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -issueLat=1 -opClass=SimdMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -issueLat=1 -opClass=SimdShift -opLat=1 - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -issueLat=1 -opClass=SimdShiftAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -issueLat=1 -opClass=SimdSqrt -opLat=1 - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -issueLat=1 -opClass=SimdFloatAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -issueLat=1 -opClass=SimdFloatAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -issueLat=1 -opClass=SimdFloatCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -issueLat=1 -opClass=SimdFloatCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -issueLat=1 -opClass=SimdFloatDiv -opLat=1 - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -issueLat=1 -opClass=SimdFloatMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -issueLat=1 -opClass=SimdFloatMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -issueLat=1 -opClass=SimdFloatMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -issueLat=1 -opClass=SimdFloatSqrt -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=131072 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.interrupts] -type=SparcInterrupts - -[system.cpu.isa] -type=SparcISA - -[system.cpu.itb] -type=SparcTLB -size=64 - -[system.cpu.l2cache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -size=2097152 -system=system -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.toL2Bus] -type=CoherentBus -block_size=64 -clock=500 -header_cycles=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleDRAM -activation_limit=4 -addr_mapping=openmap -banks_per_rank=8 -channels=1 -clock=1000 -conf_table_reported=false -in_addr_map=true -lines_per_rowbuffer=32 -mem_sched_policy=frfcfs -null=false -page_policy=open -range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -tBURST=5000 -tCL=13750 -tRCD=13750 -tREFI=7800000 -tRFC=300000 -tRP=13750 -tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_thresh_perc=70 -zero=false -port=system.membus.master[0] - diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,43 +0,0 @@ -Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simout -Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Mar 26 2013 15:04:14 -gem5 started Mar 26 2013 23:39:12 -gem5 executing on ribera.cs.wisc.edu -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 387290918500 because target called exit() diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,912 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.387415 # Number of seconds simulated -sim_ticks 387415034000 # Number of ticks simulated -final_tick 387415034000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145899 # Simulator instruction rate (inst/s) -host_op_rate 146358 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40339574 # Simulator tick rate (ticks/s) -host_mem_usage 236680 # Number of bytes of host memory used -host_seconds 9603.85 # Real time elapsed on the host -sim_insts 1401188945 # Number of instructions simulated -sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 76672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1678848 # Number of bytes read from this memory -system.physmem.bytes_read::total 1755520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 76672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 76672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory -system.physmem.bytes_written::total 162112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1198 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26232 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27430 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 197907 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4333461 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4531368 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197907 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197907 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 418445 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 418445 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 418445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4333461 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4949813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27431 # Total number of read requests seen -system.physmem.writeReqs 2533 # Total number of write requests seen -system.physmem.cpureqs 29964 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1755520 # Total number of bytes read from memory -system.physmem.bytesWritten 162112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1755520 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1887 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1775 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1646 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1602 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1689 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1531 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1534 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1703 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1803 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 168 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 163 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 168 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 148 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 163 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 163 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 162 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 387415006000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27431 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 2533 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 12673 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9088 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 9402 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 203.721761 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 84.987136 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 819.365596 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 8101 86.16% 86.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 134 1.43% 87.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 96 1.02% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 112 1.19% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 136 1.45% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 51 0.54% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 54 0.57% 92.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 494 5.25% 97.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 7 0.07% 97.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 7 0.07% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 7 0.07% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 6 0.06% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 5 0.05% 97.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 4 0.04% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 4 0.04% 98.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 4 0.04% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 2 0.02% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1 0.01% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 5 0.05% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.02% 98.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 4 0.04% 98.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3 0.03% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 2 0.02% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 1 0.01% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 1 0.01% 98.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.01% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.01% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.02% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 4 0.04% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.01% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.03% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.04% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.01% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 6 0.06% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.02% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.02% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 2 0.02% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.01% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.01% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.01% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 5 0.05% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.01% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.01% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.01% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 3 0.03% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 1 0.01% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.01% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 3 0.03% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.02% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 2 0.02% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.01% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 3 0.03% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.01% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 3 0.03% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 1 0.01% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 5 0.05% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 1 0.01% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 3 0.03% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 1 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 4 0.04% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 2 0.02% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 3 0.03% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 2 0.02% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 3 0.03% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 2 0.02% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 3 0.03% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 3 0.03% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 63 0.67% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 9402 # Bytes accessed per row activation -system.physmem.totQLat 539179750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1243632250 # Sum of mem lat for all requests -system.physmem.totBusLat 137155000 # Total cycles spent in databus access -system.physmem.totBankLat 567297500 # Total cycles spent in bank access -system.physmem.avgQLat 19655.85 # Average queueing delay per request -system.physmem.avgBankLat 20680.89 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 45336.74 # Average memory access latency -system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.42 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 17.34 # Average write queue length over time -system.physmem.readRowHits 18652 # Number of row buffer hits during reads -system.physmem.writeRowHits 1907 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.00 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.29 # Row buffer hit rate for writes -system.physmem.avgGap 12929348.75 # Average gap between requests -system.membus.throughput 4949813 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 5644 # Transaction distribution -system.membus.trans_dist::ReadResp 5643 # Transaction distribution -system.membus.trans_dist::Writeback 2533 # Transaction distribution -system.membus.trans_dist::ReadExReq 21787 # Transaction distribution -system.membus.trans_dist::ReadExResp 21787 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 57394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 57394 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1917632 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 1917632 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1917632 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 57898500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 257934750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 97771801 # Number of BP lookups -system.cpu.branchPred.condPredicted 88057721 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 3615316 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 65798916 # Number of BTB lookups -system.cpu.branchPred.BTBHits 65497220 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.541488 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1341 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 221 # Number of incorrect RAS predictions. -system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 774830069 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 164883952 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1642301632 # Number of instructions fetch has processed -system.cpu.fetch.Branches 97771801 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65498561 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 329236521 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20847739 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 263430821 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 68 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2732 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 161954673 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 734638 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 774548250 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.126550 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146630 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 445311729 57.49% 57.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74064439 9.56% 67.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37899210 4.89% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9077798 1.17% 73.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28111025 3.63% 76.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18777465 2.42% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11484121 1.48% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3796587 0.49% 81.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146025876 18.85% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 774548250 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126185 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.119564 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 215910541 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214585029 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 284243922 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42814633 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16994125 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1636747683 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16994125 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 239768122 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36721831 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52506805 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302054014 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 126503353 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1625786842 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30929320 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73521723 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3138518 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1356521286 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2746703766 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2712258152 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34445614 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 111750847 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2644064 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2664096 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 271965509 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 437002127 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 179743092 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 254365369 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 82999925 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1512533952 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2609426 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1459379576 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 51760 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 109235461 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 130266400 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 365755 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 774548250 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.884169 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.431699 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 145788241 18.82% 18.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 184687370 23.84% 42.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 209616667 27.06% 69.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131230847 16.94% 86.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70744455 9.13% 95.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20395476 2.63% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7966025 1.03% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3938371 0.51% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 180798 0.02% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 774548250 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 114730 6.73% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 100027 5.86% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1171888 68.71% 81.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 318963 18.70% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 866432215 59.37% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2644892 0.18% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419180519 28.72% 88.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171121950 11.73% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1459379576 # Type of FU issued -system.cpu.iq.rate 1.883483 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1705608 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001169 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3677058920 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1615268004 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1443179578 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 18005850 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9348843 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8546661 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1451862484 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9222700 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215378532 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 34489284 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 58874 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 244564 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12894950 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3282 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 171174 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16994125 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3070480 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 244857 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1608828785 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4142124 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 437002127 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 179743092 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2526483 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 147400 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2643 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 244564 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2269789 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1473602 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3743391 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1454060396 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 416630693 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5319180 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 93685407 # number of nop insts executed -system.cpu.iew.exec_refs 587077597 # number of memory reference insts executed -system.cpu.iew.exec_branches 89037322 # Number of branches executed -system.cpu.iew.exec_stores 170446904 # Number of stores executed -system.cpu.iew.exec_rate 1.876618 # Inst execution rate -system.cpu.iew.wb_sent 1452605609 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1451726239 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1153377842 # num instructions producing a value -system.cpu.iew.wb_consumers 1204599911 # num instructions consuming a value -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.873606 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957478 # average fanout of values written-back -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119210092 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3615316 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 757554125 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.966227 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.509360 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 240131267 31.70% 31.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 275776990 36.40% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42576218 5.62% 73.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54724225 7.22% 80.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19710067 2.60% 83.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13290513 1.75% 85.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30567554 4.04% 89.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10495304 1.39% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70281987 9.28% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 757554125 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1485108088 # Number of instructions committed -system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 569360985 # Number of memory references committed -system.cpu.commit.loads 402512843 # Number of loads committed -system.cpu.commit.membars 51356 # Number of memory barriers committed -system.cpu.commit.branches 86248928 # Number of branches committed -system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. -system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70281987 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2295940642 # The number of ROB reads -system.cpu.rob.rob_writes 3234483516 # The number of ROB writes -system.cpu.timesIdled 26699 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 281819 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1401188945 # Number of Instructions Simulated -system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.552980 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.552980 # CPI: Total CPI of All Threads -system.cpu.ipc 1.808382 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.808382 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1979142490 # number of integer regfile reads -system.cpu.int_regfile_writes 1275129238 # number of integer regfile writes -system.cpu.fp_regfile_reads 16963238 # number of floating regfile reads -system.cpu.fp_regfile_writes 10492014 # number of floating regfile writes -system.cpu.misc_regfile_reads 592731236 # number of misc regfile reads -system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.toL2Bus.throughput 150040311 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 202084 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 202083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 443785 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 262380 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 262380 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2681 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1370031 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 1372712 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 85760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 58042112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 58127872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 58127872 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 897909500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2253250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 699110999 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu.icache.replacements 199 # number of replacements -system.cpu.icache.tagsinuse 1034.677399 # Cycle average of tags in use -system.cpu.icache.total_refs 161952681 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1340 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 120860.209701 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1034.677399 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505214 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505214 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161952681 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161952681 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161952681 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161952681 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161952681 # number of overall hits -system.cpu.icache.overall_hits::total 161952681 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1992 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1992 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1992 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1992 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1992 # number of overall misses -system.cpu.icache.overall_misses::total 1992 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 116472500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 116472500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 116472500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 116472500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 116472500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 116472500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 161954673 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 161954673 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 161954673 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 161954673 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 161954673 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 161954673 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58470.130522 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 58470.130522 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 58470.130522 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 58470.130522 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 58470.130522 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 58470.130522 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 213 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42.600000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 651 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 651 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 651 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 651 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 651 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 651 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1341 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1341 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1341 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1341 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1341 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1341 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 82823750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 82823750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 82823750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 82823750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 82823750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 82823750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61762.677107 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61762.677107 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1060.219571 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 652.004183 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.632859 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.032355 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019898 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.685112 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 142 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 196298 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 196440 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 443785 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 443785 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 240593 # 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miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.894109 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.056642 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.059059 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.894109 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.056642 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.059059 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66766.263553 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 107120.191226 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 98547.484054 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86582.973792 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86582.973792 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66766.263553 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90062.995578 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 89044.703073 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66766.263553 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90062.995578 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 89044.703073 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27431 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1199 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26232 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27431 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64873750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 420472750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 485346500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1612222250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1612222250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64873750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2032695000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2097568750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64873750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2032695000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2097568750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.894109 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022143 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027929 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083036 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083036 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.894109 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056642 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059059 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.894109 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056642 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.059059 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54106.547123 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 94594.544432 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 85993.355776 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73999.277092 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73999.277092 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54106.547123 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77489.135407 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76467.090153 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54106.547123 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77489.135407 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76467.090153 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459027 # number of replacements -system.cpu.dcache.tagsinuse 4093.682387 # Cycle average of tags in use -system.cpu.dcache.total_refs 365126830 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463123 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 788.401418 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 357487250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.682387 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999434 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999434 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 200169682 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200169682 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164955829 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164955829 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 365125511 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 365125511 # 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number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14590431499 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 34053628596 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 34053628596 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 142000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 142000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 48644060095 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 48644060095 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 48644060095 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 48644060095 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201059137 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201059137 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 367905953 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 367905953 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 367905953 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 367905953 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004424 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004424 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011334 # 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average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 20285.714286 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 20285.714286 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17495.081751 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17495.081751 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17495.081751 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17495.081751 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 687683 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 41 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 37439 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.368092 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 41 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 443785 # number of writebacks -system.cpu.dcache.writebacks::total 443785 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 688711 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 688711 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628615 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1628615 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2317326 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2317326 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2317326 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2317326 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200744 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200744 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262372 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262372 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 463116 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 463116 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 463116 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 463116 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2641921001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2641921001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4654554000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4654554000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 128000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 128000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7296475001 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7296475001 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7296475001 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7296475001 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000998 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001573 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13160.647397 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13160.647397 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17740.284786 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17740.284786 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 18285.714286 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 18285.714286 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15755.177971 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15755.177971 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15755.177971 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15755.177971 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,124 +0,0 @@ -[root] -type=Root -children=system -full_system=false -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -boot_osflags=a -clock=1000 -init_param=0 -kernel= -load_addr_mask=1099511627775 -mem_mode=atomic -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clock=500 -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simulate_data_stalls=false -simulate_inst_stalls=false -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=SparcTLB -size=64 - -[system.cpu.interrupts] -type=SparcInterrupts - -[system.cpu.isa] -type=SparcISA - -[system.cpu.itb] -type=SparcTLB -size=64 - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -egid=100 -env= -errout=cerr -euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1000 -conf_table_reported=false -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.master[0] - diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,3 +0,0 @@ -warn: CoherentBus system.membus has no snooping ports attached! -warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,43 +0,0 @@ -Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic/simout -Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2013 15:49:24 -gem5 started Jan 23 2013 16:12:25 -gem5 executing on ribera.cs.wisc.edu -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 744764112500 because target called exit() diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,65 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.744764 # Number of seconds simulated -sim_ticks 744764112500 # Number of ticks simulated -final_tick 744764112500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3917871 # Simulator instruction rate (inst/s) -host_op_rate 3929519 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1964765726 # Simulator tick rate (ticks/s) -host_mem_usage 224984 # Number of bytes of host memory used -host_seconds 379.06 # Real time elapsed on the host -sim_insts 1485108088 # Number of instructions simulated -sim_ops 1489523282 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 5940451992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1385817592 # Number of bytes read from this memory -system.physmem.bytes_read::total 7326269584 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5940451992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5940451992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 614672063 # Number of bytes written to this memory -system.physmem.bytes_written::total 614672063 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1485112998 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 402512843 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1887625841 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 166846816 # Number of write requests responded to by this memory -system.physmem.num_writes::total 166846816 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 1326 # Number of other requests responded to by this memory -system.physmem.num_other::total 1326 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7976286575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1860747005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9837033580 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7976286575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7976286575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 825324492 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 825324492 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7976286575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2686071498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10662358072 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 10662372316 # Throughput (bytes/s) -system.membus.data_through_bus 7940952255 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 1489528226 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1485108088 # Number of instructions committed -system.cpu.committedOps 1489523282 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1319481286 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses -system.cpu.num_func_calls 1207835 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 78161762 # number of instructions that are conditional controls -system.cpu.num_int_insts 1319481286 # number of integer instructions -system.cpu.num_fp_insts 8454127 # number of float instructions -system.cpu.num_int_register_reads 2499743560 # number of times the integer registers were read -system.cpu.num_int_register_writes 1234343145 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read -system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written -system.cpu.num_mem_refs 569365766 # number of memory refs -system.cpu.num_load_insts 402515345 # Number of load instructions -system.cpu.num_store_insts 166850421 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1489528226 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles - ----------- End Simulation Statistics ---------- diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,196 +0,0 @@ -[root] -type=Root -children=system -full_system=false -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -boot_osflags=a -clock=1000 -init_param=0 -kernel= -load_addr_mask=1099511627775 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clock=500 -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=262144 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dtb] -type=SparcTLB -size=64 - -[system.cpu.icache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=131072 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.interrupts] -type=SparcInterrupts - -[system.cpu.isa] -type=SparcISA - -[system.cpu.itb] -type=SparcTLB -size=64 - -[system.cpu.l2cache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -size=2097152 -system=system -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.toL2Bus] -type=CoherentBus -block_size=64 -clock=500 -header_cycles=1 -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1000 -conf_table_reported=false -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.master[0] - diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,43 +0,0 @@ -Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2013 15:49:24 -gem5 started Jan 23 2013 15:49:34 -gem5 executing on ribera.cs.wisc.edu -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 2061066313000 because target called exit() diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,433 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.061066 # Number of seconds simulated -sim_ticks 2061066313000 # Number of ticks simulated -final_tick 2061066313000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 684045 # Simulator instruction rate (inst/s) -host_op_rate 686079 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 949333559 # Simulator tick rate (ticks/s) -host_mem_usage 233488 # Number of bytes of host memory used -host_seconds 2171.07 # Real time elapsed on the host -sim_insts 1485108088 # Number of instructions simulated -sim_ops 1489523282 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1672512 # Number of bytes read from this memory -system.physmem.bytes_read::total 1737728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 161152 # Number of bytes written to this memory -system.physmem.bytes_written::total 161152 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26133 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27152 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2518 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2518 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 31642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 811479 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 843121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 31642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 31642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 78189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 78189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 78189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 31642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 811479 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 921310 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 921310 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 5293 # Transaction distribution -system.membus.trans_dist::ReadResp 5293 # Transaction distribution -system.membus.trans_dist::Writeback 2518 # Transaction distribution -system.membus.trans_dist::ReadExReq 21859 # Transaction distribution -system.membus.trans_dist::ReadExResp 21859 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 56822 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 56822 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1898880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 1898880 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1898880 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 49814000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 244368000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 4122132626 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1485108088 # Number of instructions committed -system.cpu.committedOps 1489523282 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1319481286 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses -system.cpu.num_func_calls 1207835 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 78161762 # number of instructions that are conditional controls -system.cpu.num_int_insts 1319481286 # number of integer instructions -system.cpu.num_fp_insts 8454127 # number of float instructions -system.cpu.num_int_register_reads 2499743560 # number of times the integer registers were read -system.cpu.num_int_register_writes 1234343144 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read -system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written -system.cpu.num_mem_refs 569365766 # number of memory refs -system.cpu.num_load_insts 402515345 # Number of load instructions -system.cpu.num_store_insts 166850421 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4122132626 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 118 # number of replacements -system.cpu.icache.tagsinuse 906.468716 # Cycle average of tags in use -system.cpu.icache.total_refs 1485111892 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1341564.491418 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 906.468716 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.442612 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.442612 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1485111892 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1485111892 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1485111892 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1485111892 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1485111892 # number of overall hits -system.cpu.icache.overall_hits::total 1485111892 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1107 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1107 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1107 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses -system.cpu.icache.overall_misses::total 1107 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 57199000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 57199000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 57199000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 57199000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 57199000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 57199000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1485112999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1485112999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1485112999 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1485112999 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1485112999 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1485112999 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51670.280036 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51670.280036 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51670.280036 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51670.280036 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51670.280036 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51670.280036 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1107 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1107 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1107 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54985000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 54985000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54985000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 54985000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54985000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 54985000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49670.280036 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49670.280036 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49670.280036 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49670.280036 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49670.280036 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49670.280036 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2539 # number of replacements -system.cpu.l2cache.tagsinuse 22253.549915 # Cycle average of tags in use -system.cpu.l2cache.total_refs 534785 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23989 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.292926 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20839.325928 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 913.017348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 501.206640 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.635966 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.027863 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.015296 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.679124 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 88 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 189212 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 189300 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 435341 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 435341 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 237876 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 237876 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 88 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 427088 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 427176 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 88 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 427088 # number of overall hits -system.cpu.l2cache.overall_hits::total 427176 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1019 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4274 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5293 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21859 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21859 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26133 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27152 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1019 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26133 # number of overall misses -system.cpu.l2cache.overall_misses::total 27152 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 52998000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 222248000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 275246000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1136668000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1136668000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 52998000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1358916000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1411914000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 52998000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1358916000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1411914000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1107 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 193486 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 194593 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 435341 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 435341 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 259735 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 259735 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1107 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 453221 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 454328 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1107 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 453221 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 454328 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.920506 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022089 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.027200 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.084159 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.084159 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.920506 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.057661 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.059763 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.920506 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.057661 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.059763 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52009.813543 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52001.889288 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52009.813543 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.368297 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52009.813543 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.368297 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2518 # number of writebacks -system.cpu.l2cache.writebacks::total 2518 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1019 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4274 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5293 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21859 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21859 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26133 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27152 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26133 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27152 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40770000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 170960000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 211730000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 874360000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 874360000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40770000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1045320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1086090000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40770000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1045320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1086090000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.920506 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022089 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027200 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.084159 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.084159 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.920506 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.057661 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059763 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.920506 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.057661 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.059763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40009.813543 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.889288 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40009.813543 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.368297 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40009.813543 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.368297 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 449125 # number of replacements -system.cpu.dcache.tagsinuse 4095.236014 # Cycle average of tags in use -system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 559340000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.236014 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999813 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999813 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 402319357 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 402319357 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 166587088 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 568906445 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 568906445 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 568906445 # number of overall hits -system.cpu.dcache.overall_hits::total 568906445 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 193486 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 193486 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 259728 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 259728 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 453214 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses -system.cpu.dcache.overall_misses::total 453214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2694826000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2694826000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4294500000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4294500000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 133000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 133000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6989326000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6989326000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6989326000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6989326000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 402512843 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 402512843 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 569359659 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 569359659 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 569359659 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 569359659 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000481 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001557 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13927.757047 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13927.757047 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16534.605433 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16534.605433 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 19000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 19000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15421.690416 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15421.690416 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 435341 # number of writebacks -system.cpu.dcache.writebacks::total 435341 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 193486 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 193486 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 259728 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 259728 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 453214 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775044000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775044000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082898000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6082898000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082898000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6082898000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001557 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.605433 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.605433 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 27625902 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 194593 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 194593 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 435341 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 259735 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 259735 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2214 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1341783 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 1343997 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 70848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 56867968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 56938816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 56938816 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 880175500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1660500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 679831500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,573 +0,0 @@ -[root] -type=Root -children=system -full_system=false -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -boot_osflags=a -clock=1000 -init_param=0 -kernel= -load_addr_mask=1099511627775 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clock=500 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=true -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbDepth=1 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=BranchPredictor -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -instShiftAmt=2 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -predType=tournament - -[system.cpu.dcache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=262144 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dtb] -type=X86TLB -children=walker -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=X86PagetableWalker -clock=500 -system=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -issueLat=1 -opClass=SimdAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -issueLat=1 -opClass=SimdAddAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -issueLat=1 -opClass=SimdAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -issueLat=1 -opClass=SimdCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -issueLat=1 -opClass=SimdCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -issueLat=1 -opClass=SimdMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -issueLat=1 -opClass=SimdMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -issueLat=1 -opClass=SimdMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -issueLat=1 -opClass=SimdShift -opLat=1 - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -issueLat=1 -opClass=SimdShiftAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -issueLat=1 -opClass=SimdSqrt -opLat=1 - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -issueLat=1 -opClass=SimdFloatAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -issueLat=1 -opClass=SimdFloatAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -issueLat=1 -opClass=SimdFloatCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -issueLat=1 -opClass=SimdFloatCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -issueLat=1 -opClass=SimdFloatDiv -opLat=1 - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -issueLat=1 -opClass=SimdFloatMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -issueLat=1 -opClass=SimdFloatMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -issueLat=1 -opClass=SimdFloatMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -issueLat=1 -opClass=SimdFloatSqrt -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=131072 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.interrupts] -type=X86LocalApic -clock=8000 -int_latency=1000 -pio_addr=2305843009213693952 -pio_latency=100000 -system=system -int_master=system.membus.slave[2] -int_slave=system.membus.master[2] -pio=system.membus.master[1] - -[system.cpu.isa] -type=X86ISA - -[system.cpu.itb] -type=X86TLB -children=walker -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=X86PagetableWalker -clock=500 -system=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -size=2097152 -system=system -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.toL2Bus] -type=CoherentBus -block_size=64 -clock=500 -header_cycles=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -system=system -use_default_range=false -width=8 -master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave -slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master - -[system.physmem] -type=SimpleDRAM -activation_limit=4 -addr_mapping=openmap -banks_per_rank=8 -channels=1 -clock=1000 -conf_table_reported=false -in_addr_map=true -lines_per_rowbuffer=32 -mem_sched_policy=frfcfs -null=false -page_policy=open -range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -tBURST=5000 -tCL=13750 -tRCD=13750 -tREFI=7800000 -tRFC=300000 -tRP=13750 -tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_thresh_perc=70 -zero=false -port=system.membus.master[0] - diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,45 +0,0 @@ -Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Mar 26 2013 15:13:59 -gem5 started Mar 27 2013 00:17:33 -gem5 executing on ribera.cs.wisc.edu -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -info: Increasing stack size by one page. -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -info: Increasing stack size by one page. -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 607388314000 because target called exit() diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,894 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.602445 # Number of seconds simulated -sim_ticks 602445443000 # Number of ticks simulated -final_tick 602445443000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75864 # Simulator instruction rate (inst/s) -host_op_rate 139784 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51934905 # Simulator tick rate (ticks/s) -host_mem_usage 251596 # Number of bytes of host memory used -host_seconds 11600.01 # Real time elapsed on the host -sim_insts 880025277 # Number of instructions simulated -sim_ops 1621493927 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 57088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1693376 # Number of bytes read from this memory -system.physmem.bytes_read::total 1750464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 57088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 57088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162240 # Number of bytes written to this memory -system.physmem.bytes_written::total 162240 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 892 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26459 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27351 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2535 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2535 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 94760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2810837 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2905598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 94760 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 94760 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 269302 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 269302 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 269302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 94760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2810837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3174900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27351 # Total number of read requests seen -system.physmem.writeReqs 2535 # Total number of write requests seen -system.physmem.cpureqs 29886 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1750464 # Total number of bytes read from memory -system.physmem.bytesWritten 162240 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1750464 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162240 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1685 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1663 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1729 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1833 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1606 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1566 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1601 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1748 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1766 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1798 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1764 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1769 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1731 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1726 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1630 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 168 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 147 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 163 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 152 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 602445296500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27351 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 2535 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 26984 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 9716 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 196.485797 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 83.147665 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 791.749785 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 8505 87.54% 87.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 120 1.24% 88.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 95 0.98% 89.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 92 0.95% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 80 0.82% 91.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 71 0.73% 92.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 54 0.56% 92.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 469 4.83% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 5 0.05% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 8 0.08% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 7 0.07% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 4 0.04% 97.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1 0.01% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 2 0.02% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 6 0.06% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 3 0.03% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 10 0.10% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 4 0.04% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 3 0.03% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.02% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.02% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 5 0.05% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 1 0.01% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 2 0.02% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 5 0.05% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.03% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 2 0.02% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.02% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 2 0.02% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 4 0.04% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 6 0.06% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 3 0.03% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.01% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 2 0.02% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.01% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.01% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.01% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 4 0.04% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 4 0.04% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.01% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 1 0.01% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 9 0.09% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.01% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 12 0.12% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 1 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.01% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.01% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 5 0.05% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 3 0.03% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 1 0.01% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 2 0.02% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 4 0.04% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.04% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 2 0.02% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 4 0.04% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.02% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 60 0.62% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 9716 # Bytes accessed per row activation -system.physmem.totQLat 64494000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 817427750 # Sum of mem lat for all requests -system.physmem.totBusLat 136755000 # Total cycles spent in databus access -system.physmem.totBankLat 616178750 # Total cycles spent in bank access -system.physmem.avgQLat 2358.01 # Average queueing delay per request -system.physmem.avgBankLat 22528.56 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29886.58 # Average memory access latency -system.physmem.avgRdBW 2.91 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.91 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.27 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 6.79 # Average write queue length over time -system.physmem.readRowHits 18283 # Number of row buffer hits during reads -system.physmem.writeRowHits 1882 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.85 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.24 # Row buffer hit rate for writes -system.physmem.avgGap 20158110.70 # Average gap between requests -system.membus.throughput 3174900 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 5446 # Transaction distribution -system.membus.trans_dist::ReadResp 5446 # Transaction distribution -system.membus.trans_dist::Writeback 2535 # Transaction distribution -system.membus.trans_dist::ReadExReq 21905 # Transaction distribution -system.membus.trans_dist::ReadExResp 21905 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 57237 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 57237 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 57237 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 57237 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1912704 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1912704 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 1912704 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1912704 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1912704 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 54082500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 256518250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 155713554 # Number of BP lookups -system.cpu.branchPred.condPredicted 155713554 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25700556 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80709168 # Number of BTB lookups -system.cpu.branchPred.BTBHits 80519202 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.764629 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1652287 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5525 # Number of incorrect RAS predictions. -system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1204890888 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 175274710 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1434157607 # Number of instructions fetch has processed -system.cpu.fetch.Branches 155713554 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 82171489 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 393078664 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83865410 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 578146605 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 120 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 818 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 183614088 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10709458 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1204511587 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.041777 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.242024 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 818350873 67.94% 67.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 26907285 2.23% 70.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 13113553 1.09% 71.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20212953 1.68% 72.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26380040 2.19% 75.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18070462 1.50% 76.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31901824 2.65% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 38309687 3.18% 82.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 211264910 17.54% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1204511587 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.129235 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.190280 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 284457753 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 500656322 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 268669195 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92717647 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 58010670 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2309624447 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 58010670 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 333355935 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 124738073 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 4511 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 298536751 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 389865647 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2217848111 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 12491 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 242988677 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 121785341 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2582951472 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5647827193 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5647820629 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6564 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1886895260 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 696056212 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 111 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 111 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 737069424 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 525225323 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 216592521 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 339815721 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144680776 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1968472561 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 318 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1774064524 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 139240 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 346662124 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 707342719 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 269 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1204511587 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.472850 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.418809 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 354280098 29.41% 29.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 362488713 30.09% 59.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234063693 19.43% 78.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 140542909 11.67% 90.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60330954 5.01% 95.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 39440037 3.27% 98.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10861856 0.90% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1902055 0.16% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 601272 0.05% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1204511587 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 393728 13.88% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2222867 78.36% 92.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 220107 7.76% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46812439 2.64% 2.64% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1058775186 59.68% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 18990 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 399 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 476273356 26.85% 89.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192184154 10.83% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1774064524 # Type of FU issued -system.cpu.iq.rate 1.472386 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2836702 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001599 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4755616169 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2315308754 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1716674618 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 408 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1904 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 108 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1730088586 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 201 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 210326331 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 106183201 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 39649 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 179972 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 28406463 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2374 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 51 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 58010670 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1594890 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 105925 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1968472879 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 62991695 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 525225323 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 216592521 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 95 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49046 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2792 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 179972 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1387758 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24439911 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25827669 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1757610573 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 472678337 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 16453951 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 664130755 # number of memory reference insts executed -system.cpu.iew.exec_branches 110138876 # Number of branches executed -system.cpu.iew.exec_stores 191452418 # Number of stores executed -system.cpu.iew.exec_rate 1.458730 # Inst execution rate -system.cpu.iew.wb_sent 1717393687 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1716674726 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1259775247 # num instructions producing a value -system.cpu.iew.wb_consumers 1819353010 # num instructions consuming a value -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.424755 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692430 # average fanout of values written-back -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 346980337 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 49 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25700670 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1146500917 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.414298 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.835051 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 413558140 36.07% 36.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 412696375 36.00% 72.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 87598589 7.64% 79.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122118435 10.65% 90.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 23941558 2.09% 92.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25472827 2.22% 94.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 16346085 1.43% 96.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12113072 1.06% 97.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 32655836 2.85% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1146500917 # Number of insts commited each cycle -system.cpu.commit.committedInsts 880025277 # Number of instructions committed -system.cpu.commit.committedOps 1621493927 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 607228180 # Number of memory references committed -system.cpu.commit.loads 419042122 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 107161574 # Number of branches committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1621354439 # Number of committed integer instructions. -system.cpu.commit.function_calls 1061692 # Number of function calls committed. -system.cpu.commit.bw_lim_events 32655836 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3082319345 # The number of ROB reads -system.cpu.rob.rob_writes 3994980480 # The number of ROB writes -system.cpu.timesIdled 60198 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 379301 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 880025277 # Number of Instructions Simulated -system.cpu.committedOps 1621493927 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.369155 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.369155 # CPI: Total CPI of All Threads -system.cpu.ipc 0.730378 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.730378 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3534848910 # number of integer regfile reads -system.cpu.int_regfile_writes 1966187639 # number of integer regfile writes -system.cpu.fp_regfile_reads 108 # number of floating regfile reads -system.cpu.misc_regfile_reads 906058625 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 93496055 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 204764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 204764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 428981 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246353 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246353 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1828 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1329391 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 1331219 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 58368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 56267648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 56326016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 56326016 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 869032000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1556249 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 681716500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 799.364211 # Cycle average of tags in use -system.cpu.icache.total_refs 183612696 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 912 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 201329.710526 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 799.364211 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.390315 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.390315 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 183612696 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 183612696 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 183612696 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 183612696 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 183612696 # number of overall hits -system.cpu.icache.overall_hits::total 183612696 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1392 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1392 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1392 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1392 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1392 # number of overall misses -system.cpu.icache.overall_misses::total 1392 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 85807499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 85807499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 85807499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 85807499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 85807499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 85807499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 183614088 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 183614088 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 183614088 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 183614088 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 183614088 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 183614088 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000008 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000008 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000008 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000008 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000008 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000008 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61643.318247 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61643.318247 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61643.318247 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61643.318247 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61643.318247 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61643.318247 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 178 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.333333 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 476 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 476 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 476 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 476 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 476 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 476 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 916 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 916 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 916 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 916 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61610251 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 61610251 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61610251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 61610251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61610251 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 61610251 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67260.099345 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67260.099345 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67260.099345 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67260.099345 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67260.099345 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67260.099345 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2557 # number of replacements -system.cpu.l2cache.tagsinuse 22238.496422 # Cycle average of tags in use -system.cpu.l2cache.total_refs 531475 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24184 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.976307 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20776.249700 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 785.755358 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 676.491363 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.634041 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.023979 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020645 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.678665 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 199294 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 199314 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 428981 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 428981 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 224448 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 224448 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 423742 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 423762 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 423742 # number of overall hits -system.cpu.l2cache.overall_hits::total 423762 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 892 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4554 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5446 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21905 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21905 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 892 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26459 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27351 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 892 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26459 # number of overall misses -system.cpu.l2cache.overall_misses::total 27351 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60484750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 412971750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 473456500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1511465750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1511465750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 60484750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1924437500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1984922250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 60484750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1924437500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1984922250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 912 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 203848 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 204760 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 428981 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 428981 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246353 # 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Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 450201 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 999.724639 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 969034250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4092.265452 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999088 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999088 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 262137382 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 262137382 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 187939646 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 187939646 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 450077028 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 450077028 # 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average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14716.547387 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18287.535713 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 18287.535713 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.140580 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16639.140580 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.140580 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16639.140580 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 483 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 48 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.062500 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4002338750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6613634000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6613634000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6613634000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6613634000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000777 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000777 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000999 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000999 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12809.446082 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12809.446082 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16246.686598 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16246.686598 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14690.272209 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14690.272209 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14690.272209 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14690.272209 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,149 +0,0 @@ -[root] -type=Root -children=system -full_system=false -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -boot_osflags=a -clock=1000 -init_param=0 -kernel= -load_addr_mask=1099511627775 -mem_mode=atomic -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clock=500 -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simulate_data_stalls=false -simulate_inst_stalls=false -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=X86TLB -children=walker -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=X86PagetableWalker -clock=500 -system=system -port=system.membus.slave[4] - -[system.cpu.interrupts] -type=X86LocalApic -clock=8000 -int_latency=1000 -pio_addr=2305843009213693952 -pio_latency=100000 -system=system -int_master=system.membus.slave[5] -int_slave=system.membus.master[2] -pio=system.membus.master[1] - -[system.cpu.isa] -type=X86ISA - -[system.cpu.itb] -type=X86TLB -children=walker -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=X86PagetableWalker -clock=500 -system=system -port=system.membus.slave[3] - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -egid=100 -env= -errout=cerr -euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -system=system -use_default_range=false -width=8 -master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1000 -conf_table_reported=false -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.master[0] - diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,44 +0,0 @@ -Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic/simout -Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Mar 11 2013 13:21:48 -gem5 started Mar 11 2013 13:30:35 -gem5 executing on ribera.cs.wisc.edu -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -info: Increasing stack size by one page. -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 963992672000 because target called exit() diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,63 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.963993 # Number of seconds simulated -sim_ticks 963992672000 # Number of ticks simulated -final_tick 963992672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 988845 # Simulator instruction rate (inst/s) -host_op_rate 1822001 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1083195788 # Simulator tick rate (ticks/s) -host_mem_usage 286888 # Number of bytes of host memory used -host_seconds 889.95 # Real time elapsed on the host -sim_insts 880025278 # Number of instructions simulated -sim_ops 1621493928 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1842452911 # Number of bytes read from this memory -system.physmem.bytes_read::total 11334586471 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 9492133560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 9492133560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 864451002 # Number of bytes written to this memory -system.physmem.bytes_written::total 864451002 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1186516695 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 419042122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1605558817 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 188186058 # Number of write requests responded to by this memory -system.physmem.num_writes::total 188186058 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9846686428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1911272735 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11757959163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9846686428 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9846686428 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 896740221 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 896740221 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9846686428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2808012957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12654699384 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 12654699384 # Throughput (bytes/s) -system.membus.data_through_bus 12199037473 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1927985345 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 880025278 # Number of instructions committed -system.cpu.committedOps 1621493928 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1621354440 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2123381 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls -system.cpu.num_int_insts 1621354440 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 4204103517 # number of times the integer registers were read -system.cpu.num_int_register_writes 1886895260 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 607228180 # number of memory refs -system.cpu.num_load_insts 419042122 # Number of load instructions -system.cpu.num_store_insts 188186058 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1927985345 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles - ----------- End Simulation Statistics ---------- diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,222 +0,0 @@ -[root] -type=Root -children=system -full_system=false -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -boot_osflags=a -clock=1000 -init_param=0 -kernel= -load_addr_mask=1099511627775 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clock=500 -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=262144 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dtb] -type=X86TLB -children=walker -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=X86PagetableWalker -clock=500 -system=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.icache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=131072 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.interrupts] -type=X86LocalApic -clock=8000 -int_latency=1000 -pio_addr=2305843009213693952 -pio_latency=100000 -system=system -int_master=system.membus.slave[2] -int_slave=system.membus.master[2] -pio=system.membus.master[1] - -[system.cpu.isa] -type=X86ISA - -[system.cpu.itb] -type=X86TLB -children=walker -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=X86PagetableWalker -clock=500 -system=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -size=2097152 -system=system -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.toL2Bus] -type=CoherentBus -block_size=64 -clock=500 -header_cycles=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -system=system -use_default_range=false -width=8 -master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave -slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1000 -conf_table_reported=false -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.master[0] - diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,44 +0,0 @@ -Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Mar 11 2013 13:21:48 -gem5 started Mar 11 2013 13:30:24 -gem5 executing on ribera.cs.wisc.edu -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -info: Increasing stack size by one page. -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 1800193398000 because target called exit() diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,414 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.800193 # Number of seconds simulated -sim_ticks 1800193398000 # Number of ticks simulated -final_tick 1800193398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 510604 # Simulator instruction rate (inst/s) -host_op_rate 940816 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1044499940 # Simulator tick rate (ticks/s) -host_mem_usage 295340 # Number of bytes of host memory used -host_seconds 1723.50 # Real time elapsed on the host -sim_insts 880025278 # Number of instructions simulated -sim_ops 1621493928 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1682368 # Number of bytes read from this memory -system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 46208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 46208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 160704 # Number of bytes written to this memory -system.physmem.bytes_written::total 160704 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 722 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26287 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27009 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2511 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2511 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 934548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 960217 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 25668 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 25668 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 89270 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 89270 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 89270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 934548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1049487 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 1049487 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 5039 # Transaction distribution -system.membus.trans_dist::ReadResp 5039 # Transaction distribution -system.membus.trans_dist::Writeback 2511 # Transaction distribution -system.membus.trans_dist::ReadExReq 21970 # Transaction distribution -system.membus.trans_dist::ReadExResp 21970 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 56529 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 56529 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 56529 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 56529 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1889280 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1889280 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 1889280 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1889280 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1889280 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 49608000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 243081000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 3600386796 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 880025278 # Number of instructions committed -system.cpu.committedOps 1621493928 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1621354440 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2123381 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls -system.cpu.num_int_insts 1621354440 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 4204103517 # number of times the integer registers were read -system.cpu.num_int_register_writes 1886895260 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 607228180 # number of memory refs -system.cpu.num_load_insts 419042122 # Number of load instructions -system.cpu.num_store_insts 188186058 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3600386796 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 660.197305 # Cycle average of tags in use -system.cpu.icache.total_refs 1186515974 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1643373.925208 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 660.197305 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.322362 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.322362 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1186515974 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1186515974 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1186515974 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1186515974 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1186515974 # number of overall hits -system.cpu.icache.overall_hits::total 1186515974 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 722 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 722 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses -system.cpu.icache.overall_misses::total 722 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39712000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39712000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39712000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39712000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39712000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39712000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1186516696 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1186516696 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1186516696 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1186516696 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1186516696 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1186516696 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55002.770083 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55002.770083 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55002.770083 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55002.770083 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55002.770083 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55002.770083 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 722 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38268000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 38268000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38268000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 38268000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38268000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38268000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53002.770083 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53002.770083 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53002.770083 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53002.770083 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2532 # number of replacements -system.cpu.l2cache.tagsinuse 22211.029315 # Cycle average of tags in use -system.cpu.l2cache.total_refs 519268 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.788687 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21021.301343 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 643.199216 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 546.528756 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.641519 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.019629 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016679 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.677827 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 193009 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 193009 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 422980 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 422980 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 222752 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 222752 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 415761 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 415761 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 415761 # number of overall hits -system.cpu.l2cache.overall_hits::total 415761 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4317 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5039 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21970 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21970 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 722 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26287 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27009 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 722 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26287 # number of overall misses -system.cpu.l2cache.overall_misses::total 27009 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37546000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 224484000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 262030000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1143343000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1143343000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 37546000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1367827000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1405373000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 37546000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1367827000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1405373000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 197326 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 198048 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 422980 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 422980 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 244722 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 244722 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 722 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 442048 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 442770 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 722 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 442048 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 442770 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021878 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.025443 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089775 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.089775 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.059466 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.061000 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.059466 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.061000 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.770083 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.396904 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52041.101502 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52041.101502 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.770083 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52034.351581 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52033.507349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.770083 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52034.351581 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52033.507349 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2511 # number of writebacks -system.cpu.l2cache.writebacks::total 2511 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4317 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5039 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21970 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21970 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26287 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27009 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26287 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27009 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28882000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 172680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201562000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 879703000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 879703000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28882000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1052383000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1081265000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28882000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1052383000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1081265000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021878 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.025443 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089775 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089775 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059466 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.061000 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059466 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.061000 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.770083 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.396904 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40041.101502 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40041.101502 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.770083 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40034.351581 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.770083 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40034.351581 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 437952 # number of replacements -system.cpu.dcache.tagsinuse 4094.905740 # Cycle average of tags in use -system.cpu.dcache.total_refs 606786132 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1372.670235 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 771788000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.905740 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 418844796 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 418844796 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 187941336 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 187941336 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 606786132 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 606786132 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 606786132 # number of overall hits -system.cpu.dcache.overall_hits::total 606786132 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 244722 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 442048 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses -system.cpu.dcache.overall_misses::total 442048 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2746552000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2746552000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4105029000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4105029000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6851581000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6851581000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6851581000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6851581000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 419042122 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 419042122 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 607228180 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 607228180 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 607228180 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 607228180 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001300 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13918.855093 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13918.855093 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16774.254052 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16774.254052 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15499.631262 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15499.631262 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 422980 # number of writebacks -system.cpu.dcache.writebacks::total 422980 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197326 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197326 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 244722 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 244722 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 442048 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3615585000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3615585000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5967485000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5967485000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5967485000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5967485000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001300 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14774.254052 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14774.254052 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 30778915 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 198048 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 198048 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 422980 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 244722 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 244722 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1444 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1307076 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 1308520 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 55361792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 55408000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 55408000 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 855855000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1083000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 663072000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 3935aa172f34 -r e49271f36b3c tests/long/se/00.gzip/test.py --- a/tests/long/se/00.gzip/test.py Thu Jun 06 22:34:43 2013 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,33 +0,0 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Korey Sewell - -m5.util.addToPath('../configs/common') -from cpu2000 import gzip_log - -workload = gzip_log(isa, opsys, 'smred') -root.system.cpu.workload = workload.makeLiveProcess()