diff -r f73d7c34b8c5 -r b914860111a9 tests/configs/inorder-timing.py --- a/tests/configs/inorder-timing.py Tue Jun 11 15:51:57 2013 +0100 +++ b/tests/configs/inorder-timing.py Tue Jun 11 15:57:19 2013 +0100 @@ -1,3 +1,15 @@ +# Copyright (c) 2013 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # @@ -24,29 +36,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Hansson -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -from Caches import * +from base_config import * -cpu = InOrderCPU(cpu_id=0) -cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'), - L1Cache(size = '256kB'), - L2Cache(size = '2MB')) - -cpu.clock = '2GHz' - -system = System(cpu = cpu, - physmem = DDR3_1600_x64(), - membus = CoherentBus(), - mem_mode = "timing") -system.clock = '1GHz' -system.system_port = system.membus.slave -system.physmem.port = system.membus.master -# create the interrupt controller -cpu.createInterruptController() -cpu.connectAllPorts(system.membus) - -root = Root(full_system = False, system = system) +root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64, + cpu_class=InOrderCPU).create_root() diff -r f73d7c34b8c5 -r b914860111a9 tests/configs/base_config.py --- a/tests/configs/base_config.py Tue Jun 11 15:51:57 2013 +0100 +++ b/tests/configs/base_config.py Tue Jun 11 15:57:19 2013 +0100 @@ -1,4 +1,4 @@ -# Copyright (c) 2012 ARM Limited +# Copyright (c) 2012-2013 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -34,6 +34,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Andreas Sandberg +# Andreas Hansson from abc import ABCMeta, abstractmethod import m5 @@ -56,17 +57,19 @@ __metaclass__ = ABCMeta - def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU, - num_cpus=1, checker=False): - """Initialize a simple ARM system. + def __init__(self, mem_mode='timing', mem_class=SimpleMemory, + cpu_class=TimingSimpleCPU, num_cpus=1, checker=False): + """Initialize a simple base system. Keyword Arguments: mem_mode -- String describing the memory mode (timing or atomic) + mem_class -- Memory controller class to use cpu_class -- CPU class to use num_cpus -- Number of CPUs to instantiate checker -- Set to True to add checker CPUs """ self.mem_mode = mem_mode + self.mem_class = mem_class self.cpu_class = cpu_class self.num_cpus = num_cpus self.checker = checker @@ -153,6 +156,50 @@ defined by this class.""" pass +class BaseSESystem(BaseSystem): + """Basic syscall-emulation builder.""" + + def __init__(self, **kwargs): + BaseSystem.__init__(self, **kwargs) + + def init_system(self, system): + BaseSystem.init_system(self, system) + + def create_system(self): + system = System(physmem = self.mem_class(), + membus = CoherentBus(), + mem_mode = self.mem_mode) + system.system_port = system.membus.slave + system.physmem.port = system.membus.master + self.init_system(system) + return system + + def create_root(self): + system = self.create_system() + m5.ticks.setGlobalFrequency('1THz') + return Root(full_system=False, system=system) + +class BaseSESystemUniprocessor(BaseSESystem): + """Basic syscall-emulation builder for uniprocessor systems. + + Note: This class is only really needed to provide backwards + compatibility in existing test cases. + """ + + def __init__(self, **kwargs): + BaseSESystem.__init__(self, **kwargs) + + def create_caches_private(self, cpu): + # The atomic SE configurations do not use caches + if self.mem_mode == "timing": + # @todo We might want to revisit these rather enthusiastic L1 sizes + cpu.addTwoLevelCacheHierarchy(L1Cache(size='128kB'), + L1Cache(size='256kB'), + L2Cache(size='2MB')) + + def create_caches_shared(self, system): + return None + class BaseFSSystem(BaseSystem): """Basic full system builder.""" diff -r f73d7c34b8c5 -r b914860111a9 tests/configs/o3-timing-checker.py --- a/tests/configs/o3-timing-checker.py Tue Jun 11 15:51:57 2013 +0100 +++ b/tests/configs/o3-timing-checker.py Tue Jun 11 15:57:19 2013 +0100 @@ -1,5 +1,5 @@ -# Copyright (c) 2011 ARM Limited -# All rights reserved +# Copyright (c) 2013 ARM Limited +# All rights reserved. # # The license below extends only to copyright in the software and shall # not be construed as granting a license to any other intellectual @@ -33,31 +33,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Geoffrey Blake +# Authors: Andreas Hansson -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -from Caches import * +from base_config import * -cpu = DerivO3CPU(cpu_id=0) -cpu.createInterruptController() -cpu.addCheckerCpu() -cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'), - L1Cache(size = '256kB'), - L2Cache(size = '2MB')) -# @todo Note that the L2 latency here is unmodified and 2 cycles, -# should set hit latency and response latency to 20 cycles as for -# other scripts -cpu.clock = '2GHz' - -system = System(cpu = cpu, - physmem = DDR3_1600_x64(), - membus = CoherentBus(), - mem_mode = "timing") -system.clock = '1GHz' -system.system_port = system.membus.slave -system.physmem.port = system.membus.master -cpu.connectAllPorts(system.membus) - -root = Root(full_system = False, system = system) +root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64, + cpu_class=DerivO3CPU, + checker=True).create_root() diff -r f73d7c34b8c5 -r b914860111a9 tests/configs/o3-timing.py --- a/tests/configs/o3-timing.py Tue Jun 11 15:51:57 2013 +0100 +++ b/tests/configs/o3-timing.py Tue Jun 11 15:57:19 2013 +0100 @@ -1,3 +1,15 @@ +# Copyright (c) 2013 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # @@ -24,31 +36,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Hansson -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -from Caches import * +from base_config import * -cpu = DerivO3CPU(cpu_id=0) -cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'), - L1Cache(size = '256kB'), - L2Cache(size = '2MB')) -# @todo Note that the L2 latency here is unmodified and 2 cycles, -# should set hit latency and response latency to 20 cycles as for -# other scripts -cpu.clock = '2GHz' - -system = System(cpu = cpu, - physmem = DDR3_1600_x64(), - membus = CoherentBus(), - mem_mode = "timing") -system.clock = '1GHz' -system.system_port = system.membus.slave -system.physmem.port = system.membus.master -# create the interrupt controller -cpu.createInterruptController() -cpu.connectAllPorts(system.membus) - -root = Root(full_system = False, system = system) +root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64, + cpu_class=DerivO3CPU).create_root() diff -r f73d7c34b8c5 -r b914860111a9 tests/configs/simple-atomic-dummychecker.py --- a/tests/configs/simple-atomic-dummychecker.py Tue Jun 11 15:51:57 2013 +0100 +++ b/tests/configs/simple-atomic-dummychecker.py Tue Jun 11 15:57:19 2013 +0100 @@ -1,5 +1,5 @@ -# Copyright (c) 2011 ARM Limited -# All rights reserved +# Copyright (c) 2013 ARM Limited +# All rights reserved. # # The license below extends only to copyright in the software and shall # not be construed as granting a license to any other intellectual @@ -33,20 +33,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Geoffrey Blake +# Authors: Andreas Hansson -import m5 from m5.objects import * +from base_config import * -system = System(cpu = AtomicSimpleCPU(cpu_id=0), - physmem = SimpleMemory(), - membus = CoherentBus()) -system.clock = '1GHz' -system.system_port = system.membus.slave -system.physmem.port = system.membus.master -system.cpu.addCheckerCpu() -system.cpu.createInterruptController() -system.cpu.connectAllPorts(system.membus) -system.cpu.clock = '2GHz' - -root = Root(full_system = False, system = system) +root = BaseSESystemUniprocessor(mem_mode='atomic', + cpu_class=AtomicSimpleCPU, + checker=True).create_root() diff -r f73d7c34b8c5 -r b914860111a9 tests/configs/simple-atomic.py --- a/tests/configs/simple-atomic.py Tue Jun 11 15:51:57 2013 +0100 +++ b/tests/configs/simple-atomic.py Tue Jun 11 15:57:19 2013 +0100 @@ -1,3 +1,15 @@ +# Copyright (c) 2013 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # @@ -24,20 +36,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Hansson -import m5 from m5.objects import * +from base_config import * -system = System(cpu = AtomicSimpleCPU(cpu_id=0), - physmem = SimpleMemory(), - membus = CoherentBus()) -system.clock = '1GHz' -system.system_port = system.membus.slave -system.physmem.port = system.membus.master -# create the interrupt controller -system.cpu.createInterruptController() -system.cpu.connectAllPorts(system.membus) -system.cpu.clock = '2GHz' - -root = Root(full_system = False, system = system) +root = BaseSESystemUniprocessor(mem_mode='atomic', + cpu_class=AtomicSimpleCPU).create_root() diff -r f73d7c34b8c5 -r b914860111a9 tests/configs/simple-timing.py --- a/tests/configs/simple-timing.py Tue Jun 11 15:51:57 2013 +0100 +++ b/tests/configs/simple-timing.py Tue Jun 11 15:57:19 2013 +0100 @@ -1,3 +1,15 @@ +# Copyright (c) 2013 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # @@ -24,27 +36,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Hansson -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -from Caches import * +from base_config import * -cpu = TimingSimpleCPU(cpu_id=0) -cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'), - L1Cache(size = '256kB'), - L2Cache(size = '2MB')) -system = System(cpu = cpu, - physmem = SimpleMemory(), - membus = CoherentBus(), - mem_mode = "timing") -system.clock = '1GHz' -system.system_port = system.membus.slave -system.physmem.port = system.membus.master -# create the interrupt controller -cpu.createInterruptController() -cpu.connectAllPorts(system.membus) -cpu.clock = '2GHz' - -root = Root(full_system=False, system = system) +root = BaseSESystemUniprocessor(mem_mode='timing', + cpu_class=TimingSimpleCPU).create_root() diff -r f73d7c34b8c5 -r b914860111a9 tests/long/se/10.mcf/test.py --- a/tests/long/se/10.mcf/test.py Tue Jun 11 15:51:57 2013 +0100 +++ b/tests/long/se/10.mcf/test.py Tue Jun 11 15:57:19 2013 +0100 @@ -30,5 +30,5 @@ from cpu2000 import mcf workload = mcf(isa, opsys, 'smred') -root.system.cpu.workload = workload.makeLiveProcess() +root.system.cpu[0].workload = workload.makeLiveProcess() root.system.physmem.range=AddrRange('256MB') diff -r f73d7c34b8c5 -r b914860111a9 tests/long/se/20.parser/test.py --- a/tests/long/se/20.parser/test.py Tue Jun 11 15:51:57 2013 +0100 +++ b/tests/long/se/20.parser/test.py Tue Jun 11 15:57:19 2013 +0100 @@ -30,4 +30,4 @@ from cpu2000 import parser workload = parser(isa, opsys, 'mdred') -root.system.cpu.workload = workload.makeLiveProcess() +root.system.cpu[0].workload = workload.makeLiveProcess() diff -r f73d7c34b8c5 -r b914860111a9 tests/long/se/30.eon/test.py --- a/tests/long/se/30.eon/test.py Tue Jun 11 15:51:57 2013 +0100 +++ b/tests/long/se/30.eon/test.py Tue Jun 11 15:57:19 2013 +0100 @@ -30,4 +30,4 @@ from cpu2000 import eon_cook workload = eon_cook(isa, opsys, 'mdred') -root.system.cpu.workload = workload.makeLiveProcess() +root.system.cpu[0].workload = workload.makeLiveProcess() diff -r f73d7c34b8c5 -r b914860111a9 tests/long/se/40.perlbmk/test.py --- a/tests/long/se/40.perlbmk/test.py Tue Jun 11 15:51:57 2013 +0100 +++ b/tests/long/se/40.perlbmk/test.py Tue Jun 11 15:57:19 2013 +0100 @@ -30,4 +30,4 @@ from cpu2000 import perlbmk_makerand workload = perlbmk_makerand(isa, opsys, 'lgred') -root.system.cpu.workload = workload.makeLiveProcess() +root.system.cpu[0].workload = workload.makeLiveProcess() diff -r f73d7c34b8c5 -r b914860111a9 tests/long/se/50.vortex/test.py --- a/tests/long/se/50.vortex/test.py Tue Jun 11 15:51:57 2013 +0100 +++ b/tests/long/se/50.vortex/test.py Tue Jun 11 15:57:19 2013 +0100 @@ -30,4 +30,4 @@ from cpu2000 import vortex workload = vortex(isa, opsys, 'smred') -root.system.cpu.workload = workload.makeLiveProcess() +root.system.cpu[0].workload = workload.makeLiveProcess() diff -r f73d7c34b8c5 -r b914860111a9 tests/long/se/60.bzip2/test.py --- a/tests/long/se/60.bzip2/test.py Tue Jun 11 15:51:57 2013 +0100 +++ b/tests/long/se/60.bzip2/test.py Tue Jun 11 15:57:19 2013 +0100 @@ -30,4 +30,4 @@ from cpu2000 import bzip2_source workload = bzip2_source(isa, opsys, 'lgred') -root.system.cpu.workload = workload.makeLiveProcess() +root.system.cpu[0].workload = workload.makeLiveProcess() diff -r f73d7c34b8c5 -r b914860111a9 tests/long/se/70.twolf/test.py --- a/tests/long/se/70.twolf/test.py Tue Jun 11 15:51:57 2013 +0100 +++ b/tests/long/se/70.twolf/test.py Tue Jun 11 15:57:19 2013 +0100 @@ -31,8 +31,8 @@ import os workload = twolf(isa, opsys, 'smred') -root.system.cpu.workload = workload.makeLiveProcess() -cwd = root.system.cpu.workload[0].cwd +root.system.cpu[0].workload = workload.makeLiveProcess() +cwd = root.system.cpu[0].workload[0].cwd #Remove two files who's presence or absence affects execution sav_file = os.path.join(cwd, workload.input_set + '.sav') diff -r f73d7c34b8c5 -r b914860111a9 tests/quick/se/00.hello/test.py --- a/tests/quick/se/00.hello/test.py Tue Jun 11 15:51:57 2013 +0100 +++ b/tests/quick/se/00.hello/test.py Tue Jun 11 15:57:19 2013 +0100 @@ -26,7 +26,7 @@ # # Authors: Steve Reinhardt -root.system.cpu.workload = LiveProcess(cmd = 'hello', - executable = binpath('hello')) -if root.system.cpu.checker != NULL: - root.system.cpu.checker.workload = root.system.cpu.workload +root.system.cpu[0].workload = LiveProcess(cmd = 'hello', + executable = binpath('hello')) +if root.system.cpu[0].checker != NULL: + root.system.cpu[0].checker.workload = root.system.cpu[0].workload diff -r f73d7c34b8c5 -r b914860111a9 tests/quick/se/01.hello-2T-smt/test.py --- a/tests/quick/se/01.hello-2T-smt/test.py Tue Jun 11 15:51:57 2013 +0100 +++ b/tests/quick/se/01.hello-2T-smt/test.py Tue Jun 11 15:57:19 2013 +0100 @@ -29,5 +29,5 @@ process1 = LiveProcess(cmd = 'hello', executable = binpath('hello')) process2 = LiveProcess(cmd = 'hello', executable = binpath('hello')) -root.system.cpu.workload = [process1, process2] -root.system.cpu.numThreads = 2 +root.system.cpu[0].workload = [process1, process2] +root.system.cpu[0].numThreads = 2 diff -r f73d7c34b8c5 -r b914860111a9 tests/quick/se/02.insttest/test.py --- a/tests/quick/se/02.insttest/test.py Tue Jun 11 15:51:57 2013 +0100 +++ b/tests/quick/se/02.insttest/test.py Tue Jun 11 15:57:19 2013 +0100 @@ -26,5 +26,5 @@ # # Authors: Ali Saidi -root.system.cpu.workload = LiveProcess(cmd = 'insttest', - executable = binpath('insttest')) +root.system.cpu[0].workload = LiveProcess(cmd = 'insttest', + executable = binpath('insttest')) diff -r f73d7c34b8c5 -r b914860111a9 tests/quick/se/20.eio-short/test.py --- a/tests/quick/se/20.eio-short/test.py Tue Jun 11 15:51:57 2013 +0100 +++ b/tests/quick/se/20.eio-short/test.py Tue Jun 11 15:57:19 2013 +0100 @@ -28,6 +28,6 @@ require_sim_object("EioProcess") -root.system.cpu.workload = EioProcess(file = binpath('anagram', +root.system.cpu[0].workload = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz')) -root.system.cpu.max_insts_any_thread = 500000 +root.system.cpu[0].max_insts_any_thread = 500000