diff -r 9df73385c878 -r 0f18925d4ae4 src/arch/x86/isa/microops/fpop.isa
--- a/src/arch/x86/isa/microops/fpop.isa	Tue Jun 11 09:43:05 2013 +0200
+++ b/src/arch/x86/isa/microops/fpop.isa	Tue Jun 11 14:54:33 2013 +0200
@@ -365,9 +365,9 @@
 
     class absfp(FpUnaryOp):
         code = 'FpDestReg = fabs(FpSrcReg1);'
-        flag_code = 'FSW &= (~CC1Bit);'
+        flag_code = 'FSW = FSW & (~CC1Bit);'
 
     class chsfp(FpUnaryOp):
         code = 'FpDestReg = (-1) * (FpSrcReg1);'
-        flag_code = 'FSW &= (~CC1Bit);'
+        flag_code = 'FSW = FSW & (~CC1Bit);'
 }};
diff -r 9df73385c878 -r 0f18925d4ae4 src/arch/x86/isa/insts/x87/arithmetic/change_sign.py
--- a/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py	Tue Jun 11 09:43:05 2013 +0200
+++ b/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py	Tue Jun 11 14:54:33 2013 +0200
@@ -38,10 +38,10 @@
 microcode = '''
 
 def macroop FABS {
-    absfp st(0), st(0)
+    absfp st(0), st(0), SetStatus=True
 };
 
 def macroop FCHS {
-    chsfp st(0), st(0)
+    chsfp st(0), st(0), SetStatus=True
 };
 '''