diff -r cec988a3082e -r 5523750ec6fe SConstruct --- a/SConstruct Fri Jun 28 08:50:25 2013 +0100 +++ b/SConstruct Fri Jun 28 09:13:27 2013 +0100 @@ -620,12 +620,9 @@ # clang has a few additional warnings that we disable, # tautological comparisons are allowed due to unsigned integers # being compared to constants that happen to be 0, and extraneous - # parantheses are allowed due to Ruby's printing of the AST, - # finally self assignments are allowed as the generated CPU code - # is relying on this + # parantheses are allowed due to Ruby's printing of the AST. main.Append(CCFLAGS=['-Wno-tautological-compare', - '-Wno-parentheses', - '-Wno-self-assign']) + '-Wno-parentheses']) main.Append(TCMALLOC_CCFLAGS=['-fno-builtin']) diff -r cec988a3082e -r 5523750ec6fe src/SConscript --- a/src/SConscript Fri Jun 28 08:50:25 2013 +0100 +++ b/src/SConscript Fri Jun 28 09:13:27 2013 +0100 @@ -894,8 +894,9 @@ swig_env = new_env.Clone() # Both gcc and clang have issues with unused labels and values in - # the SWIG generated code - swig_env.Append(CCFLAGS=['-Wno-unused-label', '-Wno-unused-value']) + # the SWIG generated code, as well as self assignment + swig_env.Append(CCFLAGS=['-Wno-unused-label', '-Wno-unused-value', + '-Wno-self-assign']) # Add additional warnings here that should not be applied to # the SWIG generated code diff -r cec988a3082e -r 5523750ec6fe src/arch/alpha/isa/branch.isa --- a/src/arch/alpha/isa/branch.isa Fri Jun 28 08:50:25 2013 +0100 +++ b/src/arch/alpha/isa/branch.isa Fri Jun 28 09:13:27 2013 +0100 @@ -229,8 +229,6 @@ %(code)s; if (cond) NPC = NPC + disp; - else - NPC = NPC; ''' % { "code" : code } iop = InstObjParams(name, Name, 'Branch', code, ('IsDirectControl', 'IsCondControl')) diff -r cec988a3082e -r 5523750ec6fe src/arch/arm/isa/formats/pred.isa --- a/src/arch/arm/isa/formats/pred.isa Fri Jun 28 08:50:25 2013 +0100 +++ b/src/arch/arm/isa/formats/pred.isa Fri Jun 28 09:13:27 2013 +0100 @@ -171,7 +171,6 @@ }}; def format DataImmOp(code, flagtype = logic) {{ - code += "resTemp = resTemp;" iop = InstObjParams(name, Name, 'PredImmOp', {"code": code, "predicate_test": pickPredicate(code)}) diff -r cec988a3082e -r 5523750ec6fe src/arch/arm/isa/insts/ldr.isa --- a/src/arch/arm/isa/insts/ldr.isa Fri Jun 28 08:50:25 2013 +0100 +++ b/src/arch/arm/isa/insts/ldr.isa Fri Jun 28 09:13:27 2013 +0100 @@ -194,7 +194,7 @@ # Code that actually handles the access if self.flavor == "dprefetch" or self.flavor == "iprefetch": - accCode = 'uint64_t temp = Mem%s; temp = temp;' + accCode = 'uint64_t temp M5_VAR_USED = Mem%s;' elif self.flavor == "fp": accCode = "FpDest_uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n" else: diff -r cec988a3082e -r 5523750ec6fe src/arch/arm/isa/templates/macromem.isa --- a/src/arch/arm/isa/templates/macromem.isa Fri Jun 28 08:50:25 2013 +0100 +++ b/src/arch/arm/isa/templates/macromem.isa Fri Jun 28 09:13:27 2013 +0100 @@ -228,8 +228,7 @@ Trace::InstRecord *traceData) const { Fault fault = NoFault; - uint64_t resTemp = 0; - resTemp = resTemp; + uint64_t resTemp M5_VAR_USED = 0; %(op_decl)s; %(op_rd)s; diff -r cec988a3082e -r 5523750ec6fe src/arch/arm/isa/templates/pred.isa --- a/src/arch/arm/isa/templates/pred.isa Fri Jun 28 08:50:25 2013 +0100 +++ b/src/arch/arm/isa/templates/pred.isa Fri Jun 28 09:13:27 2013 +0100 @@ -168,8 +168,7 @@ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; - uint64_t resTemp = 0; - resTemp = resTemp; + uint64_t resTemp M5_VAR_USED = 0; %(op_decl)s; %(op_rd)s; @@ -192,8 +191,7 @@ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; - uint64_t resTemp = 0; - resTemp = resTemp; + uint64_t resTemp M5_VAR_USED = 0; %(op_decl)s; %(op_rd)s; @@ -217,8 +215,7 @@ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; - uint64_t resTemp = 0; - resTemp = resTemp; + uint64_t resTemp M5_VAR_USED = 0; %(op_decl)s; %(op_rd)s; diff -r cec988a3082e -r 5523750ec6fe src/arch/mips/isa/decoder.isa --- a/src/arch/mips/isa/decoder.isa Fri Jun 28 08:50:25 2013 +0100 +++ b/src/arch/mips/isa/decoder.isa Fri Jun 28 09:13:27 2013 +0100 @@ -679,8 +679,8 @@ debug.iexi = 0; NPC = DEPC; } else { - NPC = NPC; // Undefined; + ; } Debug = debug; }}, IsReturn, IsSerializing, IsERET); @@ -1028,19 +1028,25 @@ 0x1: decode MOVCF { format BasicOp { 0x0: movf_s({{ - Fd = (getCondCode(FCSR,CC) == 0) ? - Fs : Fd; + if (getCondCode(FCSR,CC) == 0) + Fd = Fs; }}); 0x1: movt_s({{ - Fd = (getCondCode(FCSR,CC) == 1) ? - Fs : Fd; + if (getCondCode(FCSR,CC) == 1) + Fd = Fs; }}); } } format BasicOp { - 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); - 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); + 0x2: movz_s({{ + if (Rt == 0) + Fd = Fs; + }}); + 0x3: movn_s({{ + if (Rt != 0) + Fd = Fs; + }}); } format FloatOp { @@ -1484,7 +1490,7 @@ else Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>; } else { - Fd_ud = Fd_ud; + ; } }}); } diff -r cec988a3082e -r 5523750ec6fe src/arch/mips/isa/formats/branch.isa --- a/src/arch/mips/isa/formats/branch.isa Fri Jun 28 08:50:25 2013 +0100 +++ b/src/arch/mips/isa/formats/branch.isa Fri Jun 28 09:13:27 2013 +0100 @@ -231,7 +231,7 @@ }}; def format Branch(code, *opt_flags) {{ - not_taken_code = 'NNPC = NNPC; NPC = NPC;' + not_taken_code = ';' #Build Instruction Flags #Use Link & Likely Flags to Add Link/Condition Code @@ -270,7 +270,7 @@ }}; def format DspBranch(code, *opt_flags) {{ - not_taken_code = 'NNPC = NNPC; NPC = NPC;' + not_taken_code = ';' #Build Instruction Flags #Use Link & Likely Flags to Add Link/Condition Code diff -r cec988a3082e -r 5523750ec6fe src/arch/power/isa/formats/branch.isa --- a/src/arch/power/isa/formats/branch.isa Fri Jun 28 08:50:25 2013 +0100 +++ b/src/arch/power/isa/formats/branch.isa Fri Jun 28 09:13:27 2013 +0100 @@ -104,8 +104,6 @@ def GetCondCode(br_code): cond_code = 'if(condOk(CR)) {\n' cond_code += ' ' + br_code + '\n' - cond_code += '} else {\n' - cond_code += ' NPC = NPC;\n' cond_code += '}\n' return cond_code @@ -118,8 +116,6 @@ cond_code += 'bool cond_ok = condOk(CR);\n' cond_code += 'if(ctr_ok && cond_ok) {\n' cond_code += ' ' + br_code + '\n' - cond_code += '} else {\n' - cond_code += ' NPC = NPC;\n' cond_code += '}\n' cond_code += 'CTR = ctr;\n' return cond_code diff -r cec988a3082e -r 5523750ec6fe src/arch/sparc/isa/decoder.isa --- a/src/arch/sparc/isa/decoder.isa Fri Jun 28 08:50:25 2013 +0100 +++ b/src/arch/sparc/isa/decoder.isa Fri Jun 28 09:13:27 2013 +0100 @@ -411,26 +411,18 @@ 0x0: movccfcc0({{ if (passesCondition(Fsr<11:10>, COND4)) Rd = Rs2_or_imm11; - else - Rd = Rd; }}); 0x1: movccfcc1({{ if (passesCondition(Fsr<33:32>, COND4)) Rd = Rs2_or_imm11; - else - Rd = Rd; }}); 0x2: movccfcc2({{ if (passesCondition(Fsr<35:34>, COND4)) Rd = Rs2_or_imm11; - else - Rd = Rd; }}); 0x3: movccfcc3({{ if (passesCondition(Fsr<37:36>, COND4)) Rd = Rs2_or_imm11; - else - Rd = Rd; }}); } 0x1: decode CC @@ -438,14 +430,10 @@ 0x0: movcci({{ if (passesCondition(Ccr<3:0>, COND4)) Rd = Rs2_or_imm11; - else - Rd = Rd; }}); 0x2: movccx({{ if (passesCondition(Ccr<7:4>, COND4)) Rd = Rs2_or_imm11; - else - Rd = Rd; }}); } } @@ -632,53 +620,37 @@ 0x01: fmovs_fcc0({{ if (passesFpCondition(Fsr<11:10>, COND4)) Frds = Frs2s; - else - Frds = Frds; }}); 0x02: fmovd_fcc0({{ if (passesFpCondition(Fsr<11:10>, COND4)) Frd = Frs2; - else - Frd = Frd; }}); 0x03: FpUnimpl::fmovq_fcc0(); 0x25: fmovrsz({{ if (Rs1 == 0) Frds = Frs2s; - else - Frds = Frds; }}); 0x26: fmovrdz({{ if (Rs1 == 0) Frd = Frs2; - else - Frd = Frd; }}); 0x27: FpUnimpl::fmovrqz(); 0x41: fmovs_fcc1({{ if (passesFpCondition(Fsr<33:32>, COND4)) Frds = Frs2s; - else - Frds = Frds; }}); 0x42: fmovd_fcc1({{ if (passesFpCondition(Fsr<33:32>, COND4)) Frd = Frs2; - else - Frd = Frd; }}); 0x43: FpUnimpl::fmovq_fcc1(); 0x45: fmovrslez({{ if (Rs1 <= 0) Frds = Frs2s; - else - Frds = Frds; }}); 0x46: fmovrdlez({{ if (Rs1 <= 0) Frd = Frs2; - else - Frd = Frd; }}); 0x47: FpUnimpl::fmovrqlez(); 0x51: fcmps({{ @@ -742,105 +714,73 @@ 0x65: fmovrslz({{ if (Rs1 < 0) Frds = Frs2s; - else - Frds = Frds; }}); 0x66: fmovrdlz({{ if (Rs1 < 0) Frd = Frs2; - else - Frd = Frd; }}); 0x67: FpUnimpl::fmovrqlz(); 0x81: fmovs_fcc2({{ if (passesFpCondition(Fsr<35:34>, COND4)) Frds = Frs2s; - else - Frds = Frds; }}); 0x82: fmovd_fcc2({{ if (passesFpCondition(Fsr<35:34>, COND4)) Frd = Frs2; - else - Frd = Frd; }}); 0x83: FpUnimpl::fmovq_fcc2(); 0xA5: fmovrsnz({{ if (Rs1 != 0) Frds = Frs2s; - else - Frds = Frds; }}); 0xA6: fmovrdnz({{ if (Rs1 != 0) Frd = Frs2; - else - Frd = Frd; }}); 0xA7: FpUnimpl::fmovrqnz(); 0xC1: fmovs_fcc3({{ if (passesFpCondition(Fsr<37:36>, COND4)) Frds = Frs2s; - else - Frds = Frds; }}); 0xC2: fmovd_fcc3({{ if (passesFpCondition(Fsr<37:36>, COND4)) Frd = Frs2; - else - Frd = Frd; }}); 0xC3: FpUnimpl::fmovq_fcc3(); 0xC5: fmovrsgz({{ if (Rs1 > 0) Frds = Frs2s; - else - Frds = Frds; }}); 0xC6: fmovrdgz({{ if (Rs1 > 0) Frd = Frs2; - else - Frd = Frd; }}); 0xC7: FpUnimpl::fmovrqgz(); 0xE5: fmovrsgez({{ if (Rs1 >= 0) Frds = Frs2s; - else - Frds = Frds; }}); 0xE6: fmovrdgez({{ if (Rs1 >= 0) Frd = Frs2; - else - Frd = Frd; }}); 0xE7: FpUnimpl::fmovrqgez(); 0x101: fmovs_icc({{ if (passesCondition(Ccr<3:0>, COND4)) Frds = Frs2s; - else - Frds = Frds; }}); 0x102: fmovd_icc({{ if (passesCondition(Ccr<3:0>, COND4)) Frd = Frs2; - else - Frd = Frd; }}); 0x103: FpUnimpl::fmovq_icc(); 0x181: fmovs_xcc({{ if (passesCondition(Ccr<7:4>, COND4)) Frds = Frs2s; - else - Frds = Frds; }}); 0x182: fmovd_xcc({{ if (passesCondition(Ccr<7:4>, COND4)) Frd = Frs2; - else - Frd = Frd; }}); 0x183: FpUnimpl::fmovq_xcc(); default: FailUnimpl::fpop2(); diff -r cec988a3082e -r 5523750ec6fe src/arch/sparc/isa/formats/branch.isa --- a/src/arch/sparc/isa/formats/branch.isa Fri Jun 28 08:50:25 2013 +0100 +++ b/src/arch/sparc/isa/formats/branch.isa Fri Jun 28 09:13:27 2013 +0100 @@ -241,7 +241,6 @@ // Primary format for branch instructions: def format Branch(code, *opt_flags) {{ - code = 'NNPC = NNPC;\n' + code (usesImm, code, immCode, rString, iString) = splitOutImm(code) iop = InstObjParams(name, Name, 'Branch', code, opt_flags) @@ -295,7 +294,7 @@ def doCondBranch(name, Name, base, cond, code, opt_flags): opt_flags += ('IsCondControl', ) return doBranch(name, Name, base, cond, code, code, - 'NNPC = NNPC; NPC = NPC;\n', + ';', 'NNPC = NPC + 8; NPC = NPC + 4;\n', opt_flags) diff -r cec988a3082e -r 5523750ec6fe src/arch/x86/isa/decoder/two_byte_opcodes.isa --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa Fri Jun 28 08:50:25 2013 +0100 +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa Fri Jun 28 09:13:27 2013 +0100 @@ -731,11 +731,6 @@ Rbx = result.rbx; Rcx = result.rcx; Rdx = result.rdx; - } else { - Rax = Rax; - Rbx = Rbx; - Rcx = Rcx; - Rdx = Rdx; } }}); 0x3: Inst::BT(Ev,Gv); diff -r cec988a3082e -r 5523750ec6fe src/arch/x86/isa/macroop.isa --- a/src/arch/x86/isa/macroop.isa Fri Jun 28 08:50:25 2013 +0100 +++ b/src/arch/x86/isa/macroop.isa Fri Jun 28 09:13:27 2013 +0100 @@ -100,10 +100,8 @@ std::stringstream out; out << mnemonic << "\t"; - int regSize = %(regSize)s; + int regSize M5_VAR_USED = %(regSize)s; %(disassembly)s - // Shut up gcc. - regSize = regSize; return out.str(); } }}; @@ -161,14 +159,12 @@ self.adjust_env = "" self.init_env = "" self.adjust_imm = ''' - uint64_t adjustedImm = IMMEDIATE; - //This is to pacify gcc in case the immediate isn't used. - adjustedImm = adjustedImm; + uint64_t adjustedImm M5_VAR_USED = IMMEDIATE; + // Pacify gcc in case the immediate isn't used. ''' self.adjust_disp = ''' - uint64_t adjustedDisp = DISPLACEMENT; - //This is to pacify gcc in case the displacement isn't used. - adjustedDisp = adjustedDisp; + uint64_t adjustedDisp M5_VAR_USED = DISPLACEMENT; + // Pacify gcc in case the displacement isn't used. ''' self.serializing = False self.function_call = False diff -r cec988a3082e -r 5523750ec6fe src/arch/x86/isa/microops/fpop.isa --- a/src/arch/x86/isa/microops/fpop.isa Fri Jun 28 08:50:25 2013 +0100 +++ b/src/arch/x86/isa/microops/fpop.isa Fri Jun 28 09:13:27 2013 +0100 @@ -267,7 +267,6 @@ class Movfp(FpUnaryOp): code = 'FpDestReg_uqw = FpSrcReg1_uqw;' - else_code = 'FpDestReg_uqw = FpDestReg_uqw;' cond_check = "checkCondition(ccFlagBits | cfofBits | dfBit | \ ecfBit | ezfBit, src2)" diff -r cec988a3082e -r 5523750ec6fe src/arch/x86/isa/microops/mediaop.isa --- a/src/arch/x86/isa/microops/mediaop.isa Fri Jun 28 08:50:25 2013 +0100 +++ b/src/arch/x86/isa/microops/mediaop.isa Fri Jun 28 09:13:27 2013 +0100 @@ -246,8 +246,6 @@ (offset + 1) * srcSize * 8 - 1, (offset + 0) * srcSize * 8); DestReg = merge(0, fpSrcReg1, destSize); - } else { - DestReg = DestReg; } ''' @@ -267,8 +265,6 @@ insertBits(FpDestReg_uqw, (offset + 1) * destSize * 8 - 1, (offset + 0) * destSize * 8, srcReg1); - } else { - FpDestReg_uqw = FpDestReg_uqw; } ''' diff -r cec988a3082e -r 5523750ec6fe src/arch/x86/isa/microops/regop.isa --- a/src/arch/x86/isa/microops/regop.isa Fri Jun 28 08:50:25 2013 +0100 +++ b/src/arch/x86/isa/microops/regop.isa Fri Jun 28 09:13:27 2013 +0100 @@ -714,7 +714,6 @@ class Mov(CondRegOp): code = 'DestReg = merge(SrcReg1, op2, dataSize)' - else_code = 'DestReg = DestReg;' # Shift instructions @@ -1170,7 +1169,7 @@ class Wrip(WrRegOp, CondRegOp): code = 'NRIP = psrc1 + sop2 + CSBase;' - else_code = "NRIP = NRIP;" + else_code = ";" class Wruflags(WrRegOp): code = ''' @@ -1671,10 +1670,6 @@ SegBaseDest = base; SegLimitDest = limit; SegAttrDest = attr; - } else { - SegBaseDest = SegBaseDest; - SegLimitDest = SegLimitDest; - SegAttrDest = SegAttrDest; } break; } diff -r cec988a3082e -r 5523750ec6fe src/arch/x86/isa/microops/seqop.isa --- a/src/arch/x86/isa/microops/seqop.isa Fri Jun 28 08:50:25 2013 +0100 +++ b/src/arch/x86/isa/microops/seqop.isa Fri Jun 28 09:13:27 2013 +0100 @@ -171,7 +171,7 @@ iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase", {"code": "nuIP = target;", - "else_code": "nuIP = nuIP;", + "else_code": ";", "cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \ ecfBit | ezfBit, cc)", "cond_control_flag_init": "flags[IsCondControl] = true"}) @@ -180,7 +180,7 @@ decoder_output += SeqOpConstructor.subst(iop) iop = InstObjParams("br", "MicroBranch", "SeqOpBase", {"code": "nuIP = target;", - "else_code": "nuIP = nuIP;", + "else_code": ";", "cond_test": "true", "cond_control_flag_init": ""}) exec_output += SeqOpExecute.subst(iop)