# HG changeset patch
# Parent 59c6f42dcb6da10576ccd9c856a130c5595254b6

diff -r 59c6f42dcb6d src/arch/x86/isa/decoder/one_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa	Sun Oct 20 17:29:46 2013 +0200
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa	Sun Oct 20 17:44:43 2013 +0200
@@ -381,6 +381,7 @@
                 default: UD2();
             }
         }
+
         format WarnUnimpl {
             0x19: decode OPCODE_OP_BOTTOM3 {
                 // The second parameter here should be of size b, but
@@ -393,8 +394,8 @@
                     0x3, 0x4: ret_far_real();
                     default: Inst::RET_FAR();
                 }
-                0x4: int3();
-                0x5: decode FullSystemInt default int_Ib() {
+                0x4: Inst::INT3();
+                0x5: decode FullSystemInt default Inst::INT(Ib) {
                     0: decode IMMEDIATE {
                         // Really only the LSB matters, but the decoder
                         // will sign extend it, and there's no easy way to
@@ -402,6 +403,8 @@
                         0xffffffffffffff80:
                             SyscallInst::int80('xc->syscall(Rax)',
                                  IsSyscall, IsNonSpeculative, IsSerializeAfter);
+
+                        default: Inst::INT(Ib);
                     }
                 }
                 0x6: decode MODE_SUBMODE {
diff -r 59c6f42dcb6d src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py	Sun Oct 20 17:29:46 2013 +0200
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py	Sun Oct 20 17:44:43 2013 +0200
@@ -221,6 +221,34 @@
 def macroop IRET_VIRT {
     panic "Virtual mode iret isn't implemented!"
 };
+
+def macroop INT3 {
+
+    limm t1, 0x03, dataSize=8
+
+    rdip t7
+
+    # Are we in long mode?
+    rdm5reg t5
+    andi t0, t5, 0xE, flags=(EZF,)
+    br rom_label("longModeSoftInterrupt"), flags=(CEZF,)
+    br rom_label("legacyModeInterrupt")
+};
+
+def macroop INT_I {
+
+    #load the byte-sized interrupt vector specified in the instruction
+    mov t1, t0, t0, dataSize=8
+    limm t1, imm, dataSize=1
+
+    rdip t7
+
+    # Are we in long mode?
+    rdm5reg t5
+    andi t0, t5, 0xE, flags=(EZF,)
+    br rom_label("longModeSoftInterrupt"), flags=(CEZF,)
+    br rom_label("legacyModeInterrupt")
+};
 '''
 #let {{
 #    class INT(Inst):