diff -r 8a9733ade4a4 -r 54906a1386ab src/arch/arm/isa/formats/branch.isa
--- a/src/arch/arm/isa/formats/branch.isa	Fri Aug 13 12:00:58 2010 -0500
+++ b/src/arch/arm/isa/formats/branch.isa	Fri Aug 13 12:01:19 2010 -0500
@@ -166,7 +166,7 @@
                                                   ((enable ? 1 : 0) << 9);
                             return new Cps(machInst, mods);
                         } else if ((op2 & 0xf0) == 0xf0) {
-                            return new WarnUnimplemented("dbg", machInst);
+                            return new Dbg(machInst);
                         } else {
                             switch (op2) {
                               case 0x0:
diff -r 8a9733ade4a4 -r 54906a1386ab src/arch/arm/isa/insts/misc.isa
--- a/src/arch/arm/isa/insts/misc.isa	Fri Aug 13 12:00:58 2010 -0500
+++ b/src/arch/arm/isa/insts/misc.isa	Fri Aug 13 12:01:19 2010 -0500
@@ -706,6 +706,15 @@
     decoder_output += BasicConstructor.subst(dmbIop)
     exec_output += PredOpExecute.subst(dmbIop)
 
+    dbgCode = '''
+    '''
+    dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
+                             {"code": dbgCode,
+                               "predicate_test": predicateTest})
+    header_output += BasicDeclare.subst(dbgIop)
+    decoder_output += BasicConstructor.subst(dbgIop)
+    exec_output += PredOpExecute.subst(dbgIop)
+
     cpsCode = '''
     uint32_t mode = bits(imm, 4, 0);
     uint32_t f = bits(imm, 5);