diff -r e895db06e69f -r 07db1338d0b2 src/cpu/ozone/cpu_impl.hh
--- a/src/cpu/ozone/cpu_impl.hh	Mon Jul 15 18:08:57 2013 -0400
+++ b/src/cpu/ozone/cpu_impl.hh	Wed Aug 07 15:24:58 2013 -0500
@@ -282,7 +282,7 @@
     assert(thread_num == 0);
 
     assert(_status == Idle);
-    notIdleFraction++;
+    notIdleFraction = 1;
     scheduleTickEvent(delay);
     _status = Running;
     if (thread.quiesceEvent && thread.quiesceEvent->scheduled())
@@ -300,7 +300,7 @@
     // @todo: Figure out how to initially set the status properly so
     // this is running.
 //    assert(_status == Running);
-    notIdleFraction--;
+    notIdleFraction = 0;
     unscheduleTickEvent();
     _status = Idle;
 }
diff -r e895db06e69f -r 07db1338d0b2 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc	Mon Jul 15 18:08:57 2013 -0400
+++ b/src/cpu/simple/atomic.cc	Wed Aug 07 15:24:58 2013 -0500
@@ -175,8 +175,10 @@
     if (thread->status() == ThreadContext::Active) {
         schedule(tickEvent, nextCycle());
         _status = BaseSimpleCPU::Running;
+        notIdleFraction = 1;
     } else {
         _status = BaseSimpleCPU::Idle;
+        notIdleFraction = 0;
     }
 
     system->totalNumInsts = 0;
@@ -244,7 +246,7 @@
     assert(_status == Idle);
     assert(!tickEvent.scheduled());
 
-    notIdleFraction++;
+    notIdleFraction = 1;
     numCycles += ticksToCycles(thread->lastActivate - thread->lastSuspend);
 
     //Make sure ticks are still on multiples of cycles
@@ -271,7 +273,7 @@
     if (tickEvent.scheduled())
         deschedule(tickEvent);
 
-    notIdleFraction--;
+    notIdleFraction = 0;
     _status = Idle;
 }
 
diff -r e895db06e69f -r 07db1338d0b2 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc	Mon Jul 15 18:08:57 2013 -0400
+++ b/src/cpu/simple/timing.cc	Wed Aug 07 15:24:58 2013 -0500
@@ -144,8 +144,10 @@
     if (thread->status() == ThreadContext::Active) {
         schedule(fetchEvent, nextCycle());
         _status = BaseSimpleCPU::Running;
+        notIdleFraction = 1;
     } else {
         _status = BaseSimpleCPU::Idle;
+        notIdleFraction = 0;
     }
 }
 
@@ -207,7 +209,7 @@
 
     assert(_status == Idle);
 
-    notIdleFraction++;
+    notIdleFraction = 1;
     _status = BaseSimpleCPU::Running;
 
     // kick things off by initiating the fetch of the next instruction
@@ -231,7 +233,7 @@
     // just change status to Idle... if status != Running,
     // completeInst() will not initiate fetch of next instruction.
 
-    notIdleFraction--;
+    notIdleFraction = 0;
     _status = Idle;
 }
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,5 +1,21 @@
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here
+Traceback (most recent call last):
+  File "<string>", line 1, in <module>
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/src/python/m5/main.py", line 387, in main
+    exec filecode in scope
+  File "tests/run.py", line 180, in <module>
+    execfile(joinpath(tests_root, 'configs', test_filename + '.py'))
+  File "tests/configs/tsunami-simple-atomic-dual.py", line 42, in <module>
+    num_cpus=2).create_root()
+  File "tests/configs/base_config.py", line 230, in create_root
+    system = self.create_system()
+  File "tests/configs/alpha_generic.py", line 62, in create_system
+    system = FSConfig.makeLinuxAlphaSystem(self.mem_mode, DDR3_1600_x64)
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/FSConfig.py", line 83, in makeLinuxAlphaSystem
+    self.disk0.childImage(mdesc.disk())
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/Benchmarks.py", line 55, in disk
+    return env.get('LINUX_IMAGE', disk('linux-latest.img'))
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 37, in disk
+    system()
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 59, in system
+    raise ImportError, "Can't find a path to system files."
+ImportError: Can't find a path to system files.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,15 +1,7 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:01:11
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
-      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: Entering event queue @ 0.  Starting simulation...
-info: Launching CPU 1 @ 97861500
-Exiting @ tick 1870325497500 because m5_exit instruction encountered
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,912 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  1.870336                       # Number of seconds simulated
-sim_ticks                                1870335643500                       # Number of ticks simulated
-final_tick                               1870335643500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1417566                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1417565                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            41981821830                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308248                       # Number of bytes of host memory used
-host_seconds                                    44.55                       # Real time elapsed on the host
-sim_insts                                    63154034                       # Number of instructions simulated
-sim_ops                                      63154034                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst           761216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         66693056                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2649600                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           110976                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           668672                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             70883520                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       761216                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       110976                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          872192                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7861504                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7861504                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             11894                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data           1042079                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41400                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1734                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             10448                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1107555                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          122836                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               122836                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              406994                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            35658336                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1416644                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               59335                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              357514                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                37898823                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         406994                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          59335                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             466329                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4203258                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4203258                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4203258                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             406994                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           35658336                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1416644                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              59335                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             357514                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42102082                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                             0                       # Total number of read requests seen
-system.physmem.writeReqs                            0                       # Total number of write requests seen
-system.physmem.cpureqs                              0                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                            0                       # Total number of bytes read from memory
-system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd                      0                       # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15                    0                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
-system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                               0                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                       0                       # Categorize read packet sizes
-system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::6                      0                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::mean             nan                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean            nan                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev            nan                       # Bytes accessed per row activation
-system.physmem.totQLat                              0                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat                         0                       # Sum of mem lat for all requests
-system.physmem.totBusLat                            0                       # Total cycles spent in databus access
-system.physmem.totBankLat                           0                       # Total cycles spent in bank access
-system.physmem.avgQLat                            nan                       # Average queueing delay per request
-system.physmem.avgBankLat                         nan                       # Average bank access latency per request
-system.physmem.avgBusLat                          nan                       # Average bus latency per request
-system.physmem.avgMemAccLat                       nan                       # Average memory access latency
-system.physmem.avgRdBW                           0.00                       # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                   0.00                       # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil                           0.00                       # Data bus utilization in percentage
-system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
-system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
-system.physmem.readRowHits                          0                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                     nan                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                             nan                       # Average gap between requests
-system.membus.throughput                     42160246                       # Throughput (bytes/s)
-system.membus.data_through_bus               78853810                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.l2c.tags.replacements                       1000626                       # number of replacements
-system.l2c.tags.tagsinuse                     65381.922487                       # Cycle average of tags in use
-system.l2c.tags.total_refs                         2464723                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                       1065768                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                          2.312626                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                     838081000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks        56158.706931                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst          4894.235246                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data          4134.598984                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst           174.423126                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data            19.958201                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks           0.856914                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst            0.074680                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data            0.063089                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst            0.002661                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data            0.000305                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total                0.997649                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst             873088                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             763068                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             101908                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              36743                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1774807                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          816628                       # number of Writeback hits
-system.l2c.Writeback_hits::total               816628                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             135                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              37                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 172                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            14                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data             9                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                23                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           166235                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            14287                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               180522                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              873088                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              929303                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              101908                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               51030                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1955329                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             873088                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             929303                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             101908                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              51030                       # number of overall hits
-system.l2c.overall_hits::total                1955329                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst            11894                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           926761                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             1734                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data              908                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               941297                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          2442                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           570                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              3012                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data           65                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          100                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total             165                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         115706                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           9662                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             125368                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst             11894                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data           1042467                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              1734                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             10570                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1066665                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            11894                       # number of overall misses
-system.l2c.overall_misses::cpu0.data          1042467                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             1734                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            10570                       # number of overall misses
-system.l2c.overall_misses::total              1066665                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.inst         884982                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data        1689829                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         103642                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data          37651                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2716104                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       816628                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           816628                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         2577                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          607                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            3184                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data           79                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          109                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total           188                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       281941                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        23949                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           305890                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          884982                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1971770                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          103642                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           61600                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             3021994                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         884982                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1971770                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         103642                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          61600                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            3021994                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.013440                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.548435                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.016731                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.024116                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.346561                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.947614                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.939044                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.945980                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.822785                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.917431                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.877660                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.410391                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.403441                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.409847                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.013440                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.528696                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.016731                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.171591                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.352967                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.013440                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.528696                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.016731                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.171591                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.352967                       # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               81316                       # number of writebacks
-system.l2c.writebacks::total                    81316                       # number of writebacks
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements                     41695                       # number of replacements
-system.iocache.tags.tagsinuse                     0.435438                       # Cycle average of tags in use
-system.iocache.tags.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                     41711                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle              1685787165017                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide       0.435438                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide      0.027215                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total            0.027215                       # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::tsunami.ide          175                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
-system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide        41727                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41727                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41727                       # number of overall misses
-system.iocache.overall_misses::total            41727                       # number of overall misses
-system.iocache.ReadReq_accesses::tsunami.ide          175                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41727                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41727                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41727                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41727                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41520                       # number of writebacks
-system.iocache.writebacks::total                41520                       # number of writebacks
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.cpu0.dtb.fetch_hits                          0                       # ITB hits
-system.cpu0.dtb.fetch_misses                        0                       # ITB misses
-system.cpu0.dtb.fetch_acv                           0                       # ITB acv
-system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     9154530                       # DTB read hits
-system.cpu0.dtb.read_misses                      7079                       # DTB read misses
-system.cpu0.dtb.read_acv                          152                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  508987                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5936899                       # DTB write hits
-system.cpu0.dtb.write_misses                      726                       # DTB write misses
-system.cpu0.dtb.write_acv                          99                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 189050                       # DTB write accesses
-system.cpu0.dtb.data_hits                    15091429                       # DTB hits
-system.cpu0.dtb.data_misses                      7805                       # DTB misses
-system.cpu0.dtb.data_acv                          251                       # DTB access violations
-system.cpu0.dtb.data_accesses                  698037                       # DTB accesses
-system.cpu0.itb.fetch_hits                    3855556                       # ITB hits
-system.cpu0.itb.fetch_misses                     3485                       # ITB misses
-system.cpu0.itb.fetch_acv                         127                       # ITB acv
-system.cpu0.itb.fetch_accesses                3859041                       # ITB accesses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.read_acv                            0                       # DTB read access violations
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.write_acv                           0                       # DTB write access violations
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.data_hits                           0                       # DTB hits
-system.cpu0.itb.data_misses                         0                       # DTB misses
-system.cpu0.itb.data_acv                            0                       # DTB access violations
-system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                      3740671175                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   57222076                       # Number of instructions committed
-system.cpu0.committedOps                     57222076                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             53249924                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                299810                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1399585                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      6808233                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    53249924                       # number of integer instructions
-system.cpu0.num_fp_insts                       299810                       # number of float instructions
-system.cpu0.num_int_register_reads           73318596                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          39827534                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              147724                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             150835                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     15135515                       # number of memory refs
-system.cpu0.num_load_insts                    9184477                       # Number of load instructions
-system.cpu0.num_store_insts                   5951038                       # Number of store instructions
-system.cpu0.num_idle_cycles              3683437331.313678                       # Number of idle cycles
-system.cpu0.num_busy_cycles              57233843.686322                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.015300                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.984700                       # Percentage of idle cycles
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6283                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    197120                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   71004     40.60%     40.60% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    243      0.14%     40.74% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1908      1.09%     41.83% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                      8      0.00%     41.84% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 101705     58.16%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              174868                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    69637     49.24%     49.24% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     243      0.17%     49.41% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1908      1.35%     50.76% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                       8      0.01%     50.77% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   69629     49.23%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               141425                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1852989887500     99.07%     99.07% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               20110000      0.00%     99.07% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22               82044000      0.00%     99.08% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30                 949500      0.00%     99.08% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            17242445000      0.92%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1870335436000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.980748                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.684617                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.808753                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2                         6      2.65%      2.65% # number of syscalls executed
-system.cpu0.kern.syscall::3                        19      8.41%     11.06% # number of syscalls executed
-system.cpu0.kern.syscall::4                         2      0.88%     11.95% # number of syscalls executed
-system.cpu0.kern.syscall::6                        32     14.16%     26.11% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.44%     26.55% # number of syscalls executed
-system.cpu0.kern.syscall::15                        1      0.44%     26.99% # number of syscalls executed
-system.cpu0.kern.syscall::17                        9      3.98%     30.97% # number of syscalls executed
-system.cpu0.kern.syscall::19                        8      3.54%     34.51% # number of syscalls executed
-system.cpu0.kern.syscall::20                        6      2.65%     37.17% # number of syscalls executed
-system.cpu0.kern.syscall::23                        2      0.88%     38.05% # number of syscalls executed
-system.cpu0.kern.syscall::24                        4      1.77%     39.82% # number of syscalls executed
-system.cpu0.kern.syscall::33                        7      3.10%     42.92% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      0.88%     43.81% # number of syscalls executed
-system.cpu0.kern.syscall::45                       37     16.37%     60.18% # number of syscalls executed
-system.cpu0.kern.syscall::47                        4      1.77%     61.95% # number of syscalls executed
-system.cpu0.kern.syscall::48                        8      3.54%     65.49% # number of syscalls executed
-system.cpu0.kern.syscall::54                       10      4.42%     69.91% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.44%     70.35% # number of syscalls executed
-system.cpu0.kern.syscall::59                        4      1.77%     72.12% # number of syscalls executed
-system.cpu0.kern.syscall::71                       30     13.27%     85.40% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.33%     86.73% # number of syscalls executed
-system.cpu0.kern.syscall::74                        8      3.54%     90.27% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.44%     90.71% # number of syscalls executed
-system.cpu0.kern.syscall::90                        2      0.88%     91.59% # number of syscalls executed
-system.cpu0.kern.syscall::92                        9      3.98%     95.58% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      0.88%     96.46% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      0.88%     97.35% # number of syscalls executed
-system.cpu0.kern.syscall::132                       2      0.88%     98.23% # number of syscalls executed
-system.cpu0.kern.syscall::144                       2      0.88%     99.12% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      0.88%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   226                       # number of syscalls executed
-system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  110      0.06%      0.06% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.06% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.06% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.06% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3762      2.05%      2.11% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      38      0.02%      2.14% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.14% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               168035     91.68%     93.82% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6150      3.36%     97.17% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.17% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     3      0.00%     97.17% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     7      0.00%     97.18% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     97.18% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4673      2.55%     99.73% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 357      0.19%     99.92% # number of callpals executed
-system.cpu0.kern.callpal::imb                     142      0.08%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                183291                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             7091                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1158                       # number of protection mode switches
-system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1157                      
-system.cpu0.kern.mode_good::user                 1158                      
-system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.163165                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.280640                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1869378426000     99.95%     99.95% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user           957009000      0.05%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3763                       # number of times the context was actually changed
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.toL2Bus.throughput                   131930075                       # Throughput (bytes/s)
-system.toL2Bus.data_through_bus             246743154                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus           10368                       # Total snoop data (bytes)
-system.iobus.throughput                       1460500                       # Throughput (bytes/s)
-system.iobus.data_through_bus                 2731626                       # Total data (bytes)
-system.cpu0.icache.tags.replacements                884406                       # number of replacements
-system.cpu0.icache.tags.tagsinuse               511.244754                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs                56345130                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs                884918                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs                 63.672713                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle            9786576500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.244754                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998525                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total        0.998525                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst     56345130                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       56345130                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     56345130                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        56345130                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     56345130                       # number of overall hits
-system.cpu0.icache.overall_hits::total       56345130                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       885002                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       885002                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       885002                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        885002                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       885002                       # number of overall misses
-system.cpu0.icache.overall_misses::total       885002                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     57230132                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     57230132                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     57230132                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     57230132                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     57230132                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     57230132                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015464                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.015464                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015464                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.015464                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015464                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.015464                       # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements               1978683                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse               507.129817                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs                13123756                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs               1979195                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs                  6.630855                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle              10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   507.129817                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.990488                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total        0.990488                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      7298341                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7298341                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      5462261                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5462261                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       172144                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       172144                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       186623                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       186623                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     12760602                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12760602                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     12760602                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12760602                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1683328                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1683328                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       286000                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       286000                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        16153                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        16153                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data          715                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total          715                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1969328                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1969328                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1969328                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1969328                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      8981669                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8981669                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5748261                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5748261                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       188297                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       188297                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       187338                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       187338                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     14729930                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     14729930                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     14729930                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     14729930                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.187418                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.187418                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049754                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.049754                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.085785                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.085785                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.003817                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.003817                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.133696                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.133696                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.133696                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.133696                       # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       775614                       # number of writebacks
-system.cpu0.dcache.writebacks::total           775614                       # number of writebacks
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dtb.fetch_hits                          0                       # ITB hits
-system.cpu1.dtb.fetch_misses                        0                       # ITB misses
-system.cpu1.dtb.fetch_acv                           0                       # ITB acv
-system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     1163439                       # DTB read hits
-system.cpu1.dtb.read_misses                      3277                       # DTB read misses
-system.cpu1.dtb.read_acv                           58                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  220342                       # DTB read accesses
-system.cpu1.dtb.write_hits                     751446                       # DTB write hits
-system.cpu1.dtb.write_misses                      415                       # DTB write misses
-system.cpu1.dtb.write_acv                          58                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 103280                       # DTB write accesses
-system.cpu1.dtb.data_hits                     1914885                       # DTB hits
-system.cpu1.dtb.data_misses                      3692                       # DTB misses
-system.cpu1.dtb.data_acv                          116                       # DTB access violations
-system.cpu1.dtb.data_accesses                  323622                       # DTB accesses
-system.cpu1.itb.fetch_hits                    1468399                       # ITB hits
-system.cpu1.itb.fetch_misses                     1539                       # ITB misses
-system.cpu1.itb.fetch_acv                          57                       # ITB acv
-system.cpu1.itb.fetch_accesses                1469938                       # ITB accesses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.read_acv                            0                       # DTB read access violations
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.write_acv                           0                       # DTB write access violations
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.data_hits                           0                       # DTB hits
-system.cpu1.itb.data_misses                         0                       # DTB misses
-system.cpu1.itb.data_acv                            0                       # DTB access violations
-system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                      3740249123                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                    5931958                       # Number of instructions committed
-system.cpu1.committedOps                      5931958                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses              5550578                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                 28590                       # Number of float alu accesses
-system.cpu1.num_func_calls                     182742                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts       577190                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                     5550578                       # number of integer instructions
-system.cpu1.num_fp_insts                        28590                       # number of float instructions
-system.cpu1.num_int_register_reads            7657288                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           4163275                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               17889                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              17683                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      1926244                       # number of memory refs
-system.cpu1.num_load_insts                    1170888                       # Number of load instructions
-system.cpu1.num_store_insts                    755356                       # Number of store instructions
-system.cpu1.num_idle_cycles              3734312432.077611                       # Number of idle cycles
-system.cpu1.num_busy_cycles              5936690.922389                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.001587                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.998413                       # Percentage of idle cycles
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2204                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     39554                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   10328     33.46%     33.46% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1907      6.18%     39.64% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    110      0.36%     40.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  18518     60.00%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               30863                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    10318     45.77%     45.77% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1907      8.46%     54.23% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     110      0.49%     54.72% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   10208     45.28%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                22543                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1859123129500     99.41%     99.41% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22               82001000      0.00%     99.42% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30               14064500      0.00%     99.42% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            10905353000      0.58%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1870124548000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.999032                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.551247                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.730422                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::2                         2      2.00%      2.00% # number of syscalls executed
-system.cpu1.kern.syscall::3                        11     11.00%     13.00% # number of syscalls executed
-system.cpu1.kern.syscall::4                         2      2.00%     15.00% # number of syscalls executed
-system.cpu1.kern.syscall::6                        10     10.00%     25.00% # number of syscalls executed
-system.cpu1.kern.syscall::17                        6      6.00%     31.00% # number of syscalls executed
-system.cpu1.kern.syscall::19                        2      2.00%     33.00% # number of syscalls executed
-system.cpu1.kern.syscall::23                        2      2.00%     35.00% # number of syscalls executed
-system.cpu1.kern.syscall::24                        2      2.00%     37.00% # number of syscalls executed
-system.cpu1.kern.syscall::33                        4      4.00%     41.00% # number of syscalls executed
-system.cpu1.kern.syscall::45                       17     17.00%     58.00% # number of syscalls executed
-system.cpu1.kern.syscall::47                        2      2.00%     60.00% # number of syscalls executed
-system.cpu1.kern.syscall::48                        2      2.00%     62.00% # number of syscalls executed
-system.cpu1.kern.syscall::59                        3      3.00%     65.00% # number of syscalls executed
-system.cpu1.kern.syscall::71                       24     24.00%     89.00% # number of syscalls executed
-system.cpu1.kern.syscall::74                        8      8.00%     97.00% # number of syscalls executed
-system.cpu1.kern.syscall::90                        1      1.00%     98.00% # number of syscalls executed
-system.cpu1.kern.syscall::132                       2      2.00%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                   100                       # number of syscalls executed
-system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                    8      0.02%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                  470      1.46%      1.50% # number of callpals executed
-system.cpu1.kern.callpal::tbi                      15      0.05%      1.54% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.02%      1.57% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                26238     81.66%     83.22% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2576      8.02%     91.24% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     91.25% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     4      0.01%     91.26% # number of callpals executed
-system.cpu1.kern.callpal::rdusp                     2      0.01%     91.26% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.01%     91.27% # number of callpals executed
-system.cpu1.kern.callpal::rti                    2607      8.11%     99.39% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 158      0.49%     99.88% # number of callpals executed
-system.cpu1.kern.callpal::imb                      38      0.12%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 32131                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             1033                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                580                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2046                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                612                      
-system.cpu1.kern.mode_good::user                  580                      
-system.cpu1.kern.mode_good::idle                   32                      
-system.cpu1.kern.mode_switch_good::kernel     0.592449                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.015640                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.334518                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        1373906500      0.07%      0.07% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user           508289000      0.03%      0.10% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1868002681000     99.90%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                     471                       # number of times the context was actually changed
-system.cpu1.icache.tags.replacements                103103                       # number of replacements
-system.cpu1.icache.tags.tagsinuse               427.126317                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs                 5832124                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs                103615                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs                 56.286484                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle          1868933191000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   427.126317                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.834231                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total        0.834231                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst      5832124                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        5832124                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      5832124                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         5832124                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      5832124                       # number of overall hits
-system.cpu1.icache.overall_hits::total        5832124                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       103642                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       103642                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       103642                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        103642                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       103642                       # number of overall misses
-system.cpu1.icache.overall_misses::total       103642                       # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      5935766                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      5935766                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      5935766                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      5935766                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      5935766                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      5935766                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.017461                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.017461                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.017461                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.017461                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.017461                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.017461                       # miss rate for overall accesses
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements                 62052                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse               421.569557                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs                 1836045                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs                 62390                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs                 29.428514                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle          1851115695500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   421.569557                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.823378                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total        0.823378                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data      1109514                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1109514                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data       707455                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total        707455                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        15133                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        15133                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        15610                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        15610                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      1816969                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         1816969                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      1816969                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        1816969                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data        41451                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total        41451                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        25850                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        25850                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         1285                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         1285                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data          735                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total          735                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data        67301                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total         67301                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data        67301                       # number of overall misses
-system.cpu1.dcache.overall_misses::total        67301                       # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      1150965                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      1150965                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data       733305                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total       733305                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        16418                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        16418                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        16345                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        16345                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      1884270                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      1884270                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      1884270                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      1884270                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036014                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.036014                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.035251                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.035251                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.078268                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.078268                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.044968                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.044968                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.035717                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.035717                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035717                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.035717                       # miss rate for overall accesses
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks        41014                       # number of writebacks
-system.cpu1.dcache.writebacks::total            41014                       # number of writebacks
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,5 +1,21 @@
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here
+Traceback (most recent call last):
+  File "<string>", line 1, in <module>
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/src/python/m5/main.py", line 387, in main
+    exec filecode in scope
+  File "tests/run.py", line 180, in <module>
+    execfile(joinpath(tests_root, 'configs', test_filename + '.py'))
+  File "tests/configs/tsunami-simple-atomic.py", line 42, in <module>
+    cpu_class=AtomicSimpleCPU).create_root()
+  File "tests/configs/base_config.py", line 230, in create_root
+    system = self.create_system()
+  File "tests/configs/alpha_generic.py", line 62, in create_system
+    system = FSConfig.makeLinuxAlphaSystem(self.mem_mode, DDR3_1600_x64)
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/FSConfig.py", line 83, in makeLinuxAlphaSystem
+    self.disk0.childImage(mdesc.disk())
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/Benchmarks.py", line 55, in disk
+    return env.get('LINUX_IMAGE', disk('linux-latest.img'))
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 37, in disk
+    system()
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 59, in system
+    raise ImportError, "Can't find a path to system files."
+ImportError: Can't find a path to system files.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,14 +1,7 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:01:49
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
-      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1829330593000 because m5_exit instruction encountered
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,608 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  1.829332                       # Number of seconds simulated
-sim_ticks                                1829332269000                       # Number of ticks simulated
-final_tick                               1829332269000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1710493                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1710492                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            52117657653                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 306192                       # Number of bytes of host memory used
-host_seconds                                    35.10                       # Real time elapsed on the host
-sim_insts                                    60038305                       # Number of instructions simulated
-sim_ops                                      60038305                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            857984                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          66839424                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             70349696                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       857984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          857984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7411392                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7411392                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              13406                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1044366                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1099214                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          115803                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115803                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               469015                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             36537607                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1449867                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                38456489                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          469015                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             469015                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4051419                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4051419                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4051419                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              469015                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            36537607                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1449867                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42507908                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                             0                       # Total number of read requests seen
-system.physmem.writeReqs                            0                       # Total number of write requests seen
-system.physmem.cpureqs                              0                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                            0                       # Total number of bytes read from memory
-system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd                      0                       # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15                    0                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
-system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                               0                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                       0                       # Categorize read packet sizes
-system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::6                      0                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::mean             nan                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean            nan                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev            nan                       # Bytes accessed per row activation
-system.physmem.totQLat                              0                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat                         0                       # Sum of mem lat for all requests
-system.physmem.totBusLat                            0                       # Total cycles spent in databus access
-system.physmem.totBankLat                           0                       # Total cycles spent in bank access
-system.physmem.avgQLat                            nan                       # Average queueing delay per request
-system.physmem.avgBankLat                         nan                       # Average bank access latency per request
-system.physmem.avgBusLat                          nan                       # Average bus latency per request
-system.physmem.avgMemAccLat                       nan                       # Average memory access latency
-system.physmem.avgRdBW                           0.00                       # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                   0.00                       # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil                           0.00                       # Data bus utilization in percentage
-system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
-system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
-system.physmem.readRowHits                          0                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                     nan                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                             nan                       # Average gap between requests
-system.membus.throughput                     42552540                       # Throughput (bytes/s)
-system.membus.data_through_bus               77842734                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.iocache.tags.replacements                     41686                       # number of replacements
-system.iocache.tags.tagsinuse                     1.225570                       # Cycle average of tags in use
-system.iocache.tags.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                     41702                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle              1685780659017                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide       1.225570                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide      0.076598                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total            0.076598                       # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
-system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide        41726                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41726                       # number of overall misses
-system.iocache.overall_misses::total            41726                       # number of overall misses
-system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41726                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41512                       # number of writebacks
-system.iocache.writebacks::total                41512                       # number of writebacks
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9710427                       # DTB read hits
-system.cpu.dtb.read_misses                      10329                       # DTB read misses
-system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_accesses                   728856                       # DTB read accesses
-system.cpu.dtb.write_hits                     6352498                       # DTB write hits
-system.cpu.dtb.write_misses                      1142                       # DTB write misses
-system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
-system.cpu.dtb.data_hits                     16062925                       # DTB hits
-system.cpu.dtb.data_misses                      11471                       # DTB misses
-system.cpu.dtb.data_acv                           367                       # DTB access violations
-system.cpu.dtb.data_accesses                  1020787                       # DTB accesses
-system.cpu.itb.fetch_hits                     4974648                       # ITB hits
-system.cpu.itb.fetch_misses                      5006                       # ITB misses
-system.cpu.itb.fetch_acv                          184                       # ITB acv
-system.cpu.itb.fetch_accesses                 4979654                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                       3658664430                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    60038305                       # Number of instructions committed
-system.cpu.committedOps                      60038305                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              55913521                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
-system.cpu.num_func_calls                     1484182                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7110746                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     55913521                       # number of integer instructions
-system.cpu.num_fp_insts                        324460                       # number of float instructions
-system.cpu.num_int_register_reads            76953934                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           41740225                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      16115709                       # number of memory refs
-system.cpu.num_load_insts                     9747513                       # Number of load instructions
-system.cpu.num_store_insts                    6368196                       # Number of store instructions
-system.cpu.num_idle_cycles               3598609001.180807                       # Number of idle cycles
-system.cpu.num_busy_cycles               60055428.819193                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.016415                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.983585                       # Percentage of idle cycles
-system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6357                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211319                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74830     40.99%     40.99% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     243      0.13%     41.12% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1866      1.02%     42.14% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105623     57.86%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182562                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73463     49.29%     49.29% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      243      0.16%     49.46% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1866      1.25%     50.71% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73463     49.29%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149035                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1811927418500     99.05%     99.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                20110000      0.00%     99.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22                80238000      0.00%     99.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             17304295000      0.95%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1829332061500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981732                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.695521                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.816353                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
-system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
-system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
-system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
-system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
-system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
-system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
-system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
-system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
-system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
-system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
-system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
-system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
-system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
-system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
-system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
-system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
-system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
-system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
-system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
-system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
-system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
-system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
-system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
-system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
-system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
-system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
-system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
-system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
-system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
-system.cpu.kern.syscall::total                    326                       # number of syscalls executed
-system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4177      2.17%      2.18% # number of callpals executed
-system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
-system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175249     91.19%     93.40% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6771      3.52%     96.92% # number of callpals executed
-system.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
-system.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
-system.cpu.kern.callpal::rdusp                      9      0.00%     96.93% # number of callpals executed
-system.cpu.kern.callpal::whami                      2      0.00%     96.93% # number of callpals executed
-system.cpu.kern.callpal::rti                     5203      2.71%     99.64% # number of callpals executed
-system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
-system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192180                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5949                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1909                      
-system.cpu.kern.mode_good::user                  1738                      
-system.cpu.kern.mode_good::idle                   171                      
-system.cpu.kern.mode_switch_good::kernel     0.320894                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081545                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.390229                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        26834202500      1.47%      1.47% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           1465074000      0.08%      1.55% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1801032784000     98.45%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.iobus.throughput                       1480181                       # Throughput (bytes/s)
-system.iobus.data_through_bus                 2707742                       # Total data (bytes)
-system.cpu.icache.tags.replacements                 919609                       # number of replacements
-system.cpu.icache.tags.tagsinuse                511.215244                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 59129907                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                 920121                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                  64.263186                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle             9686972500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     511.215244                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.998467                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.998467                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     59129907                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        59129907                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      59129907                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         59129907                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     59129907                       # number of overall hits
-system.cpu.icache.overall_hits::total        59129907                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       920236                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        920236                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       920236                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         920236                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       920236                       # number of overall misses
-system.cpu.icache.overall_misses::total        920236                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     60050143                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     60050143                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     60050143                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     60050143                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     60050143                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     60050143                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015324                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.015324                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.015324                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.015324                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.015324                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.015324                       # miss rate for overall accesses
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                992301                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse             65424.374219                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                 2433263                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs               1057464                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  2.301036                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle             614754000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 56309.127841                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   4867.327126                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   4247.919252                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.859209                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.074270                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.064818                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.998297                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst       906812                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       811232                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1718044                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       833497                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       833497                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187230                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187230                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       906812                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       998462                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1905274                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       906812                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       998462                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1905274                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst        13406                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       927640                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       941046                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           12                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           12                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       117117                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       117117                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        13406                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1044757                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1058163                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        13406                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1044757                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1058163                       # number of overall misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       920218                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1738872                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2659090                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       833497                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       833497                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           16                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           16                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       304347                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       304347                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       920218                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2043219                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2963437                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       920218                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2043219                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2963437                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014568                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.533472                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.353898                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.750000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.750000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384814                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.384814                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014568                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.511329                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.357073                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014568                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.511329                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.357073                       # miss rate for overall accesses
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        74291                       # number of writebacks
-system.cpu.l2cache.writebacks::total            74291                       # number of writebacks
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                2042706                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                511.997802                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                 14038427                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                2043218                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                   6.870744                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle               10840000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data     511.997802                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.999996                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.999996                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data      7807777                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7807777                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5848211                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5848211                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       183141                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183141                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199282                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199282                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13655988                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13655988                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13655988                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13655988                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1721710                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1721710                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304363                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304363                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17162                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17162                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2026073                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2026073                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2026073                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2026073                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data      9529487                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9529487                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6152574                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6152574                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200303                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200303                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199282                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199282                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15682061                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15682061                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15682061                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15682061                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180672                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.180672                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049469                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049469                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085680                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085680                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.129197                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.129197                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.129197                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.129197                       # miss rate for overall accesses
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       833497                       # number of writebacks
-system.cpu.dcache.writebacks::total            833497                       # number of writebacks
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               132868790                       # Throughput (bytes/s)
-system.cpu.toL2Bus.data_through_bus         243051054                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus        10112                       # Total snoop data (bytes)
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,5 +1,21 @@
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here
+Traceback (most recent call last):
+  File "<string>", line 1, in <module>
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/src/python/m5/main.py", line 387, in main
+    exec filecode in scope
+  File "tests/run.py", line 180, in <module>
+    execfile(joinpath(tests_root, 'configs', test_filename + '.py'))
+  File "tests/configs/tsunami-simple-timing-dual.py", line 42, in <module>
+    num_cpus=2).create_root()
+  File "tests/configs/base_config.py", line 230, in create_root
+    system = self.create_system()
+  File "tests/configs/alpha_generic.py", line 62, in create_system
+    system = FSConfig.makeLinuxAlphaSystem(self.mem_mode, DDR3_1600_x64)
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/FSConfig.py", line 83, in makeLinuxAlphaSystem
+    self.disk0.childImage(mdesc.disk())
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/Benchmarks.py", line 55, in disk
+    return env.get('LINUX_IMAGE', disk('linux-latest.img'))
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 37, in disk
+    system()
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 59, in system
+    raise ImportError, "Can't find a path to system files."
+ImportError: Can't find a path to system files.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,15 +1,7 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 14:39:13
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
-      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: Entering event queue @ 0.  Starting simulation...
-info: Launching CPU 1 @ 614109000
-Exiting @ tick 1955749107000 because m5_exit instruction encountered
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,1645 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  1.961841                       # Number of seconds simulated
-sim_ticks                                1961841175000                       # Number of ticks simulated
-final_tick                               1961841175000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1094895                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1094895                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            36191186298                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308248                       # Number of bytes of host memory used
-host_seconds                                    54.21                       # Real time elapsed on the host
-sim_insts                                    59351715                       # Number of instructions simulated
-sim_ops                                      59351715                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst           831360                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24914752                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2650816                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            32192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           287808                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28716928                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       831360                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        32192                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          863552                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7746368                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7746368                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             12990                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            389293                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41419                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst               503                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              4497                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                448702                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          121037                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               121037                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              423765                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12699678                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1351188                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               16409                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              146703                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14637744                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         423765                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          16409                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             440174                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3948519                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3948519                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3948519                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             423765                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12699678                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1351188                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              16409                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             146703                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18586263                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        448702                       # Total number of read requests seen
-system.physmem.writeReqs                       121037                       # Total number of write requests seen
-system.physmem.cpureqs                         572905                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                     28716928                       # Total number of bytes read from memory
-system.physmem.bytesWritten                   7746368                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd               28716928                       # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr                7746368                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                       73                       # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite               3165                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                 27842                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                 28115                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                 28314                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                 28019                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                 27858                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                 28118                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                 27836                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                 27466                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                 27905                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                 27953                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10                27826                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11                28040                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12                28428                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13                28581                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14                28092                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15                28236                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                  7663                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1                  7614                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2                  7774                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3                  7534                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4                  7350                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5                  7579                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6                  7314                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                  6876                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8                  7222                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9                  7326                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10                 7279                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11                 7591                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12                 7943                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13                 8207                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14                 7875                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15                 7890                       # Track writes on a per bank basis
-system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry                           1                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                    1961833946000                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                  448702                       # Categorize read packet sizes
-system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::6                 121037                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                    407897                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      7065                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      5297                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      3282                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      3277                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      2995                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      1539                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1507                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1468                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1448                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1445                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1437                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1400                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     2065                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     2339                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     2218                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                     1196                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      434                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      219                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       99                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      3809                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      3916                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      4987                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      5260                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      5261                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      5262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      5262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      5262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      5262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      5263                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     5263                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     5262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     5262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     5262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     5262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     5262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     5262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     1454                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     1347                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                      276                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        1                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        39515                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      922.589599                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     226.543369                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev    2381.494153                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-67          13878     35.12%     35.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-131         6056     15.33%     50.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-195         3741      9.47%     59.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-259         2391      6.05%     65.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-323         1744      4.41%     70.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-387         1425      3.61%     73.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-451         1039      2.63%     76.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-515          750      1.90%     78.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-579          668      1.69%     80.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-643          592      1.50%     81.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-707          528      1.34%     83.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-771          459      1.16%     84.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-835          301      0.76%     84.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-899          245      0.62%     85.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-963          187      0.47%     86.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1027          264      0.67%     86.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1091          137      0.35%     87.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1155          111      0.28%     87.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1219           92      0.23%     87.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1283           96      0.24%     87.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1347           88      0.22%     88.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1411          105      0.27%     88.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1475         1100      2.78%     91.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1539          187      0.47%     91.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1603          132      0.33%     91.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1667           88      0.22%     92.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1731           54      0.14%     92.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1795           43      0.11%     92.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1859           23      0.06%     92.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1923           21      0.05%     92.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1987           20      0.05%     92.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2051           29      0.07%     92.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2115           19      0.05%     92.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2179           11      0.03%     92.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2243           14      0.04%     92.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2307            4      0.01%     92.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2371            9      0.02%     92.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2435            6      0.02%     92.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2499            1      0.00%     92.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2563            3      0.01%     92.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2627            5      0.01%     92.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2691            3      0.01%     92.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2755            1      0.00%     92.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2819            6      0.02%     92.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2883            5      0.01%     92.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2947            2      0.01%     92.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3075            2      0.01%     92.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3139            2      0.01%     92.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3203            1      0.00%     92.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3267            2      0.01%     92.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3331            4      0.01%     92.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3395            4      0.01%     92.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3459            2      0.01%     92.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3587            3      0.01%     92.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3715            1      0.00%     92.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3779            2      0.01%     92.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3843            1      0.00%     92.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3971            3      0.01%     92.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4035            2      0.01%     92.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4099            1      0.00%     92.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4163            3      0.01%     92.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4227            2      0.01%     92.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4291            1      0.00%     92.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4355            4      0.01%     92.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4419            1      0.00%     92.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4483            2      0.01%     92.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4547            1      0.00%     92.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4675            1      0.00%     92.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4739            1      0.00%     92.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4803            1      0.00%     92.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4867            1      0.00%     92.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4931            1      0.00%     92.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5571            1      0.00%     92.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5763            2      0.01%     92.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6147            3      0.01%     92.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6403            1      0.00%     92.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6787            1      0.00%     92.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6851            1      0.00%     92.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7171            2      0.01%     92.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7235            1      0.00%     92.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7299            2      0.01%     92.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7363            1      0.00%     93.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7555            1      0.00%     93.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7619            2      0.01%     93.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7683            2      0.01%     93.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7747            1      0.00%     93.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7811            1      0.00%     93.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7939            2      0.01%     93.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8003            3      0.01%     93.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8131            6      0.02%     93.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8195         2432      6.15%     99.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8256-8259            1      0.00%     99.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8384-8387            2      0.01%     99.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12352-12355            1      0.00%     99.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12416-12419            1      0.00%     99.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13059            1      0.00%     99.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13696-13699            1      0.00%     99.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13824-13827            1      0.00%     99.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14016-14019            1      0.00%     99.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14272-14275            3      0.01%     99.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14400-14403            1      0.00%     99.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14528-14531            2      0.01%     99.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14595            1      0.00%     99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14784-14787            1      0.00%     99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15107            2      0.01%     99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15296-15299            2      0.01%     99.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15363           16      0.04%     99.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15488-15491            2      0.01%     99.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16192-16195            1      0.00%     99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16387          242      0.61%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16448-16451           10      0.03%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16512-16515            6      0.02%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16576-16579            1      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16640-16643            6      0.02%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16704-16707            4      0.01%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16768-16771            1      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16832-16835            1      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16960-16963            2      0.01%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17024-17027            4      0.01%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17984-17987            1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          39515                       # Bytes accessed per row activation
-system.physmem.totQLat                     3750140000                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat               12006448750                       # Sum of mem lat for all requests
-system.physmem.totBusLat                   2243145000                       # Total cycles spent in databus access
-system.physmem.totBankLat                  6013163750                       # Total cycles spent in bank access
-system.physmem.avgQLat                        8359.11                       # Average queueing delay per request
-system.physmem.avgBankLat                    13403.42                       # Average bank access latency per request
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
-system.physmem.avgMemAccLat                  26762.53                       # Average memory access latency
-system.physmem.avgRdBW                          14.64                       # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW                           3.95                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                  14.64                       # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW                   3.95                       # Average consumed write bandwidth in MB/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
-system.physmem.avgRdQLen                         0.01                       # Average read queue length over time
-system.physmem.avgWrQLen                         6.90                       # Average write queue length over time
-system.physmem.readRowHits                     433153                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     96987                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   96.55                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.13                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3443390.65                       # Average gap between requests
-system.membus.throughput                     18639952                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              292620                       # Transaction distribution
-system.membus.trans_dist::ReadResp             292620                       # Transaction distribution
-system.membus.trans_dist::WriteReq              12397                       # Transaction distribution
-system.membus.trans_dist::WriteResp             12397                       # Transaction distribution
-system.membus.trans_dist::Writeback            121037                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4186                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq            858                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            3168                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            163944                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           163855                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        39192                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       902644                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       941836                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124669                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124669                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.bridge.slave        39192                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.physmem.port      1027313                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1066505                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        68594                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     31155200                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     31223794                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5308096                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      5308096                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.bridge.slave        68594                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.physmem.port     36463296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            36531890                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               36531890                       # Total data (bytes)
-system.membus.snoop_data_through_bus            36736                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            39129000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1559666750                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3812357322                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          376257250                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.l2c.tags.replacements                        341780                       # number of replacements
-system.l2c.tags.tagsinuse                     65282.130402                       # Cycle average of tags in use
-system.l2c.tags.total_refs                         2491702                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                        406958                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                          6.122750                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                    8422138750                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks        55415.399962                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst          4783.359658                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data          4905.357732                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst           160.897835                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data            17.115216                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks           0.845572                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst            0.072988                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data            0.074850                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst            0.002455                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data            0.000261                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total                0.996126                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst             908184                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             776732                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst              79667                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              28709                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1793292                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          820882                       # number of Writeback hits
-system.l2c.Writeback_hits::total               820882                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             160                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              41                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 201                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            18                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            18                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                36                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           176285                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data             7535                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               183820                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              908184                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              953017                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst               79667                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               36244                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1977112                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             908184                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             953017                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst              79667                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              36244                       # number of overall hits
-system.l2c.overall_hits::total                1977112                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst            12993                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           271572                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst              511                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data              178                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               285254                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          2440                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           483                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2923                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data           33                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data           73                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total             106                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         118111                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           4331                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             122442                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst             12993                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            389683                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst               511                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data              4509                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                407696                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            12993                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           389683                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst              511                       # number of overall misses
-system.l2c.overall_misses::cpu1.data             4509                       # number of overall misses
-system.l2c.overall_misses::total               407696                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst   1030661993                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  16900238244                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst     41124000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data     15490750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    17987514987                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data      1078963                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data       302487                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total      1381450                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data        69997                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data        92496                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total       162493                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   7866556623                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    326108488                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   8192665111                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   1030661993                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  24766794867                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst     41124000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    341599238                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     26180180098                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1030661993                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  24766794867                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst     41124000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    341599238                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    26180180098                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst         921177                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data        1048304                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst          80178                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data          28887                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2078546                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       820882                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           820882                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         2600                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          524                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            3124                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data           51                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data           91                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total           142                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       294396                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        11866                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           306262                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          921177                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1342700                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst           80178                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           40753                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2384808                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         921177                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1342700                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst          80178                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          40753                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2384808                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.014105                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.259058                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.006373                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.006162                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.137237                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.938462                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.921756                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.935659                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.647059                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.802198                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.746479                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.401198                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.364992                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.399795                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.014105                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.290223                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.006373                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.110642                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.170955                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.014105                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.290223                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.006373                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.110642                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.170955                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79324.404910                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 62231.151385                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80477.495108                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 87026.685393                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 63057.888713                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   442.197951                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   626.267081                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   472.613753                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2121.121212                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1267.068493                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  1532.952830                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66603.082041                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75296.349111                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 66910.578976                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 79324.404910                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 63556.262057                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 80477.495108                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 75759.422932                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 64214.954520                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 79324.404910                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 63556.262057                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 80477.495108                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 75759.422932                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 64214.954520                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               79517                       # number of writebacks
-system.l2c.writebacks::total                    79517                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst             3                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst             8                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              3                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              8                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             8                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst        12990                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data       271572                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst          503                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data          178                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          285243                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         2440                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          483                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2923                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           33                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           73                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total          106                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       118111                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         4331                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        122442                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        12990                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       389683                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst          503                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data         4509                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           407685                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        12990                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       389683                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst          503                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data         4509                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          407685                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    866381257                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data  13503893756                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     34165000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data     13232750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  14417672763                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     24556937                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      4864483                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     29421420                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       330033                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       730073                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total      1060106                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   6385916377                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    270944012                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   6656860389                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    866381257                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  19889810133                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     34165000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    284176762                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  21074533152                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    866381257                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  19889810133                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     34165000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    284176762                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  21074533152                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1373141500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     17611000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   1390752500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1974248000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    499178500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2473426500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3347389500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    516789500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   3864179000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014102                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.259058                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.006274                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.006162                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.137232                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.938462                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.921756                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.935659                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.647059                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.802198                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.746479                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.401198                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.364992                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.399795                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014102                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.290223                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.006274                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.110642                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.170951                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014102                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.290223                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.006274                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.110642                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.170951                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 66696.016705                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 49724.911832                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67922.465209                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74341.292135                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 50545.229026                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10064.318443                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10071.393375                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10065.487513                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54067.075692                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62559.226968                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 54367.458789                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66696.016705                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 51041.000334                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67922.465209                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63024.342870                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 51693.177703                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66696.016705                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51041.000334                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67922.465209                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63024.342870                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 51693.177703                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements                     41698                       # number of replacements
-system.iocache.tags.tagsinuse                     0.564923                       # Cycle average of tags in use
-system.iocache.tags.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                     41714                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle              1754539957000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide       0.564923                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide      0.035308                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total            0.035308                       # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::tsunami.ide          178                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              178                       # number of ReadReq misses
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-system.iocache.overall_misses::total            41730                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21912883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21912883                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide  10439154521                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  10439154521                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide  10461067404                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  10461067404                       # number of demand (read+write) miss cycles
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-system.iocache.overall_miss_latency::total  10461067404                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          178                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            178                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
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-system.iocache.demand_accesses::tsunami.ide        41730                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41730                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41730                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41730                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123106.084270                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 123106.084270                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251231.096482                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 251231.096482                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 250684.577139                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 250684.577139                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 250684.577139                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 250684.577139                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        274830                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                27442                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.014941                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41520                       # number of writebacks
-system.iocache.writebacks::total                41520                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          178                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          178                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41730                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41730                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41730                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41730                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12655383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12655383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   8277077521                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   8277077521                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   8289732904                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   8289732904                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   8289732904                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   8289732904                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71097.657303                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 71097.657303                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199198.053547                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 199198.053547                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198651.639204                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 198651.639204                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198651.639204                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 198651.639204                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.cpu0.dtb.fetch_hits                          0                       # ITB hits
-system.cpu0.dtb.fetch_misses                        0                       # ITB misses
-system.cpu0.dtb.fetch_acv                           0                       # ITB acv
-system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     8725663                       # DTB read hits
-system.cpu0.dtb.read_misses                      7765                       # DTB read misses
-system.cpu0.dtb.read_acv                          210                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  524069                       # DTB read accesses
-system.cpu0.dtb.write_hits                    6139453                       # DTB write hits
-system.cpu0.dtb.write_misses                      910                       # DTB write misses
-system.cpu0.dtb.write_acv                         133                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 202595                       # DTB write accesses
-system.cpu0.dtb.data_hits                    14865116                       # DTB hits
-system.cpu0.dtb.data_misses                      8675                       # DTB misses
-system.cpu0.dtb.data_acv                          343                       # DTB access violations
-system.cpu0.dtb.data_accesses                  726664                       # DTB accesses
-system.cpu0.itb.fetch_hits                    4015307                       # ITB hits
-system.cpu0.itb.fetch_misses                     3984                       # ITB misses
-system.cpu0.itb.fetch_acv                         184                       # ITB acv
-system.cpu0.itb.fetch_accesses                4019291                       # ITB accesses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.read_acv                            0                       # DTB read access violations
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.write_acv                           0                       # DTB write access violations
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.data_hits                           0                       # DTB hits
-system.cpu0.itb.data_misses                         0                       # DTB misses
-system.cpu0.itb.data_acv                            0                       # DTB access violations
-system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                      3923682350                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   54601969                       # Number of instructions committed
-system.cpu0.committedOps                     54601969                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             50544405                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                297630                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1438477                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      6291508                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    50544405                       # number of integer instructions
-system.cpu0.num_fp_insts                       297630                       # number of float instructions
-system.cpu0.num_int_register_reads           69247284                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          37427910                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              145753                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             148838                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     14912078                       # number of memory refs
-system.cpu0.num_load_insts                    8757685                       # Number of load instructions
-system.cpu0.num_store_insts                   6154393                       # Number of store instructions
-system.cpu0.num_idle_cycles              3674902109.498127                       # Number of idle cycles
-system.cpu0.num_busy_cycles              248780240.501873                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.063405                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.936595                       # Percentage of idle cycles
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6366                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    204697                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   73289     40.68%     40.68% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.07%     40.75% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1975      1.10%     41.85% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                      6      0.00%     41.85% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 104766     58.15%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              180167                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    71920     49.28%     49.28% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     131      0.09%     49.37% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1975      1.35%     50.72% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                       6      0.00%     50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   71914     49.27%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               145946                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1899196330000     96.81%     96.81% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               95025500      0.00%     96.81% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              769055500      0.04%     96.85% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30                5164500      0.00%     96.85% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            61774827500      3.15%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1961840403000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.981321                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.686425                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.810060                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2                         8      3.42%      3.42% # number of syscalls executed
-system.cpu0.kern.syscall::3                        20      8.55%     11.97% # number of syscalls executed
-system.cpu0.kern.syscall::4                         4      1.71%     13.68% # number of syscalls executed
-system.cpu0.kern.syscall::6                        33     14.10%     27.78% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.43%     28.21% # number of syscalls executed
-system.cpu0.kern.syscall::17                       10      4.27%     32.48% # number of syscalls executed
-system.cpu0.kern.syscall::19                       10      4.27%     36.75% # number of syscalls executed
-system.cpu0.kern.syscall::20                        6      2.56%     39.32% # number of syscalls executed
-system.cpu0.kern.syscall::23                        1      0.43%     39.74% # number of syscalls executed
-system.cpu0.kern.syscall::24                        3      1.28%     41.03% # number of syscalls executed
-system.cpu0.kern.syscall::33                        8      3.42%     44.44% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      0.85%     45.30% # number of syscalls executed
-system.cpu0.kern.syscall::45                       39     16.67%     61.97% # number of syscalls executed
-system.cpu0.kern.syscall::47                        3      1.28%     63.25% # number of syscalls executed
-system.cpu0.kern.syscall::48                       10      4.27%     67.52% # number of syscalls executed
-system.cpu0.kern.syscall::54                       10      4.27%     71.79% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.43%     72.22% # number of syscalls executed
-system.cpu0.kern.syscall::59                        6      2.56%     74.79% # number of syscalls executed
-system.cpu0.kern.syscall::71                       27     11.54%     86.32% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.28%     87.61% # number of syscalls executed
-system.cpu0.kern.syscall::74                        7      2.99%     90.60% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.43%     91.03% # number of syscalls executed
-system.cpu0.kern.syscall::90                        3      1.28%     92.31% # number of syscalls executed
-system.cpu0.kern.syscall::92                        9      3.85%     96.15% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      0.85%     97.01% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      0.85%     97.86% # number of syscalls executed
-system.cpu0.kern.syscall::132                       1      0.43%     98.29% # number of syscalls executed
-system.cpu0.kern.syscall::144                       2      0.85%     99.15% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      0.85%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   234                       # number of syscalls executed
-system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                   88      0.05%      0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.05% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3942      2.08%      2.13% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      51      0.03%      2.16% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.16% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               173212     91.45%     93.61% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6702      3.54%     97.15% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.15% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     4      0.00%     97.16% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     9      0.00%     97.16% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     97.16% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4842      2.56%     99.72% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 394      0.21%     99.93% # number of callpals executed
-system.cpu0.kern.callpal::imb                     139      0.07%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                189397                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             7440                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1369                       # number of protection mode switches
-system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1368                      
-system.cpu0.kern.mode_good::user                 1369                      
-system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.183871                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.310705                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1958025785500     99.81%     99.81% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          3814613000      0.19%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3943                       # number of times the context was actually changed
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.toL2Bus.throughput                   105075557                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2099191                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2099176                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             12397                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            12397                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           820882                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            4248                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq           894                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           5142                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           348581                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          307031                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side      1842377                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side      3534341                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side       160357                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side       115223                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count                      5652298                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side     58955328                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side    137106504                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side      5131392                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side      4050090                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size                 205243314                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             205232754                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus          908800                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         4911962990                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.3                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           742500                       # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4148559004                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        6195378103                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         360929992                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         206344318                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                       1391673                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq                 7377                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7377                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               53949                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              53949                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        10582                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2474                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        39192                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83460                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83460                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.cchip.pio        10582                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.backdoor.pio         2474                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side        83460                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  122652                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        42328                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9876                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total        68594                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661648                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661648                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.cchip.pio        42328                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.backdoor.pio         9876                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side      2661648                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              2730242                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 2730242                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              9937000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               359000                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            13505000                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy             2453000                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           378297154                       # Layer occupancy (ticks)
-system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
-system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            26795000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            43124750                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu0.icache.tags.replacements                920572                       # number of replacements
-system.cpu0.icache.tags.tagsinuse               508.501962                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs                53689788                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs                921084                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs                 58.289785                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle           39101383250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.501962                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.993168                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total        0.993168                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst     53689788                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       53689788                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     53689788                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        53689788                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     53689788                       # number of overall hits
-system.cpu0.icache.overall_hits::total       53689788                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       921200                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       921200                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       921200                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        921200                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       921200                       # number of overall misses
-system.cpu0.icache.overall_misses::total       921200                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  12937764004                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  12937764004                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  12937764004                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  12937764004                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  12937764004                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  12937764004                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     54610988                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     54610988                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     54610988                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     54610988                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     54610988                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     54610988                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016868                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.016868                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016868                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.016868                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016868                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.016868                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14044.468089                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14044.468089                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14044.468089                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14044.468089                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14044.468089                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14044.468089                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       921200                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       921200                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       921200                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       921200                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       921200                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       921200                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11089045996                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  11089045996                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11089045996                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  11089045996                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11089045996                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  11089045996                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.016868                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.016868                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.016868                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.016868                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.016868                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.016868                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12037.609635                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12037.609635                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12037.609635                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12037.609635                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12037.609635                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12037.609635                       # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements               1349865                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse               506.612721                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs                13528796                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs               1350377                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs                 10.018533                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle             105754250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.612721                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.989478                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total        0.989478                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      7507195                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7507195                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      5646858                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5646858                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       177791                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       177791                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       193304                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       193304                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     13154053                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        13154053                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     13154053                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       13154053                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1040730                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1040730                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       297940                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       297940                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        16884                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        16884                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data          399                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total          399                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1338670                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1338670                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1338670                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1338670                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  27787431256                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  27787431256                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10644315314                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  10644315314                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    223091000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    223091000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      2495533                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      2495533                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  38431746570                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  38431746570                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  38431746570                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  38431746570                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      8547925                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8547925                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5944798                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5944798                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       194675                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       194675                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       193703                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       193703                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     14492723                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     14492723                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     14492723                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     14492723                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.121752                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.121752                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.050118                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.050118                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.086729                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.086729                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.002060                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.002060                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.092368                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.092368                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.092368                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.092368                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26699.942594                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 26699.942594                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35726.372135                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 35726.372135                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13213.160389                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13213.160389                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6254.468672                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6254.468672                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28708.902545                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 28708.902545                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 28708.902545                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 28708.902545                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       798646                       # number of writebacks
-system.cpu0.dcache.writebacks::total           798646                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1040730                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      1040730                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       297940                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       297940                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        16884                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        16884                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          399                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total          399                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1338670                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1338670                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1338670                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1338670                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  25571734744                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  25571734744                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9990567686                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9990567686                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    189290000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    189290000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      1697467                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1697467                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  35562302430                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  35562302430                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  35562302430                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  35562302430                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1465580500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1465580500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2094321000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2094321000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3559901500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3559901500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.121752                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.121752                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.050118                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.050118                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.086729                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.086729                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.002060                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.002060                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.092368                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.092368                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.092368                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.092368                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24570.959561                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24570.959561                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33532.146358                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33532.146358                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11211.205875                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11211.205875                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4254.303258                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4254.303258                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26565.398814                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26565.398814                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26565.398814                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26565.398814                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dtb.fetch_hits                          0                       # ITB hits
-system.cpu1.dtb.fetch_misses                        0                       # ITB misses
-system.cpu1.dtb.fetch_acv                           0                       # ITB acv
-system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                      957039                       # DTB read hits
-system.cpu1.dtb.read_misses                      2620                       # DTB read misses
-system.cpu1.dtb.read_acv                            0                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  205337                       # DTB read accesses
-system.cpu1.dtb.write_hits                     556340                       # DTB write hits
-system.cpu1.dtb.write_misses                      235                       # DTB write misses
-system.cpu1.dtb.write_acv                          24                       # DTB write access violations
-system.cpu1.dtb.write_accesses                  89739                       # DTB write accesses
-system.cpu1.dtb.data_hits                     1513379                       # DTB hits
-system.cpu1.dtb.data_misses                      2855                       # DTB misses
-system.cpu1.dtb.data_acv                           24                       # DTB access violations
-system.cpu1.dtb.data_accesses                  295076                       # DTB accesses
-system.cpu1.itb.fetch_hits                    1320031                       # ITB hits
-system.cpu1.itb.fetch_misses                     1064                       # ITB misses
-system.cpu1.itb.fetch_acv                           0                       # ITB acv
-system.cpu1.itb.fetch_accesses                1321095                       # ITB accesses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.read_acv                            0                       # DTB read access violations
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.write_acv                           0                       # DTB write access violations
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.data_hits                           0                       # DTB hits
-system.cpu1.itb.data_misses                         0                       # DTB misses
-system.cpu1.itb.data_acv                            0                       # DTB access violations
-system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                      3921887017                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                    4749746                       # Number of instructions committed
-system.cpu1.committedOps                      4749746                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses              4446088                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                 30301                       # Number of float alu accesses
-system.cpu1.num_func_calls                     145582                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts       455512                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                     4446088                       # number of integer instructions
-system.cpu1.num_fp_insts                        30301                       # number of float instructions
-system.cpu1.num_int_register_reads            6169769                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           3384887                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               19629                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              19442                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      1521715                       # number of memory refs
-system.cpu1.num_load_insts                     962201                       # Number of load instructions
-system.cpu1.num_store_insts                    559514                       # Number of store instructions
-system.cpu1.num_idle_cycles              3904242469.193159                       # Number of idle cycles
-system.cpu1.num_busy_cycles              17644547.806841                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.004499                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.995501                       # Percentage of idle cycles
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2329                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     33659                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                    8392     30.97%     30.97% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1970      7.27%     38.24% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                     88      0.32%     38.57% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  16645     61.43%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               27095                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                     8384     44.74%     44.74% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1970     10.51%     55.26% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                      88      0.47%     55.73% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                    8296     44.27%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                18738                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1917649813500     97.79%     97.79% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              700167000      0.04%     97.83% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30               60318500      0.00%     97.83% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            42533179500      2.17%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1960943478500                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.999047                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.498408                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.691567                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::3                        10     10.87%     10.87% # number of syscalls executed
-system.cpu1.kern.syscall::6                         9      9.78%     20.65% # number of syscalls executed
-system.cpu1.kern.syscall::15                        1      1.09%     21.74% # number of syscalls executed
-system.cpu1.kern.syscall::17                        5      5.43%     27.17% # number of syscalls executed
-system.cpu1.kern.syscall::23                        3      3.26%     30.43% # number of syscalls executed
-system.cpu1.kern.syscall::24                        3      3.26%     33.70% # number of syscalls executed
-system.cpu1.kern.syscall::33                        3      3.26%     36.96% # number of syscalls executed
-system.cpu1.kern.syscall::45                       15     16.30%     53.26% # number of syscalls executed
-system.cpu1.kern.syscall::47                        3      3.26%     56.52% # number of syscalls executed
-system.cpu1.kern.syscall::59                        1      1.09%     57.61% # number of syscalls executed
-system.cpu1.kern.syscall::71                       27     29.35%     86.96% # number of syscalls executed
-system.cpu1.kern.syscall::74                        9      9.78%     96.74% # number of syscalls executed
-system.cpu1.kern.syscall::132                       3      3.26%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                    92                       # number of syscalls executed
-system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                    6      0.02%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                  283      1.02%      1.06% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       3      0.01%      1.07% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.03%      1.09% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                22604     81.73%     82.82% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2147      7.76%     90.59% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     90.59% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     3      0.01%     90.60% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.01%     90.61% # number of callpals executed
-system.cpu1.kern.callpal::rti                    2432      8.79%     99.41% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 121      0.44%     99.84% # number of callpals executed
-system.cpu1.kern.callpal::imb                      42      0.15%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 27656                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel              652                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                367                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2065                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                379                      
-system.cpu1.kern.mode_good::user                  367                      
-system.cpu1.kern.mode_good::idle                   12                      
-system.cpu1.kern.mode_switch_good::kernel     0.581288                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.005811                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.245785                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        2892019000      0.15%      0.15% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1487213000      0.08%      0.22% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1955685685000     99.78%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                     284                       # number of times the context was actually changed
-system.cpu1.icache.tags.replacements                 79630                       # number of replacements
-system.cpu1.icache.tags.tagsinuse               421.213832                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs                 4672446                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs                 80140                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs                 58.303544                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle          1959882431000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   421.213832                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.822683                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total        0.822683                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst      4672446                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        4672446                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      4672446                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         4672446                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      4672446                       # number of overall hits
-system.cpu1.icache.overall_hits::total        4672446                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst        80179                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total        80179                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst        80179                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total         80179                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst        80179                       # number of overall misses
-system.cpu1.icache.overall_misses::total        80179                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   1082064992                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   1082064992                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   1082064992                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   1082064992                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   1082064992                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   1082064992                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      4752625                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      4752625                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      4752625                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      4752625                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      4752625                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      4752625                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.016870                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.016870                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.016870                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.016870                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.016870                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.016870                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13495.615959                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13495.615959                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13495.615959                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13495.615959                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13495.615959                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13495.615959                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst        80179                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total        80179                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst        80179                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total        80179                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst        80179                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total        80179                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst    921458008                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total    921458008                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst    921458008                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total    921458008                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst    921458008                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total    921458008                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016870                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.016870                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.016870                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.016870                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.016870                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.016870                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11492.510608                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11492.510608                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11492.510608                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11492.510608                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11492.510608                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11492.510608                       # average overall mshr miss latency
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements                 40890                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse               416.865345                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs                 1457107                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs                 41228                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs                 35.342655                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle          1941571028000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   416.865345                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.814190                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total        0.814190                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data       917421                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total         917421                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data       531046                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total        531046                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data         9250                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total         9250                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data         9554                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total         9554                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      1448467                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         1448467                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      1448467                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        1448467                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data        31971                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total        31971                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        13337                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        13337                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data          850                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total          850                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data          495                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total          495                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data        45308                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total         45308                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data        45308                       # number of overall misses
-system.cpu1.dcache.overall_misses::total        45308                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data    398942000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total    398942000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data    455916495                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total    455916495                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data      9380250                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total      9380250                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      3699073                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total      3699073                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data    854858495                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total    854858495                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data    854858495                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total    854858495                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data       949392                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total       949392                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data       544383                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total       544383                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        10100                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        10100                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        10049                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        10049                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      1493775                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      1493775                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      1493775                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      1493775                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.033675                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.033675                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.024499                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.024499                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.084158                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.084158                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.049259                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.049259                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.030331                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.030331                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.030331                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.030331                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12478.245910                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12478.245910                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34184.336432                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 34184.336432                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11035.588235                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11035.588235                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7472.874747                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7472.874747                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18867.716408                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 18867.716408                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18867.716408                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18867.716408                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks        22236                       # number of writebacks
-system.cpu1.dcache.writebacks::total            22236                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        31971                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total        31971                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        13337                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        13337                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data          850                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total          850                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          495                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total          495                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data        45308                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total        45308                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data        45308                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total        45308                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    334917000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total    334917000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    427133505                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total    427133505                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data      7677750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total      7677750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      2708927                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      2708927                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data    762050505                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total    762050505                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data    762050505                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total    762050505                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18768000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18768000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    527878500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    527878500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    546646500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    546646500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033675                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.033675                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.024499                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.024499                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.084158                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.084158                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.049259                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.049259                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.030331                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.030331                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.030331                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.030331                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10475.649808                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10475.649808                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32026.205668                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32026.205668                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  9032.647059                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  9032.647059                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5472.579798                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5472.579798                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16819.336651                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16819.336651                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16819.336651                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16819.336651                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,5 +1,21 @@
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here
+Traceback (most recent call last):
+  File "<string>", line 1, in <module>
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/src/python/m5/main.py", line 387, in main
+    exec filecode in scope
+  File "tests/run.py", line 180, in <module>
+    execfile(joinpath(tests_root, 'configs', test_filename + '.py'))
+  File "tests/configs/tsunami-simple-timing.py", line 42, in <module>
+    cpu_class=TimingSimpleCPU).create_root()
+  File "tests/configs/base_config.py", line 230, in create_root
+    system = self.create_system()
+  File "tests/configs/alpha_generic.py", line 62, in create_system
+    system = FSConfig.makeLinuxAlphaSystem(self.mem_mode, DDR3_1600_x64)
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/FSConfig.py", line 83, in makeLinuxAlphaSystem
+    self.disk0.childImage(mdesc.disk())
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/Benchmarks.py", line 55, in disk
+    return env.get('LINUX_IMAGE', disk('linux-latest.img'))
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 37, in disk
+    system()
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 59, in system
+    raise ImportError, "Can't find a path to system files."
+ImportError: Can't find a path to system files.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,14 +1,7 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:32:52
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
-      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1910582068000 because m5_exit instruction encountered
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,1132 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  1.918473                       # Number of seconds simulated
-sim_ticks                                1918473094000                       # Number of ticks simulated
-final_tick                               1918473094000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 813863                       # Simulator instruction rate (inst/s)
-host_op_rate                                   813863                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            27788392408                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 306196                       # Number of bytes of host memory used
-host_seconds                                    69.04                       # Real time elapsed on the host
-sim_insts                                    56188014                       # Number of instructions simulated
-sim_ops                                      56188014                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            850688                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24847488                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28350528                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       850688                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          850688                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7389888                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7389888                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              13292                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388242                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                442977                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          115467                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115467                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               443419                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             12951700                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1382533                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14777652                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          443419                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             443419                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3851963                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3851963                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3851963                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              443419                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            12951700                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1382533                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18629615                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        442977                       # Total number of read requests seen
-system.physmem.writeReqs                       115467                       # Total number of write requests seen
-system.physmem.cpureqs                         558574                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                     28350528                       # Total number of bytes read from memory
-system.physmem.bytesWritten                   7389888                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd               28350528                       # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr                7389888                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                       50                       # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite                130                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                 27963                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                 28090                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                 28297                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                 28045                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                 27408                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                 27547                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                 26911                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                 26768                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                 27805                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                 27257                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10                27713                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11                27329                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12                27431                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13                28072                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14                28025                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15                28266                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                  7723                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1                  7594                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2                  7833                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3                  7543                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4                  7011                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5                  6984                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6                  6467                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                  6223                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8                  7221                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9                  6661                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10                 7097                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11                 6780                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12                 7013                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13                 7721                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14                 7774                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15                 7822                       # Track writes on a per bank basis
-system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                    1918461222000                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                  442977                       # Categorize read packet sizes
-system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::6                 115467                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                    402244                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      7043                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      5311                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      3263                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      3253                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      3011                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      1562                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1513                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1478                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1450                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1424                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1426                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1399                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     2029                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     2311                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     2193                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                     1221                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      460                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      219                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      112                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      3591                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      3696                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      4739                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      5019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      5021                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     1430                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     1325                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                      282                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        37132                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      962.378541                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     229.718891                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev    2449.750918                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-67          13161     35.44%     35.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-131         5591     15.06%     50.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-195         3357      9.04%     59.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-259         2263      6.09%     65.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-323         1589      4.28%     69.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-387         1303      3.51%     73.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-451          971      2.61%     76.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-515          731      1.97%     78.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-579          647      1.74%     79.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-643          569      1.53%     81.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-707          543      1.46%     82.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-771          425      1.14%     83.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-835          308      0.83%     84.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-899          237      0.64%     85.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-963          163      0.44%     85.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1027          235      0.63%     86.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1091          101      0.27%     86.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1155           93      0.25%     86.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1219           98      0.26%     87.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1283           98      0.26%     87.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1347           85      0.23%     87.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1411          107      0.29%     88.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1475         1046      2.82%     90.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1539          157      0.42%     91.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1603           87      0.23%     91.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1667           55      0.15%     91.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1731           46      0.12%     91.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1795           40      0.11%     91.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1859           31      0.08%     91.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1923           18      0.05%     91.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1987           16      0.04%     92.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2051           26      0.07%     92.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2115           19      0.05%     92.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2179            8      0.02%     92.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2243            8      0.02%     92.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2307           15      0.04%     92.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2371           14      0.04%     92.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2435            3      0.01%     92.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2499            3      0.01%     92.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2563            6      0.02%     92.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2627            4      0.01%     92.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2691            4      0.01%     92.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2755            1      0.00%     92.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2819            3      0.01%     92.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2883            2      0.01%     92.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2947            4      0.01%     92.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3011            2      0.01%     92.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3075            1      0.00%     92.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3139            3      0.01%     92.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3203            4      0.01%     92.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3267            2      0.01%     92.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3331            3      0.01%     92.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3395            3      0.01%     92.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3459            1      0.00%     92.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3523            4      0.01%     92.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3587            3      0.01%     92.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3651            1      0.00%     92.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3779            2      0.01%     92.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3843            1      0.00%     92.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3907            1      0.00%     92.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3971            1      0.00%     92.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4035            1      0.00%     92.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4099            1      0.00%     92.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4227            2      0.01%     92.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4291            1      0.00%     92.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4355            1      0.00%     92.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4419            3      0.01%     92.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4483            2      0.01%     92.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4675            1      0.00%     92.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4931            4      0.01%     92.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4995            2      0.01%     92.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5059            2      0.01%     92.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5123            1      0.00%     92.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5315            2      0.01%     92.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5443            2      0.01%     92.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5699            1      0.00%     92.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5763            1      0.00%     92.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5891            1      0.00%     92.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6083            1      0.00%     92.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6403            1      0.00%     92.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6595            1      0.00%     92.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6851            1      0.00%     92.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7171            3      0.01%     92.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7235            1      0.00%     92.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7299            2      0.01%     92.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7363            2      0.01%     92.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7555            1      0.00%     92.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7683            1      0.00%     92.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7747            1      0.00%     92.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7811            1      0.00%     92.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7939            3      0.01%     92.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8003            3      0.01%     92.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8131            4      0.01%     92.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8195         2437      6.56%     99.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8256-8259            1      0.00%     99.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8512-8515            1      0.00%     99.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8576-8579            1      0.00%     99.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9152-9155            1      0.00%     99.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9728-9731            1      0.00%     99.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10176-10179            1      0.00%     99.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10368-10371            1      0.00%     99.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13760-13763            1      0.00%     99.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14016-14019            1      0.00%     99.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14211            1      0.00%     99.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14339            1      0.00%     99.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14464-14467            1      0.00%     99.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14656-14659            2      0.01%     99.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14848-14851            1      0.00%     99.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14912-14915            1      0.00%     99.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15040-15043            1      0.00%     99.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15168-15171            1      0.00%     99.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15296-15299            1      0.00%     99.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15363           16      0.04%     99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15424-15427            1      0.00%     99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15488-15491            1      0.00%     99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15744-15747            1      0.00%     99.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16192-16195            1      0.00%     99.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16387          242      0.65%     99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16448-16451            9      0.02%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16512-16515            9      0.02%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16576-16579            3      0.01%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16640-16643            3      0.01%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16704-16707            2      0.01%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16768-16771            1      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16832-16835            4      0.01%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16960-16963            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17024-17027            3      0.01%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17344-17347            2      0.01%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          37132                       # Bytes accessed per row activation
-system.physmem.totQLat                     3659130000                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat               11798708750                       # Sum of mem lat for all requests
-system.physmem.totBusLat                   2214635000                       # Total cycles spent in databus access
-system.physmem.totBankLat                  5924943750                       # Total cycles spent in bank access
-system.physmem.avgQLat                        8261.25                       # Average queueing delay per request
-system.physmem.avgBankLat                    13376.80                       # Average bank access latency per request
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
-system.physmem.avgMemAccLat                  26638.04                       # Average memory access latency
-system.physmem.avgRdBW                          14.78                       # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW                           3.85                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                  14.78                       # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW                   3.85                       # Average consumed write bandwidth in MB/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
-system.physmem.avgRdQLen                         0.01                       # Average read queue length over time
-system.physmem.avgWrQLen                        13.19                       # Average write queue length over time
-system.physmem.readRowHits                     427838                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93417                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   96.59                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.90                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3435369.03                       # Average gap between requests
-system.membus.throughput                     18671288                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              292313                       # Transaction distribution
-system.membus.trans_dist::ReadResp             292313                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9649                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9649                       # Transaction distribution
-system.membus.trans_dist::Writeback            115467                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              132                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             132                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            158147                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           158147                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33158                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       877556                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       910714                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124680                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124680                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.bridge.slave        33158                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.physmem.port      1002236                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1035394                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44556                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30431296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30475852                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5309120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      5309120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.bridge.slave        44556                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.physmem.port     35740416                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            35784972                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               35784972                       # Total data (bytes)
-system.membus.snoop_data_through_bus            35392                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            32373000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1487941500                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3745756604                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          376206000                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                     41685                       # number of replacements
-system.iocache.tags.tagsinuse                     1.345474                       # Cycle average of tags in use
-system.iocache.tags.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                     41701                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle              1752558313000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide       1.345474                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide      0.084092                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total            0.084092                       # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
-system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21343633                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21343633                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide  10434225282                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  10434225282                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide  10455568915                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  10455568915                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide  10455568915                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  10455568915                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123373.601156                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 123373.601156                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251112.468281                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 251112.468281                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 250582.837987                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 250582.837987                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 250582.837987                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 250582.837987                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        272640                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                27184                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.029429                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41512                       # number of writebacks
-system.iocache.writebacks::total                41512                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12346133                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12346133                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   8272160782                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   8272160782                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   8284506915                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   8284506915                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   8284506915                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   8284506915                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199079.726174                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 199079.726174                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198550.195686                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 198550.195686                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198550.195686                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 198550.195686                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9065600                       # DTB read hits
-system.cpu.dtb.read_misses                      10324                       # DTB read misses
-system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_accesses                   728853                       # DTB read accesses
-system.cpu.dtb.write_hits                     6356756                       # DTB write hits
-system.cpu.dtb.write_misses                      1142                       # DTB write misses
-system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
-system.cpu.dtb.data_hits                     15422356                       # DTB hits
-system.cpu.dtb.data_misses                      11466                       # DTB misses
-system.cpu.dtb.data_acv                           367                       # DTB access violations
-system.cpu.dtb.data_accesses                  1020784                       # DTB accesses
-system.cpu.itb.fetch_hits                     4974352                       # ITB hits
-system.cpu.itb.fetch_misses                      5010                       # ITB misses
-system.cpu.itb.fetch_acv                          184                       # ITB acv
-system.cpu.itb.fetch_accesses                 4979362                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                       3836946188                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    56188014                       # Number of instructions committed
-system.cpu.committedOps                      56188014                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              52059797                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 324527                       # Number of float alu accesses
-system.cpu.num_func_calls                     1483456                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      6468822                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     52059797                       # number of integer instructions
-system.cpu.num_fp_insts                        324527                       # number of float instructions
-system.cpu.num_int_register_reads            71330046                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           38525190                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads               163675                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              166554                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      15474978                       # number of memory refs
-system.cpu.num_load_insts                     9102456                       # Number of load instructions
-system.cpu.num_store_insts                    6372522                       # Number of store instructions
-system.cpu.num_idle_cycles               3586988416.498130                       # Number of idle cycles
-system.cpu.num_busy_cycles               249957771.501870                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.065145                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.934855                       # Percentage of idle cycles
-system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6379                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211982                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74893     40.89%     40.89% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     131      0.07%     40.96% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1931      1.05%     42.01% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  106209     57.99%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               183164                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73526     49.31%     49.31% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1931      1.29%     50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73526     49.31%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149114                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1857159489000     96.80%     96.80% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                91367000      0.00%     96.81% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               736929000      0.04%     96.85% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             60484575000      3.15%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1918472360000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981747                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.692277                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814101                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
-system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
-system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
-system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
-system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
-system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
-system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
-system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
-system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
-system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
-system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
-system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
-system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
-system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
-system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
-system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
-system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
-system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
-system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
-system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
-system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
-system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
-system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
-system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
-system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
-system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
-system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
-system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
-system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
-system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
-system.cpu.kern.syscall::total                    326                       # number of syscalls executed
-system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4178      2.17%      2.17% # number of callpals executed
-system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
-system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175945     91.21%     93.41% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6832      3.54%     96.96% # number of callpals executed
-system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
-system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
-system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rti                     5156      2.67%     99.64% # number of callpals executed
-system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
-system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192891                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5903                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1911                      
-system.cpu.kern.mode_good::user                  1740                      
-system.cpu.kern.mode_good::idle                   171                      
-system.cpu.kern.mode_switch_good::kernel     0.323734                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081545                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.392402                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        46124802000      2.40%      2.40% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           5245072500      0.27%      2.68% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1867102483500     97.32%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4179                       # number of times the context was actually changed
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.iobus.throughput                       1410582                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51201                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51201                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5154                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33158                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.cchip.pio         5154                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116608                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        20616                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total        44556                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.cchip.pio        20616                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              2706164                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 2706164                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              4765000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            13484000                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy             1887000                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           378268915                       # Layer occupancy (ticks)
-system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
-system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23509000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            43091000                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                 928665                       # number of replacements
-system.cpu.icache.tags.tagsinuse                508.413691                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 55270512                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                 929176                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                  59.483362                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle            38814414250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     508.413691                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.992995                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.992995                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     55270512                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        55270512                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      55270512                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         55270512                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     55270512                       # number of overall hits
-system.cpu.icache.overall_hits::total        55270512                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       929336                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        929336                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       929336                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         929336                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       929336                       # number of overall misses
-system.cpu.icache.overall_misses::total        929336                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  13015346257                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  13015346257                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  13015346257                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  13015346257                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  13015346257                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  13015346257                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     56199848                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     56199848                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     56199848                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     56199848                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     56199848                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     56199848                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016536                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.016536                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.016536                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.016536                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.016536                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.016536                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14004.995241                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14004.995241                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14004.995241                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14004.995241                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14004.995241                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14004.995241                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       929336                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       929336                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       929336                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       929336                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       929336                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       929336                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11150220743                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11150220743                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11150220743                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11150220743                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11150220743                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11150220743                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016536                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016536                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016536                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.016536                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016536                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.016536                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.051020                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.051020                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.051020                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.051020                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.051020                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.051020                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                336065                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse             65300.870394                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                 2448301                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                401226                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  6.102050                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle            6580892750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 55613.136753                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   4759.199410                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   4928.534231                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.848589                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.072620                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.075203                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.996412                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst       916024                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       814969                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1730993                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       835407                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       835407                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187779                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187779                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       916024                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1002748                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1918772                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       916024                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1002748                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1918772                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst        13292                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       271918                       # number of ReadReq misses
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-system.cpu.l2cache.UpgradeReq_misses::total           13                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       116714                       # number of ReadExReq misses
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-system.cpu.l2cache.demand_misses::cpu.inst        13292                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       388632                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        401924                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        13292                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       388632                       # number of overall misses
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-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  16925556244                       # number of ReadReq miss cycles
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-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7757662128                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.inst   1060624743                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  24683218372                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  25743843115                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1060624743                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  24683218372                       # number of overall miss cycles
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-system.cpu.l2cache.ReadReq_accesses::cpu.inst       929316                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1086887                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2016203                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       835407                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       835407                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           17                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           17                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       304493                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.demand_accesses::cpu.inst       929316                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1391380                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2320696                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       929316                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1391380                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2320696                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014303                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.250181                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.141459                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.764706                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.764706                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383306                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.383306                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014303                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.279314                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.173191                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014303                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.279314                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.173191                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79794.217800                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62245.074780                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 63062.939543                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66467.280086                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66467.280086                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79794.217800                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63513.087888                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 64051.519976                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79794.217800                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63513.087888                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 64051.519976                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
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-system.cpu.l2cache.writebacks::writebacks        73955                       # number of writebacks
-system.cpu.l2cache.writebacks::total            73955                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        13292                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       271918                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       285210                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           13                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           13                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116714                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       116714                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        13292                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       388632                       # number of demand (read+write) MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::cpu.data       388632                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       401924                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    893093257                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  13525299756                       # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       230011                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       230011                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6297401372                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6297401372                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    893093257                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  19822701128                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20715794385                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    893093257                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  19822701128                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20715794385                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1334143500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1334143500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1895431500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1895431500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3229575000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3229575000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014303                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.250181                       # mshr miss rate for ReadReq accesses
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-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014303                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279314                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.173191                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014303                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279314                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.173191                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67190.284156                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49740.362006                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50553.602654                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53955.835392                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53955.835392                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67190.284156                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51006.353383                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 51541.571006                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67190.284156                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51006.353383                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51541.571006                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                1390866                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                511.979110                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                 14050029                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                1391378                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  10.097924                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle              105729250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data     511.979110                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.999959                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.999959                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data      7815067                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7815067                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5852671                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5852671                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       183038                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183038                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199236                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199236                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13667738                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13667738                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13667738                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13667738                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1069668                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1069668                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304510                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304510                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17219                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17219                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1374178                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1374178                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1374178                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1374178                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  28240934256                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  28240934256                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10606589383                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10606589383                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    229410500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    229410500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  38847523639                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  38847523639                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  38847523639                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  38847523639                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      8884735                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      8884735                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6157181                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6157181                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200257                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200257                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199236                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199236                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15041916                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15041916                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15041916                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15041916                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120394                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.120394                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049456                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049456                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085985                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085985                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.091357                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.091357                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.091357                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.091357                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26401.588396                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26401.588396                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34831.661959                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34831.661959                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13323.102387                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13323.102387                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 28269.644572                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 28269.644572                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 28269.644572                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 28269.644572                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       835407                       # number of writebacks
-system.cpu.dcache.writebacks::total            835407                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069668                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1069668                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304510                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304510                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17219                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17219                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1374178                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1374178                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1374178                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1374178                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  25967193744                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  25967193744                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9940394617                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   9940394617                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    194939500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    194939500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  35907588361                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  35907588361                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  35907588361                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  35907588361                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424233500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424233500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2011219500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2011219500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3435453000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3435453000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120394                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120394                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049456                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049456                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.085985                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.085985                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091357                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091357                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091357                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091357                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24275.937715                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24275.937715                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32643.902062                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32643.902062                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.185899                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.185899                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26130.230844                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26130.230844                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26130.230844                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26130.230844                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               105316327                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2023326                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2023309                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9649                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9649                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       835407                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       346045                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304495                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side      1858652                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side      3651517                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count                  5510169                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side     59476224                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side    142569036                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size             202045260                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         202035148                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus        11392                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     2426591000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       237000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1397230757                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2194639139                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,17 +1,21 @@
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
-warn: 	instruction 'mcr bpiallis' unimplemented
-warn: 	instruction 'mcr icialluis' unimplemented
-warn: 	instruction 'mcr dccimvac' unimplemented
-warn: 	instruction 'mcr dccmvau' unimplemented
-warn: 	instruction 'mcr icimvau' unimplemented
-warn: 	instruction 'mcr bpiallis' unimplemented
-warn: LCD dual screen mode not supported
-warn: 	instruction 'mcr icialluis' unimplemented
-warn: 	instruction 'mcr icialluis' unimplemented
-hack: be nice to actually delete the event here
+Traceback (most recent call last):
+  File "<string>", line 1, in <module>
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/src/python/m5/main.py", line 387, in main
+    exec filecode in scope
+  File "tests/run.py", line 180, in <module>
+    execfile(joinpath(tests_root, 'configs', test_filename + '.py'))
+  File "tests/configs/realview-simple-atomic-dual.py", line 42, in <module>
+    num_cpus=2).create_root()
+  File "tests/configs/base_config.py", line 230, in create_root
+    system = self.create_system()
+  File "tests/configs/arm_generic.py", line 65, in create_system
+    None, False)
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/FSConfig.py", line 265, in makeArmSystem
+    self.cf0.childImage(mdesc.disk())
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/Benchmarks.py", line 59, in disk
+    return env.get('LINUX_IMAGE', disk('linux-arm-ael.img'))
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 37, in disk
+    system()
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 59, in system
+    raise ImportError, "Can't find a path to system files."
+ImportError: Can't find a path to system files.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,14 +1,7 @@
-Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual/simout
-Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:45:38
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-info: Using bootloader at address 0x80000000
-info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 912096763500 because m5_exit instruction encountered
+gem5 compiled Jul 17 2013 12:12:01
+gem5 started Jul 17 2013 12:12:09
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,791 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.912097                       # Number of seconds simulated
-sim_ticks                                912096763500                       # Number of ticks simulated
-final_tick                               912096763500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 749434                       # Simulator instruction rate (inst/s)
-host_op_rate                                   964895                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            11092016800                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 399496                       # Number of bytes of host memory used
-host_seconds                                    82.23                       # Real time elapsed on the host
-sim_insts                                    61625970                       # Number of instructions simulated
-sim_ops                                      79343340                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd     39321600                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           502180                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          6235188                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           214556                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          3364528                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             49638500                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       502180                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       214556                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          716736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4195776                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data       3010088                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7222864                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd       4915200                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             14065                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             97497                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              3434                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             52597                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               5082800                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           65559                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           752522                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               822331                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        43111215                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker            70                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker           211                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              550578                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             6836104                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           211                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              235234                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             3688784                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                54422406                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         550578                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         235234                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             785811                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4600144                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data              18638                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            3300185                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7918967                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4600144                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       43111215                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker           70                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker          211                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             550578                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            6854742                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          211                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             235234                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            6988969                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               62341372                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                             0                       # Total number of read requests seen
-system.physmem.writeReqs                            0                       # Total number of write requests seen
-system.physmem.cpureqs                              0                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                            0                       # Total number of bytes read from memory
-system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd                      0                       # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15                    0                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
-system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                               0                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                       0                       # Categorize read packet sizes
-system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::6                      0                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::mean             nan                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean            nan                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev            nan                       # Bytes accessed per row activation
-system.physmem.totQLat                              0                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat                         0                       # Sum of mem lat for all requests
-system.physmem.totBusLat                            0                       # Total cycles spent in databus access
-system.physmem.totBankLat                           0                       # Total cycles spent in bank access
-system.physmem.avgQLat                            nan                       # Average queueing delay per request
-system.physmem.avgBankLat                         nan                       # Average bank access latency per request
-system.physmem.avgBusLat                          nan                       # Average bus latency per request
-system.physmem.avgMemAccLat                       nan                       # Average memory access latency
-system.physmem.avgRdBW                           0.00                       # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                   0.00                       # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil                           0.00                       # Data bus utilization in percentage
-system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
-system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
-system.physmem.readRowHits                          0                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                     nan                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                             nan                       # Average gap between requests
-system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst           22                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst           53                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               75                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst           22                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst           53                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total           75                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst           22                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst           53                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              75                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     64986577                       # Throughput (bytes/s)
-system.membus.data_through_bus               59274047                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.l2c.tags.replacements                         70658                       # number of replacements
-system.l2c.tags.tagsinuse                     51560.149653                       # Cycle average of tags in use
-system.l2c.tags.total_refs                         1623339                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                        135810                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                         11.953015                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks        39278.694978                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker       0.000049                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker       0.001108                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst          4358.955639                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data          2482.445004                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker       2.678940                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst          2126.451282                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data          3310.922653                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks           0.599345                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker      0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst            0.066512                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data            0.037879                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker      0.000041                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst            0.032447                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data            0.050521                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total                0.786745                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker         3874                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         1919                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             421038                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             175188                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         5331                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         1734                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             430511                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             169511                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1209106                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          567807                       # number of Writeback hits
-system.l2c.Writeback_hits::total               567807                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             611                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             663                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                1274                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           137                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            31                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               168                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            58148                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            50212                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               108360                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          3874                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          1919                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              421038                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              233336                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          5331                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          1734                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              430511                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              219723                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1317466                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         3874                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         1919                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             421038                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             233336                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         5331                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         1734                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             430511                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             219723                       # number of overall hits
-system.l2c.overall_hits::total                1317466                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker            3                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             7432                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             6392                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker            3                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             3347                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             5276                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                22454                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          4932                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          4304                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              9236                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          741                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          490                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1231                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          92464                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          48372                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             140836                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker            3                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              7432                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             98856                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker            3                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              3347                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             53648                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                163290                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker            3                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             7432                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            98856                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker            3                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             3347                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            53648                       # number of overall misses
-system.l2c.overall_misses::total               163290                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         3875                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         1922                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         428470                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         181580                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         5334                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         1734                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         433858                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         174787                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1231560                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       567807                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           567807                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         5543                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         4967                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           10510                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          878                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          521                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1399                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       150612                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        98584                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           249196                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         3875                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         1922                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          428470                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          332192                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         5334                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         1734                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          433858                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          273371                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1480756                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         3875                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         1922                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         428470                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         332192                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         5334                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         1734                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         433858                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         273371                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1480756                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000258                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001561                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.017345                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.035202                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000562                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.007715                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.030185                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.018232                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.889771                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.866519                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.878782                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.843964                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.940499                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.879914                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.613922                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.490668                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.565162                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000258                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.001561                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.017345                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.297587                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.007715                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.196246                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.110275                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000258                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.001561                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.017345                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.297587                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.007715                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.196246                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.110275                       # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               65559                       # number of writebacks
-system.l2c.writebacks::total                    65559                       # number of writebacks
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                   154009014                       # Throughput (bytes/s)
-system.toL2Bus.data_through_bus             140471123                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus               0                       # Total snoop data (bytes)
-system.iobus.throughput                      45730949                       # Throughput (bytes/s)
-system.iobus.data_through_bus                41711051                       # Total data (bytes)
-system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     7975768                       # DTB read hits
-system.cpu0.dtb.read_misses                      3611                       # DTB read misses
-system.cpu0.dtb.write_hits                    5966574                       # DTB write hits
-system.cpu0.dtb.write_misses                      672                       # DTB write misses
-system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    2004                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   135                       # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 7979379                       # DTB read accesses
-system.cpu0.dtb.write_accesses                5967246                       # DTB write accesses
-system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         13942342                       # DTB hits
-system.cpu0.dtb.misses                           4283                       # DTB misses
-system.cpu0.dtb.accesses                     13946625                       # DTB accesses
-system.cpu0.itb.inst_hits                    30238804                       # ITB inst hits
-system.cpu0.itb.inst_misses                      2175                       # ITB inst misses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1499                       # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                30240979                       # ITB inst accesses
-system.cpu0.itb.hits                         30238804                       # DTB hits
-system.cpu0.itb.misses                           2175                       # DTB misses
-system.cpu0.itb.accesses                     30240979                       # DTB accesses
-system.cpu0.numCycles                      1823633059                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   29750005                       # Number of instructions committed
-system.cpu0.committedOps                     39129633                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             34471201                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  5449                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1241903                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4044057                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    34471201                       # number of integer instructions
-system.cpu0.num_fp_insts                         5449                       # number of float instructions
-system.cpu0.num_int_register_reads          175121947                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          36551788                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                4535                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                916                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     14626951                       # number of memory refs
-system.cpu0.num_load_insts                    8357226                       # Number of load instructions
-system.cpu0.num_store_insts                   6269725                       # Number of store instructions
-system.cpu0.num_idle_cycles              1783968822.941743                       # Number of idle cycles
-system.cpu0.num_busy_cycles              39664236.058257                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.021750                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.978250                       # Percentage of idle cycles
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   49966                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements                428546                       # number of replacements
-system.cpu0.icache.tags.tagsinuse               511.015216                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs                29811115                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs                429058                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs                 69.480385                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle           64537139000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.015216                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998077                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total        0.998077                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst     29811115                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       29811115                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     29811115                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        29811115                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     29811115                       # number of overall hits
-system.cpu0.icache.overall_hits::total       29811115                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       429059                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       429059                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       429059                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        429059                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       429059                       # number of overall misses
-system.cpu0.icache.overall_misses::total       429059                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     30240174                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     30240174                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     30240174                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     30240174                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     30240174                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     30240174                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014188                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014188                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014188                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014188                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014188                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014188                       # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements                323609                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse               494.763091                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs                12467604                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs                323981                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs                 38.482516                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle              22115000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.763091                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.966334                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total        0.966334                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6512305                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6512305                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      5630881                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5630881                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       151619                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       151619                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       153180                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       153180                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     12143186                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12143186                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     12143186                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12143186                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       197167                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       197167                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       167342                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       167342                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9062                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         9062                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7469                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7469                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       364509                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        364509                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       364509                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       364509                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      6709472                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      6709472                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5798223                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5798223                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       160681                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       160681                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       160649                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       160649                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12507695                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12507695                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12507695                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12507695                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.029386                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.029386                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.028861                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.028861                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056397                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056397                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.046493                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.046493                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029143                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.029143                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029143                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.029143                       # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       300958                       # number of writebacks
-system.cpu0.dcache.writebacks::total           300958                       # number of writebacks
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     7364781                       # DTB read hits
-system.cpu1.dtb.read_misses                      3705                       # DTB read misses
-system.cpu1.dtb.write_hits                    5489656                       # DTB write hits
-system.cpu1.dtb.write_misses                     1595                       # DTB write misses
-system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1788                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   145                       # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 7368486                       # DTB read accesses
-system.cpu1.dtb.write_accesses                5491251                       # DTB write accesses
-system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         12854437                       # DTB hits
-system.cpu1.dtb.misses                           5300                       # DTB misses
-system.cpu1.dtb.accesses                     12859737                       # DTB accesses
-system.cpu1.itb.inst_hits                    32412306                       # ITB inst hits
-system.cpu1.itb.inst_misses                      2200                       # ITB inst misses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1327                       # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                32414506                       # ITB inst accesses
-system.cpu1.itb.hits                         32412306                       # DTB hits
-system.cpu1.itb.misses                           2200                       # DTB misses
-system.cpu1.itb.accesses                     32414506                       # DTB accesses
-system.cpu1.numCycles                      1824154149                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   31875965                       # Number of instructions committed
-system.cpu1.committedOps                     40213707                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             35797832                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  4436                       # Number of float alu accesses
-system.cpu1.num_func_calls                     955227                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      4048022                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    35797832                       # number of integer instructions
-system.cpu1.num_fp_insts                         4436                       # number of float instructions
-system.cpu1.num_int_register_reads          181634271                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          39007898                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                3022                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               1416                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     13370713                       # number of memory refs
-system.cpu1.num_load_insts                    7642673                       # Number of load instructions
-system.cpu1.num_store_insts                   5728040                       # Number of store instructions
-system.cpu1.num_idle_cycles              1783362859.317266                       # Number of idle cycles
-system.cpu1.num_busy_cycles              40791289.682734                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.022362                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.977638                       # Percentage of idle cycles
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   40379                       # number of quiesce instructions executed
-system.cpu1.icache.tags.replacements                433942                       # number of replacements
-system.cpu1.icache.tags.tagsinuse               475.447912                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs                31979125                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs                434454                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs                 73.607620                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle           69967763000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   475.447912                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.928609                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total        0.928609                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst     31979125                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       31979125                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     31979125                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        31979125                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     31979125                       # number of overall hits
-system.cpu1.icache.overall_hits::total       31979125                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       434454                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       434454                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       434454                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        434454                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       434454                       # number of overall misses
-system.cpu1.icache.overall_misses::total       434454                       # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     32413579                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     32413579                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     32413579                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     32413579                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     32413579                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     32413579                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.013403                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.013403                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.013403                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.013403                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.013403                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.013403                       # miss rate for overall accesses
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements                294289                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse               447.573682                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs                11707745                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs                294801                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs                 39.714061                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle           67293493000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   447.573682                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.874167                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total        0.874167                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data      7002209                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        7002209                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      4520313                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       4520313                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        77954                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        77954                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        79030                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        79030                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     11522522                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        11522522                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     11522522                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       11522522                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       198275                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       198275                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       125920                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       125920                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11251                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        11251                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10139                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        10139                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       324195                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        324195                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       324195                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       324195                       # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      7200484                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      7200484                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      4646233                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      4646233                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        89205                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        89205                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        89169                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        89169                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     11846717                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     11846717                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     11846717                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     11846717                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.027536                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.027536                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.027102                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.027102                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.126125                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.126125                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.113705                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.113705                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027366                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.027366                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.027366                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.027366                       # miss rate for overall accesses
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       266849                       # number of writebacks
-system.cpu1.dcache.writebacks::total           266849                       # number of writebacks
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements                         0                       # number of replacements
-system.iocache.tags.tagsinuse                            0                       # Cycle average of tags in use
-system.iocache.tags.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                         0                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                           nan                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status	Wed Aug 07 15:24:58 2013 -0500
@@ -1,1 +1,1 @@
-build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual FAILED!
+build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual FAILED!
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,16 +1,21 @@
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
-warn: 	instruction 'mcr bpiallis' unimplemented
-warn: 	instruction 'mcr icialluis' unimplemented
-warn: 	instruction 'mcr dccimvac' unimplemented
-warn: 	instruction 'mcr dccmvau' unimplemented
-warn: 	instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
-warn: 	instruction 'mcr icialluis' unimplemented
-warn: 	instruction 'mcr bpiallis' unimplemented
-hack: be nice to actually delete the event here
+Traceback (most recent call last):
+  File "<string>", line 1, in <module>
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/src/python/m5/main.py", line 387, in main
+    exec filecode in scope
+  File "tests/run.py", line 180, in <module>
+    execfile(joinpath(tests_root, 'configs', test_filename + '.py'))
+  File "tests/configs/realview-simple-atomic.py", line 42, in <module>
+    cpu_class=AtomicSimpleCPU).create_root()
+  File "tests/configs/base_config.py", line 230, in create_root
+    system = self.create_system()
+  File "tests/configs/arm_generic.py", line 65, in create_system
+    None, False)
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/FSConfig.py", line 265, in makeArmSystem
+    self.cf0.childImage(mdesc.disk())
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/Benchmarks.py", line 59, in disk
+    return env.get('LINUX_IMAGE', disk('linux-arm-ael.img'))
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 37, in disk
+    system()
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 59, in system
+    raise ImportError, "Can't find a path to system files."
+ImportError: Can't find a path to system files.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,14 +1,7 @@
-Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:44:32
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-info: Using bootloader at address 0x80000000
-info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2332810264000 because m5_exit instruction encountered
+gem5 compiled Jul 17 2013 12:12:01
+gem5 started Jul 17 2013 12:12:09
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,520 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  2.332810                       # Number of seconds simulated
-sim_ticks                                2332810264000                       # Number of ticks simulated
-final_tick                               2332810264000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 692273                       # Simulator instruction rate (inst/s)
-host_op_rate                                   890221                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            26733610702                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 396420                       # Number of bytes of host memory used
-host_seconds                                    87.26                       # Real time elapsed on the host
-sim_insts                                    60408639                       # Number of instructions simulated
-sim_ops                                      77681819                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd    111673344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            705120                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9071632                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            121450608                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       705120                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          705120                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3703232                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data        3015816                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6719048                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      13959168                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              17220                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             141778                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              14118174                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57863                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data            753954                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811817                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47870736                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            137                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             82                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               302262                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3888714                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                52061931                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          302262                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             302262                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1587455                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1292782                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2880238                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1587455                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47870736                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           137                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            82                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              302262                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             5181496                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54942169                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                             0                       # Total number of read requests seen
-system.physmem.writeReqs                            0                       # Total number of write requests seen
-system.physmem.cpureqs                              0                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                            0                       # Total number of bytes read from memory
-system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd                      0                       # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15                    0                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
-system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                               0                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                       0                       # Categorize read packet sizes
-system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::6                      0                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::mean             nan                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean            nan                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev            nan                       # Bytes accessed per row activation
-system.physmem.totQLat                              0                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat                         0                       # Sum of mem lat for all requests
-system.physmem.totBusLat                            0                       # Total cycles spent in databus access
-system.physmem.totBankLat                           0                       # Total cycles spent in bank access
-system.physmem.avgQLat                            nan                       # Average queueing delay per request
-system.physmem.avgBankLat                         nan                       # Average bank access latency per request
-system.physmem.avgBusLat                          nan                       # Average bus latency per request
-system.physmem.avgMemAccLat                       nan                       # Average memory access latency
-system.physmem.avgRdBW                           0.00                       # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                   0.00                       # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil                           0.00                       # Data bus utilization in percentage
-system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
-system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
-system.physmem.readRowHits                          0                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                     nan                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                             nan                       # Average gap between requests
-system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst             9                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                9                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst            9                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            9                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst            9                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               9                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     55969585                       # Throughput (bytes/s)
-system.membus.data_through_bus              130566422                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.iobus.throughput                      48895252                       # Throughput (bytes/s)
-system.iobus.data_through_bus               114063346                       # Total data (bytes)
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     14971214                       # DTB read hits
-system.cpu.dtb.read_misses                       7294                       # DTB read misses
-system.cpu.dtb.write_hits                    11217004                       # DTB write hits
-system.cpu.dtb.write_misses                      2181                       # DTB write misses
-system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3496                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    174                       # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 14978508                       # DTB read accesses
-system.cpu.dtb.write_accesses                11219185                       # DTB write accesses
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          26188218                       # DTB hits
-system.cpu.dtb.misses                            9475                       # DTB misses
-system.cpu.dtb.accesses                      26197693                       # DTB accesses
-system.cpu.itb.inst_hits                     61431840                       # ITB inst hits
-system.cpu.itb.inst_misses                       4471                       # ITB inst misses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2343                       # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 61436311                       # ITB inst accesses
-system.cpu.itb.hits                          61431840                       # DTB hits
-system.cpu.itb.misses                            4471                       # DTB misses
-system.cpu.itb.accesses                      61436311                       # DTB accesses
-system.cpu.numCycles                       4665543516                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    60408639                       # Number of instructions committed
-system.cpu.committedOps                      77681819                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              68795605                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
-system.cpu.num_func_calls                     2136008                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7942113                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     68795605                       # number of integer instructions
-system.cpu.num_fp_insts                         10269                       # number of float instructions
-system.cpu.num_int_register_reads           349324274                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           74103608                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      27361637                       # number of memory refs
-system.cpu.num_load_insts                    15639527                       # Number of load instructions
-system.cpu.num_store_insts                   11722110                       # Number of store instructions
-system.cpu.num_idle_cycles               4586746360.692756                       # Number of idle cycles
-system.cpu.num_busy_cycles               78797155.307244                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.016889                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.983111                       # Percentage of idle cycles
-system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    82795                       # number of quiesce instructions executed
-system.cpu.icache.tags.replacements                 850590                       # number of replacements
-system.cpu.icache.tags.tagsinuse                511.678593                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 60583498                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                 851102                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                  71.182418                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle             5709383000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     511.678593                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.999372                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.999372                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     60583498                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        60583498                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      60583498                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         60583498                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     60583498                       # number of overall hits
-system.cpu.icache.overall_hits::total        60583498                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       851102                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        851102                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       851102                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         851102                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       851102                       # number of overall misses
-system.cpu.icache.overall_misses::total        851102                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     61434600                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     61434600                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     61434600                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     61434600                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     61434600                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     61434600                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013854                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.013854                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.013854                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.013854                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.013854                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.013854                       # miss rate for overall accesses
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                 62243                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse             50007.272909                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                 1669922                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                127628                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                 13.084292                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle          2316901489000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582990                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     2.960148                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.993931                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   7014.720482                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   6089.015357                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.563043                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000045                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000015                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.107036                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.092911                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.763050                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7507                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3129                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       838871                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       366771                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1216278                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       592643                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       592643                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           26                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           26                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       113739                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       113739                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         7507                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         3129                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       838871                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       480510                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1330017                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         7507                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         3129                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       838871                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       480510                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1330017                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            5                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            3                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        10604                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data         9871                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        20483                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2919                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2919                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       133468                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133468                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker            5                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            3                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        10604                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       143339                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        153951                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker            5                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            3                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        10604                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       143339                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       153951                       # number of overall misses
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7512                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3132                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       849475                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       376642                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1236761                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       592643                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       592643                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2945                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2945                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       247207                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       247207                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7512                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         3132                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       849475                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       623849                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1483968                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7512                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker         3132                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       849475                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       623849                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1483968                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000666                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000958                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012483                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026208                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.016562                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991171                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991171                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.539904                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.539904                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000666                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000958                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012483                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.229766                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.103743                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000666                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000958                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012483                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.229766                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.103743                       # miss rate for overall accesses
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        57863                       # number of writebacks
-system.cpu.l2cache.writebacks::total            57863                       # number of writebacks
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                 623337                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                511.997031                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                 23628343                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                 623849                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  37.875100                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle               21763000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data     511.997031                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.999994                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.999994                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     13180066                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13180066                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      9962072                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        9962072                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       236039                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       236039                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247221                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247221                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      23142138                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         23142138                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     23142138                       # number of overall hits
-system.cpu.dcache.overall_hits::total        23142138                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       365459                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        365459                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       250152                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       250152                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        11183                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        11183                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       615611                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         615611                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       615611                       # number of overall misses
-system.cpu.dcache.overall_misses::total        615611                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data     13545525                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13545525                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10212224                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10212224                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247222                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       247222                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247221                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247221                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     23757749                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     23757749                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     23757749                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     23757749                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.026980                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.026980                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024495                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.024495                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045235                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045235                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.025912                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.025912                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.025912                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.025912                       # miss rate for overall accesses
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       592643                       # number of writebacks
-system.cpu.dcache.writebacks::total            592643                       # number of writebacks
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                59102649                       # Throughput (bytes/s)
-system.cpu.toL2Bus.data_through_bus         137875266                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.iocache.tags.replacements                         0                       # number of replacements
-system.iocache.tags.tagsinuse                            0                       # Cycle average of tags in use
-system.iocache.tags.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                         0                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                           nan                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status	Wed Aug 07 15:24:58 2013 -0500
@@ -1,1 +1,1 @@
-build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
+build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,18 +1,21 @@
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: DTB file specified, but no device tree support in kernel
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
-warn: 	instruction 'mcr bpiallis' unimplemented
-warn: 	instruction 'mcr icialluis' unimplemented
-warn: 	instruction 'mcr dccimvac' unimplemented
-warn: 	instruction 'mcr dccmvau' unimplemented
-warn: 	instruction 'mcr icimvau' unimplemented
-warn: 	instruction 'mcr bpiallis' unimplemented
-warn: LCD dual screen mode not supported
-warn: 	instruction 'mcr icialluis' unimplemented
-warn: 	instruction 'mcr icialluis' unimplemented
-hack: be nice to actually delete the event here
+Traceback (most recent call last):
+  File "<string>", line 1, in <module>
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/src/python/m5/main.py", line 387, in main
+    exec filecode in scope
+  File "tests/run.py", line 180, in <module>
+    execfile(joinpath(tests_root, 'configs', test_filename + '.py'))
+  File "tests/configs/realview-simple-timing-dual.py", line 42, in <module>
+    num_cpus=2).create_root()
+  File "tests/configs/base_config.py", line 230, in create_root
+    system = self.create_system()
+  File "tests/configs/arm_generic.py", line 65, in create_system
+    None, False)
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/FSConfig.py", line 265, in makeArmSystem
+    self.cf0.childImage(mdesc.disk())
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/Benchmarks.py", line 59, in disk
+    return env.get('LINUX_IMAGE', disk('linux-arm-ael.img'))
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 37, in disk
+    system()
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 59, in system
+    raise ImportError, "Can't find a path to system files."
+ImportError: Can't find a path to system files.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,14 +1,7 @@
-Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual/simout
-Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 26 2013 15:15:53
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-info: Using bootloader at address 0x80000000
-info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1183437503500 because m5_exit instruction encountered
+gem5 compiled Jul 17 2013 12:12:01
+gem5 started Jul 17 2013 12:12:10
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,1827 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  1.194911                       # Number of seconds simulated
-sim_ticks                                1194911360500                       # Number of ticks simulated
-final_tick                               1194911360500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 773513                       # Simulator instruction rate (inst/s)
-host_op_rate                                   985724                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            15060857671                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 403580                       # Number of bytes of host memory used
-host_seconds                                    79.34                       # Real time elapsed on the host
-sim_insts                                    61369589                       # Number of instructions simulated
-sim_ops                                      78206230                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd     51904512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker          256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           464036                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          6626228                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           256092                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2904304                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             62155620                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       464036                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       256092                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          720128                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4136576                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data       3027304                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7163920                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd       6488064                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker            4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             13469                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            103607                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              4083                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             45406                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               6654636                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           64634                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           756826                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               821470                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        43437960                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker           214                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker           107                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              388343                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             5545372                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker            54                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              214319                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             2430560                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                52016930                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         388343                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         214319                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             602662                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3461827                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data            2533497                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data                 33                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                5995357                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3461827                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       43437960                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          214                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker          107                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             388343                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            8078869                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker           54                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             214319                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            2430594                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               58012286                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       6654636                       # Total number of read requests seen
-system.physmem.writeReqs                       821470                       # Total number of write requests seen
-system.physmem.cpureqs                         235013                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                    425896704                       # Total number of bytes read from memory
-system.physmem.bytesWritten                  52574080                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd               62155620                       # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr                7163920                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                      138                       # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite              10632                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                415730                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                415559                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                414961                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                415336                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                422399                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                415419                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                415520                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                415301                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                415351                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                415631                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10               415270                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11               414902                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12               415547                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13               416081                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14               415762                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15               415729                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                 50036                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1                 49924                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2                 51325                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3                 51581                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4                 51864                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5                 51435                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6                 51646                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                 51467                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8                 51327                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9                 51592                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10                51318                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11                51082                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12                51567                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13                51872                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14                51738                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15                51696                       # Track writes on a per bank basis
-system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                    1194906959500                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::2                    6825                       # Categorize read packet sizes
-system.physmem.readPktSize::3                 6488064                       # Categorize read packet sizes
-system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                  159747                       # Categorize read packet sizes
-system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::2                 756836                       # Categorize write packet sizes
-system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::6                  64634                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                    581277                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    421174                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    435266                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   1590102                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                   1186915                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   1183214                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   1164468                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     13127                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     10448                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     15751                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    21053                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    15489                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     4169                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     4068                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     3980                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     3919                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       77                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                     35694                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                     35715                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                     35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                     35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                     35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                     35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                     35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                     35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                     35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                     35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                    35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                    35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                    35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                    35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                    35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    35716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        34668                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean    13801.223030                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     734.240341                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev   27780.651463                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-127          7945     22.92%     22.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-191         4005     11.55%     34.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-255         2676      7.72%     42.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-319         1963      5.66%     47.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-383         1415      4.08%     51.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-447         1138      3.28%     55.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-511          895      2.58%     57.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-575          859      2.48%     60.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-639          666      1.92%     62.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-703          565      1.63%     63.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-767          463      1.34%     65.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-831          439      1.27%     66.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-895          280      0.81%     67.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-959          254      0.73%     67.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-1023          189      0.55%     68.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1087          312      0.90%     69.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1151          134      0.39%     69.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1215          136      0.39%     70.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1279          130      0.37%     70.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1343           99      0.29%     70.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1407           89      0.26%     71.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1471          164      0.47%     71.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1535          949      2.74%     74.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1599          269      0.78%     75.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1663          135      0.39%     75.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1727          116      0.33%     75.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1791          100      0.29%     76.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1855           85      0.25%     76.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1919           65      0.19%     76.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1983           50      0.14%     76.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-2047           50      0.14%     76.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2111           59      0.17%     77.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2175           33      0.10%     77.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2239           32      0.09%     77.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2303           20      0.06%     77.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2367           23      0.07%     77.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2431           11      0.03%     77.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2495           23      0.07%     77.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2559           27      0.08%     77.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2623           12      0.03%     77.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2687           11      0.03%     77.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2751           15      0.04%     77.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2815            7      0.02%     77.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2879           13      0.04%     77.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2943            8      0.02%     77.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-3007           13      0.04%     77.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3071            9      0.03%     77.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3135           14      0.04%     77.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3199            9      0.03%     77.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3263           16      0.05%     77.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3327            6      0.02%     77.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3391            9      0.03%     77.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3455            7      0.02%     77.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3519            9      0.03%     77.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3583            6      0.02%     77.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3647            6      0.02%     77.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3711            8      0.02%     78.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3775            9      0.03%     78.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3839            8      0.02%     78.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3903            6      0.02%     78.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3967            7      0.02%     78.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-4031            9      0.03%     78.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4095            6      0.02%     78.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4159           45      0.13%     78.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4223            4      0.01%     78.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4287            6      0.02%     78.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4351            9      0.03%     78.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4415            2      0.01%     78.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4479            4      0.01%     78.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4543            6      0.02%     78.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4607            8      0.02%     78.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4671            6      0.02%     78.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4735            4      0.01%     78.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4799            3      0.01%     78.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4863            3      0.01%     78.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4927            5      0.01%     78.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4991            2      0.01%     78.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-5055            8      0.02%     78.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5119            2      0.01%     78.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5183            3      0.01%     78.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5247            1      0.00%     78.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5439            2      0.01%     78.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5503            1      0.00%     78.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5567            1      0.00%     78.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5631            5      0.01%     78.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5695            6      0.02%     78.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5759            2      0.01%     78.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5823            1      0.00%     78.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5887            1      0.00%     78.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5951            6      0.02%     78.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6079            6      0.02%     78.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6207          180      0.52%     79.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6271            1      0.00%     79.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6335            4      0.01%     79.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6399            1      0.00%     79.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6463            5      0.01%     79.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6527            1      0.00%     79.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6591            1      0.00%     79.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6655            1      0.00%     79.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6719            3      0.01%     79.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6783            2      0.01%     79.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6847           21      0.06%     79.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6911            2      0.01%     79.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6975            1      0.00%     79.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-7039            1      0.00%     79.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7103            2      0.01%     79.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7167            2      0.01%     79.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7231            6      0.02%     79.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7359            1      0.00%     79.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7423            1      0.00%     79.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7551            3      0.01%     79.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7615            3      0.01%     79.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7679            3      0.01%     79.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7743            3      0.01%     79.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7807            1      0.00%     79.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7871            3      0.01%     79.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7935            6      0.02%     79.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7999            6      0.02%     79.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8063            3      0.01%     79.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8127            7      0.02%     79.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8191            5      0.01%     79.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8255          319      0.92%     80.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8511            2      0.01%     80.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8767            1      0.00%     80.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-9023            1      0.00%     80.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9279            2      0.01%     80.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9408-9471            1      0.00%     80.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9472-9535            1      0.00%     80.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9600-9663            1      0.00%     80.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9984-10047            2      0.01%     80.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10303           18      0.05%     80.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10496-10559            2      0.01%     80.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11327            2      0.01%     80.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11583            1      0.00%     80.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11839            1      0.00%     80.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12095            1      0.00%     80.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12607            1      0.00%     80.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12863            2      0.01%     80.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12928-12991            1      0.00%     80.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13119            1      0.00%     80.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13375            3      0.01%     80.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13824-13887            1      0.00%     80.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14080-14143            1      0.00%     80.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14399            1      0.00%     80.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14784-14847            1      0.00%     80.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15167            2      0.01%     80.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15423            3      0.01%     80.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15616-15679            1      0.00%     80.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16447            1      0.00%     80.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16640-16703            2      0.01%     80.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16832-16895            1      0.00%     80.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16896-16959            2      0.01%     80.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17152-17215            2      0.01%     80.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17664-17727            1      0.00%     80.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18176-18239            2      0.01%     80.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18432-18495            1      0.00%     80.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18752-18815            1      0.00%     80.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19328-19391            1      0.00%     80.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19456-19519            4      0.01%     80.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19712-19775            1      0.00%     80.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20224-20287            1      0.00%     80.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20480-20543           13      0.04%     80.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20736-20799            1      0.00%     80.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20992-21055            2      0.01%     80.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21504-21567            2      0.01%     80.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21760-21823            1      0.00%     80.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22016-22079            2      0.01%     80.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22272-22335            2      0.01%     80.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22528-22591            1      0.00%     80.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22784-22847            1      0.00%     80.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23552-23615            4      0.01%     80.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24320-24383            2      0.01%     80.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24576-24639            4      0.01%     80.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25344-25407            1      0.00%     80.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25600-25663            3      0.01%     80.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25856-25919            1      0.00%     80.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26112-26175            2      0.01%     80.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26368-26431            3      0.01%     80.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26624-26687            2      0.01%     80.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27392-27455            2      0.01%     80.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27648-27711            1      0.00%     80.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28416-28479            1      0.00%     80.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28672-28735            1      0.00%     80.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29312-29375            1      0.00%     80.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29504-29567            1      0.00%     80.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29696-29759            3      0.01%     80.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29952-30015            1      0.00%     80.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30208-30271            2      0.01%     80.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30400-30463            1      0.00%     80.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30464-30527            3      0.01%     80.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30720-30783            6      0.02%     80.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31232-31295            2      0.01%     80.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31488-31551            3      0.01%     80.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31744-31807            2      0.01%     80.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31872-31935            1      0.00%     80.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32256-32319            1      0.00%     80.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32512-32575            1      0.00%     80.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33024-33087           16      0.05%     80.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33088-33151            1      0.00%     80.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33152-33215            2      0.01%     80.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33280-33343           36      0.10%     80.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34304-34367            1      0.00%     80.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35584-35647            1      0.00%     80.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35840-35903            1      0.00%     80.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38144-38207            1      0.00%     80.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38400-38463            1      0.00%     80.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39488-39551            1      0.00%     80.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41216-41279            1      0.00%     80.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41344-41407            1      0.00%     80.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41984-42047            1      0.00%     80.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43008-43071            1      0.00%     80.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43584-43647            1      0.00%     80.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44032-44095            1      0.00%     80.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44544-44607            1      0.00%     80.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45056-45119            1      0.00%     80.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45824-45887            1      0.00%     80.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48640-48703            2      0.01%     80.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49152-49215            1      0.00%     80.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50176-50239            1      0.00%     80.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50432-50495            2      0.01%     80.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51520-51583            1      0.00%     80.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::52224-52287            4      0.01%     80.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::52800-52863            1      0.00%     80.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::54272-54335            2      0.01%     80.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::55296-55359            1      0.00%     80.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::56064-56127            1      0.00%     80.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::56320-56383            2      0.01%     80.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::61440-61503            2      0.01%     81.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::61696-61759            1      0.00%     81.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::62080-62143            1      0.00%     81.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::62208-62271            1      0.00%     81.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::62464-62527            1      0.00%     81.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::62976-63039            1      0.00%     81.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::63488-63551            2      0.01%     81.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64512-64575            2      0.01%     81.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64832-64895            1      0.00%     81.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65024-65087            6      0.02%     81.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65152-65215            2      0.01%     81.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65216-65279            1      0.00%     81.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65344-65407            1      0.00%     81.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65472-65535            6      0.02%     81.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65536-65599         6196     17.87%     98.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::72768-72831            1      0.00%     98.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::73920-73983            1      0.00%     98.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::75008-75071            1      0.00%     98.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::82944-83007            1      0.00%     98.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::84480-84543            1      0.00%     98.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::85376-85439            1      0.00%     98.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::85568-85631            1      0.00%     98.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::94656-94719            1      0.00%     98.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::95552-95615            1      0.00%     98.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::98944-99007            1      0.00%     98.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::99520-99583            1      0.00%     98.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::109120-109183            1      0.00%     98.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::109696-109759            1      0.00%     98.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::110080-110143            1      0.00%     98.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::117440-117503            1      0.00%     98.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::117952-118015            1      0.00%     98.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::120256-120319            1      0.00%     98.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::120640-120703            1      0.00%     99.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::121152-121215            1      0.00%     99.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::129856-129919            1      0.00%     99.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::130112-130175            1      0.00%     99.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::131072-131135          336      0.97%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::131200-131263            1      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::132096-132159            3      0.01%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::136576-136639            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::196160-196223            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::196608-196671            2      0.01%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::420352-420415            1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          34668                       # Bytes accessed per row activation
-system.physmem.totQLat                   132807422500                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat              174630638750                       # Sum of mem lat for all requests
-system.physmem.totBusLat                  33272490000                       # Total cycles spent in databus access
-system.physmem.totBankLat                  8550726250                       # Total cycles spent in bank access
-system.physmem.avgQLat                       19957.54                       # Average queueing delay per request
-system.physmem.avgBankLat                     1284.95                       # Average bank access latency per request
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
-system.physmem.avgMemAccLat                  26242.50                       # Average memory access latency
-system.physmem.avgRdBW                         356.43                       # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW                          44.00                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                  52.02                       # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW                   6.00                       # Average consumed write bandwidth in MB/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil                           3.13                       # Data bus utilization in percentage
-system.physmem.avgRdQLen                         0.15                       # Average read queue length over time
-system.physmem.avgWrQLen                        11.97                       # Average write queue length over time
-system.physmem.readRowHits                    6636574                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    804724                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   99.73                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  97.96                       # Row buffer hit rate for writes
-system.physmem.avgGap                       159830.13                       # Average gap between requests
-system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst           17                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst           40                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               57                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst           40                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total           57                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst           17                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst           40                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              57                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     60028739                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq             7703151                       # Transaction distribution
-system.membus.trans_dist::ReadResp            7703151                       # Transaction distribution
-system.membus.trans_dist::WriteReq             767201                       # Transaction distribution
-system.membus.trans_dist::WriteResp            767201                       # Transaction distribution
-system.membus.trans_dist::Writeback             64634                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            27614                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          16407                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           10632                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            137758                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           137302                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382564                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1966559                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         8856                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio          906                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4358923                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     12976128                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total     12976128                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.bridge.slave      2382564                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.physmem.port     14942687                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.gic.pio         8856                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.local_cpu_timer.pio          906                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               17335051                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2389882                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17415028                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        17712                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         1812                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     19824510                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port     51904512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total     51904512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.bridge.slave      2389882                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.physmem.port     69319540                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.gic.pio        17712                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio         1812                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            71729022                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               71729022                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1208299500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               18000                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy          9149149500                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.8                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy             7960500                       # Layer occupancy (ticks)
-system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy                2500                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy              777000                       # Layer occupancy (ticks)
-system.membus.reqLayer6.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         5034294617                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        14663453747                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              1.2                       # Layer utilization (%)
-system.l2c.tags.replacements                         69629                       # number of replacements
-system.l2c.tags.tagsinuse                     53155.534639                       # Cycle average of tags in use
-system.l2c.tags.total_refs                         1651678                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                        134776                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                         12.254986                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks        40041.185718                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker       2.667860                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker       0.001521                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst          4638.655043                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data          5789.348152                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker       0.001660                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst          1927.060090                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data           756.614595                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks           0.610980                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker      0.000041                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst            0.070780                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data            0.088338                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker      0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst            0.029405                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data            0.011545                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total                0.811089                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker         4625                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         1507                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             482925                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             242050                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         3554                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         1806                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             372304                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             110721                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1219492                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          576641                       # number of Writeback hits
-system.l2c.Writeback_hits::total               576641                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            1408                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             418                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                1826                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           257                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            96                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               353                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            65574                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            45429                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               111003                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          4625                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          1507                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              482925                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              307624                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          3554                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          1806                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              372304                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              156150                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1330495                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         4625                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         1507                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             482925                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             307624                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         3554                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         1806                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             372304                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             156150                       # number of overall hits
-system.l2c.overall_hits::total                1330495                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker            4                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             6837                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             9715                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             3996                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             1891                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                22446                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          3988                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          3371                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              7359                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          387                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          473                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total             860                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          95120                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          44595                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             139715                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker            4                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              6837                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            104835                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              3996                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             46486                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                162161                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker            4                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             6837                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           104835                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             3996                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            46486                       # number of overall misses
-system.l2c.overall_misses::total               162161                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       395750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker       122500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst    486019750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data    691389999                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker        89250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    282135750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    152148250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1612301249                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data     11489505                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     12402970                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     23892475                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1837921                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1069454                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      2907375                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   6199806193                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   2820905645                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   9020711838                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker       395750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker       122500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    486019750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   6891196192                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker        89250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    282135750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   2973053895                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     10633013087                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker       395750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker       122500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    486019750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   6891196192                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker        89250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    282135750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   2973053895                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    10633013087                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         4629                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         1509                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         489762                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         251765                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         3554                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         1807                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         376300                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         112612                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1241938                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       576641                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           576641                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         5396                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         3789                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            9185                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          644                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          569                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1213                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       160694                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        90024                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           250718                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         4629                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         1509                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          489762                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          412459                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         3554                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         1807                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          376300                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          202636                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1492656                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         4629                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         1509                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         489762                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         412459                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         3554                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         1807                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         376300                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         202636                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1492656                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000864                       # miss rate for ReadReq accesses
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-system.l2c.ReadReq_miss_rate::cpu0.inst      0.013960                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.038588                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000553                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.010619                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.016792                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.018073                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.739066                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.889681                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.801198                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.600932                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.831283                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.708986                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.591932                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.495368                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.557260                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000864                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.001325                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.013960                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.254171                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.000553                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.010619                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.229406                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.108639                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000864                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.001325                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.013960                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.254171                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.000553                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.010619                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.229406                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.108639                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 98937.500000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        61250                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71086.697382                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 71167.267010                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        89250                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70604.542042                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 80459.148599                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 71830.225831                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2881.019308                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3679.314743                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  3246.701318                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  4749.149871                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2261.002114                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  3380.668605                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65178.786722                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 63256.096984                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 64565.092066                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 98937.500000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker        61250                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 71086.697382                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 65733.735794                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker        89250                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 70604.542042                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 63955.898443                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 65570.717293                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 98937.500000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker        61250                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 71086.697382                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 65733.735794                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.inst 70604.542042                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 63955.898443                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 65570.717293                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               64634                       # number of writebacks
-system.l2c.writebacks::total                    64634                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
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-system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
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-system.l2c.ReadReq_mshr_misses::cpu1.data         1891                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           22445                       # number of ReadReq MSHR misses
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-system.l2c.UpgradeReq_mshr_misses::cpu1.data         3371                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         7359                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          387                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          473                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total          860                       # number of SCUpgradeReq MSHR misses
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-system.l2c.demand_mshr_misses::cpu0.dtb.walker            4                       # number of demand (read+write) MSHR misses
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-system.l2c.demand_mshr_misses::cpu0.data       104835                       # number of demand (read+write) MSHR misses
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-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    231686750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    128101750                       # number of ReadReq MSHR miss cycles
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-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     33802856                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     73714839                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      3872886                       # number of SCUpgradeReq MSHR miss cycles
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-system.l2c.SCUpgradeReq_mshr_miss_latency::total      8604359                       # number of SCUpgradeReq MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       344250                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu1.inst    231686750                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::cpu1.data   2389111603                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   8596546655                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    340200250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12647628243                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      4849500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154070714500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 167063392493                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data  16272290763                       # number of WriteReq MSHR uncacheable cycles
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-system.l2c.WriteReq_mshr_uncacheable_latency::total  16758493263                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    340200250                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  28919919006                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      4849500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154556917000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 183821885756                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000864                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.001325                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.013958                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.038588                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000553                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010619                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.016792                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.018073                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.739066                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.889681                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.801198                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.600932                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.831283                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.708986                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.591932                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.495368                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.557260                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000864                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.001325                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.013958                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.254171                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000553                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010619                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.229406                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.108639                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000864                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.001325                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.013958                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.254171                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000553                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010619                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.229406                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.108639                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86062.500000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        48750                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58465.842598                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58485.331858                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        76250                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57979.667167                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67742.860920                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 59174.159011                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10008.019809                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.545535                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10016.964126                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10007.457364                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.114165                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10005.068605                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52642.691369                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50700.972149                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 52022.922779                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86062.500000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        48750                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58465.842598                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53184.125550                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        76250                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57979.667167                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51394.217678                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 53012.744542                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86062.500000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        48750                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58465.842598                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53184.125550                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        76250                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57979.667167                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51394.217678                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 53012.744542                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                   118431561                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2504925                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2504925                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            767201                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           767201                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           576641                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           27027                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         16760                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          43787                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           262499                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          262499                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side       993555                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side      2951402                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma         5905                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma        15026                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side       753554                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side      2880607                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma         6133                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma        11768                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count                      7617950                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side     31371320                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side     53730420                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma         6036                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma        18516                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side     24083596                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side     27977862                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma         7228                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma        14216                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size                 137209194                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             137209194                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus         4306024                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         4767819743                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2217282985                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        2471819696                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy           4396500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          10398000                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy        1697865710                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy        2215426419                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy           4326250                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy           8214499                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                      45438010                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq              7671400                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             7671400                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                7946                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               7946                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30448                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8062                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          740                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          496                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2382564                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     12976128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total     12976128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart.pio        30448                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.realview_io.pio         8062                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer1.pio          740                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi1.pio          496                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side     12976128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                15358692                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40166                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16124                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         1480                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          272                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2389882                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side     51904512                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total     51904512                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart.pio        40166                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.realview_io.pio        16124                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer1.pio         1480                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi1.pio          272                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side     51904512                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total             54294394                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                54294394                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy             21350000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              4037000                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               376000                       # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy               298000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization                0.1                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy          6488064000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.5                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2374618000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.2                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         17765827253                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
-system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     9651794                       # DTB read hits
-system.cpu0.dtb.read_misses                      3741                       # DTB read misses
-system.cpu0.dtb.write_hits                    7596285                       # DTB write hits
-system.cpu0.dtb.write_misses                     1585                       # DTB write misses
-system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    1811                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   138                       # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 9655535                       # DTB read accesses
-system.cpu0.dtb.write_accesses                7597870                       # DTB write accesses
-system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         17248079                       # DTB hits
-system.cpu0.dtb.misses                           5326                       # DTB misses
-system.cpu0.dtb.accesses                     17253405                       # DTB accesses
-system.cpu0.itb.inst_hits                    43295611                       # ITB inst hits
-system.cpu0.itb.inst_misses                      2205                       # ITB inst misses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1332                       # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                43297816                       # ITB inst accesses
-system.cpu0.itb.hits                         43295611                       # DTB hits
-system.cpu0.itb.misses                           2205                       # DTB misses
-system.cpu0.itb.accesses                     43297816                       # DTB accesses
-system.cpu0.numCycles                      2389822721                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   42568710                       # Number of instructions committed
-system.cpu0.committedOps                     53298123                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             48055390                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  3860                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1403445                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      5582451                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    48055390                       # number of integer instructions
-system.cpu0.num_fp_insts                         3860                       # number of float instructions
-system.cpu0.num_int_register_reads          272420788                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          52266741                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3022                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                840                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     18017454                       # number of memory refs
-system.cpu0.num_load_insts                   10035613                       # Number of load instructions
-system.cpu0.num_store_insts                   7981841                       # Number of store instructions
-system.cpu0.num_idle_cycles              2150296210.870201                       # Number of idle cycles
-system.cpu0.num_busy_cycles              239526510.129800                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.100228                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.899772                       # Percentage of idle cycles
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   51308                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements                490004                       # number of replacements
-system.cpu0.icache.tags.tagsinuse               509.392438                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs                42805077                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs                490516                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs                 87.265404                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle           76030513250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.392438                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.994907                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total        0.994907                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst     42805077                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       42805077                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     42805077                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        42805077                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     42805077                       # number of overall hits
-system.cpu0.icache.overall_hits::total       42805077                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       490517                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       490517                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       490517                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        490517                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       490517                       # number of overall misses
-system.cpu0.icache.overall_misses::total       490517                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   6812396235                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   6812396235                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   6812396235                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   6812396235                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   6812396235                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   6812396235                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     43295594                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     43295594                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     43295594                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     43295594                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     43295594                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     43295594                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011329                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.011329                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011329                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.011329                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011329                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.011329                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13888.195995                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13888.195995                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13888.195995                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13888.195995                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13888.195995                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13888.195995                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       490517                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       490517                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       490517                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       490517                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       490517                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       490517                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5828002765                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   5828002765                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5828002765                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   5828002765                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5828002765                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   5828002765                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    431776750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    431776750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    431776750                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    431776750                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.011329                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011329                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.011329                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.011329                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.011329                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.011329                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11881.347160                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11881.347160                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11881.347160                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11881.347160                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11881.347160                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11881.347160                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements                406612                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse               470.882465                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs                15965290                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs                407124                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs                 39.214809                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle             659626250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   470.882465                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.919692                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total        0.919692                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      9135819                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        9135819                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      6493762                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       6493762                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       156506                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       156506                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       158999                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       158999                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     15629581                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        15629581                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     15629581                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       15629581                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       263761                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       263761                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       176647                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       176647                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9920                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         9920                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7375                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7375                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       440408                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        440408                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       440408                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       440408                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3882137498                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   3882137498                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   7549327791                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   7549327791                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     98498000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total     98498000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     40527887                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     40527887                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  11431465289                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  11431465289                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  11431465289                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  11431465289                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      9399580                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      9399580                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      6670409                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      6670409                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       166426                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       166426                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       166374                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       166374                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     16069989                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     16069989                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     16069989                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     16069989                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.028061                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.028061                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.026482                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.026482                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059606                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059606                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.044328                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.044328                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027406                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.027406                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027406                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.027406                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14718.390884                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14718.390884                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42736.801593                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 42736.801593                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data  9929.233871                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9929.233871                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5495.306712                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5495.306712                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25956.534143                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 25956.534143                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25956.534143                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 25956.534143                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       376581                       # number of writebacks
-system.cpu0.dcache.writebacks::total           376581                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       263761                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       263761                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       176647                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       176647                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9920                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9920                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7371                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         7371                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       440408                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       440408                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       440408                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       440408                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3349960502                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3349960502                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7149928209                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7149928209                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     78594000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     78594000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     25787113                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     25787113                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10499888711                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  10499888711                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10499888711                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  10499888711                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13764207250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13764207250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  25807935730                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  25807935730                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  39572142980                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  39572142980                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.028061                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.028061                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.026482                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.026482                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059606                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059606                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.044304                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.044304                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027406                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.027406                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.027406                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.027406                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12700.742346                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12700.742346                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40475.797545                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40475.797545                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7922.782258                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7922.782258                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  3498.455162                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  3498.455162                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23841.276069                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23841.276069                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23841.276069                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23841.276069                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     5707792                       # DTB read hits
-system.cpu1.dtb.read_misses                      3579                       # DTB read misses
-system.cpu1.dtb.write_hits                    3874264                       # DTB write hits
-system.cpu1.dtb.write_misses                      643                       # DTB write misses
-system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1989                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   150                       # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 5711371                       # DTB read accesses
-system.cpu1.dtb.write_accesses                3874907                       # DTB write accesses
-system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          9582056                       # DTB hits
-system.cpu1.dtb.misses                           4222                       # DTB misses
-system.cpu1.dtb.accesses                      9586278                       # DTB accesses
-system.cpu1.itb.inst_hits                    19381456                       # ITB inst hits
-system.cpu1.itb.inst_misses                      2171                       # ITB inst misses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1495                       # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                19383627                       # ITB inst accesses
-system.cpu1.itb.hits                         19381456                       # DTB hits
-system.cpu1.itb.misses                           2171                       # DTB misses
-system.cpu1.itb.accesses                     19383627                       # DTB accesses
-system.cpu1.numCycles                      2388389320                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   18800879                       # Number of instructions committed
-system.cpu1.committedOps                     24908107                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             22271769                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  6793                       # Number of float alu accesses
-system.cpu1.num_func_calls                     796713                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      2514831                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    22271769                       # number of integer instructions
-system.cpu1.num_fp_insts                         6793                       # number of float instructions
-system.cpu1.num_int_register_reads          130796956                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          23323418                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                4535                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               2260                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     10017504                       # number of memory refs
-system.cpu1.num_load_insts                    5984439                       # Number of load instructions
-system.cpu1.num_store_insts                   4033065                       # Number of store instructions
-system.cpu1.num_idle_cycles              1968748229.220572                       # Number of idle cycles
-system.cpu1.num_busy_cycles              419641090.779428                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.175700                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.824300                       # Percentage of idle cycles
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   39064                       # number of quiesce instructions executed
-system.cpu1.icache.tags.replacements                376544                       # number of replacements
-system.cpu1.icache.tags.tagsinuse               474.938465                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs                19004396                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs                377056                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs                 50.402052                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle          327017678500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   474.938465                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.927614                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total        0.927614                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst     19004396                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       19004396                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     19004396                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        19004396                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     19004396                       # number of overall hits
-system.cpu1.icache.overall_hits::total       19004396                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       377056                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       377056                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       377056                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        377056                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       377056                       # number of overall misses
-system.cpu1.icache.overall_misses::total       377056                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5154731460                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   5154731460                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   5154731460                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   5154731460                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   5154731460                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   5154731460                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     19381452                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     19381452                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     19381452                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     19381452                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     19381452                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     19381452                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.019454                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.019454                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.019454                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.019454                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.019454                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.019454                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13670.997040                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13670.997040                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13670.997040                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13670.997040                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13670.997040                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13670.997040                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       377056                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       377056                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       377056                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       377056                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       377056                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       377056                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4398633040                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   4398633040                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4398633040                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   4398633040                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4398633040                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   4398633040                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6184500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6184500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6184500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      6184500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.019454                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.019454                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.019454                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.019454                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.019454                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.019454                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11665.728804                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11665.728804                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11665.728804                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11665.728804                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11665.728804                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11665.728804                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements                220840                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse               471.619758                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs                 8232994                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs                221207                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs                 37.218506                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle          106228428000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   471.619758                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.921132                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total        0.921132                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data      4390579                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        4390579                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      3674302                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       3674302                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        73464                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        73464                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        73742                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        73742                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      8064881                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         8064881                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      8064881                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        8064881                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       133951                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       133951                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       112879                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       112879                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         9745                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         9745                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         9392                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         9392                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       246830                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        246830                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       246830                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       246830                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1653824236                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   1653824236                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   3737179210                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   3737179210                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     78087000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     78087000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     49049473                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     49049473                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   5391003446                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   5391003446                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   5391003446                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   5391003446                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      4524530                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      4524530                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      3787181                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      3787181                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        83209                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        83209                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        83134                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        83134                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      8311711                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      8311711                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      8311711                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      8311711                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.029606                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.029606                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.029806                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.029806                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.117115                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.117115                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.112974                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.112974                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.029697                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.029697                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.029697                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.029697                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12346.486670                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12346.486670                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33107.834141                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 33107.834141                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  8013.032324                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8013.032324                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5222.473701                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5222.473701                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21840.957120                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 21840.957120                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21840.957120                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 21840.957120                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       200060                       # number of writebacks
-system.cpu1.dcache.writebacks::total           200060                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       133951                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       133951                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       112879                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       112879                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         9745                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         9745                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         9391                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         9391                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       246830                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       246830                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       246830                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       246830                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1384995764                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1384995764                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   3490409790                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   3490409790                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     58580000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     58580000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     30268527                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     30268527                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4875405554                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4875405554                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4875405554                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   4875405554                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168372273000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168372273000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    531015000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    531015000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168903288000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168903288000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.029606                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.029606                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.029806                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.029806                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.117115                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.117115                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.112962                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.112962                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029697                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.029697                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.029697                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.029697                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10339.570171                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10339.570171                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30921.693052                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30921.693052                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6011.287840                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6011.287840                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3223.142051                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3223.142051                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19752.078572                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19752.078572                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19752.078572                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19752.078572                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements                         0                       # number of replacements
-system.iocache.tags.tagsinuse                            0                       # Cycle average of tags in use
-system.iocache.tags.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                         0                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                           nan                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 624927975253                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 624927975253                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 624927975253                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 624927975253                       # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status	Wed Aug 07 15:24:58 2013 -0500
@@ -1,1 +1,1 @@
-build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual FAILED!
+build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual FAILED!
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,16 +1,21 @@
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
-warn: 	instruction 'mcr bpiallis' unimplemented
-warn: 	instruction 'mcr icialluis' unimplemented
-warn: 	instruction 'mcr dccimvac' unimplemented
-warn: 	instruction 'mcr dccmvau' unimplemented
-warn: 	instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
-warn: 	instruction 'mcr icialluis' unimplemented
-warn: 	instruction 'mcr bpiallis' unimplemented
-hack: be nice to actually delete the event here
+Traceback (most recent call last):
+  File "<string>", line 1, in <module>
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/src/python/m5/main.py", line 387, in main
+    exec filecode in scope
+  File "tests/run.py", line 180, in <module>
+    execfile(joinpath(tests_root, 'configs', test_filename + '.py'))
+  File "tests/configs/realview-simple-timing.py", line 42, in <module>
+    cpu_class=TimingSimpleCPU).create_root()
+  File "tests/configs/base_config.py", line 230, in create_root
+    system = self.create_system()
+  File "tests/configs/arm_generic.py", line 65, in create_system
+    None, False)
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/FSConfig.py", line 265, in makeArmSystem
+    self.cf0.childImage(mdesc.disk())
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/Benchmarks.py", line 59, in disk
+    return env.get('LINUX_IMAGE', disk('linux-arm-ael.img'))
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 37, in disk
+    system()
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 59, in system
+    raise ImportError, "Can't find a path to system files."
+ImportError: Can't find a path to system files.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,14 +1,7 @@
-Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:45:50
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-info: Using bootloader at address 0x80000000
-info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2603634694000 because m5_exit instruction encountered
+gem5 compiled Jul 17 2013 12:12:01
+gem5 started Jul 17 2013 12:12:09
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,1309 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  2.615733                       # Number of seconds simulated
-sim_ticks                                2615733285000                       # Number of ticks simulated
-final_tick                               2615733285000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 250012                       # Simulator instruction rate (inst/s)
-host_op_rate                                   318151                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            10863402189                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 396412                       # Number of bytes of host memory used
-host_seconds                                   240.78                       # Real time elapsed on the host
-sim_insts                                    60198861                       # Number of instructions simulated
-sim_ops                                      76605713                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd    122683392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            704864                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9093712                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            132482416                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       704864                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          704864                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3710144                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6726216                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      15335424                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              17216                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142123                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15494770                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57971                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811989                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        46902103                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            122                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             49                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               269471                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3476544                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                50648289                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          269471                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             269471                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1418395                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1153050                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2571446                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1418395                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       46902103                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           122                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            49                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              269471                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4629594                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53219735                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15494770                       # Total number of read requests seen
-system.physmem.writeReqs                       811989                       # Total number of write requests seen
-system.physmem.cpureqs                         215180                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                    991665280                       # Total number of bytes read from memory
-system.physmem.bytesWritten                  51967296                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd              132482416                       # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr                6726216                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                      299                       # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite               4515                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                968107                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                967905                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                967771                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                967944                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                974725                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                968490                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                967971                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                967840                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                968519                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                968300                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10               967957                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11               967809                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12               967935                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13               967629                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14               967887                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15               967682                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                 49150                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1                 49013                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2                 50857                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3                 50909                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4                 51128                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5                 51425                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6                 51159                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                 51254                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8                 51364                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9                 51157                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10                50876                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11                50797                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12                50874                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13                50522                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14                50827                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15                50677                       # Track writes on a per bank basis
-system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                    2615728912000                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::2                    6652                       # Categorize read packet sizes
-system.physmem.readPktSize::3                15335424                       # Categorize read packet sizes
-system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                  152694                       # Categorize read packet sizes
-system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::2                 754018                       # Categorize write packet sizes
-system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::6                  57971                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                   1128832                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    975833                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                   1007328                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   3775576                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                   2827750                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   2822812                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2787859                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     21456                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     18919                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     32464                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    45819                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    32079                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     4562                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     4458                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     4371                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     4308                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       45                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                     35288                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                     35301                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                     35303                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                     35304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                     35304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                     35304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                     35304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                     35304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                     35304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                     35304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                    35304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                    35304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                    35304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                    35304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                    35304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    35304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    35304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    35304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    35304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    35304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    35303                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    35303                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    35303                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        38488                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean    27115.229266                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean    2500.122459                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev   33119.773163                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-127          5498     14.28%     14.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-191         3288      8.54%     22.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-255         2221      5.77%     28.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-319         1687      4.38%     32.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-383         1187      3.08%     36.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-447         1056      2.74%     38.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-511          814      2.11%     40.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-575          739      1.92%     42.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-639          550      1.43%     44.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-703          512      1.33%     45.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-767          421      1.09%     46.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-831          397      1.03%     47.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-895          314      0.82%     48.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-959          250      0.65%     49.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-1023          198      0.51%     49.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1087          236      0.61%     50.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1151          133      0.35%     50.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1215          138      0.36%     51.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1279           98      0.25%     51.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1343          109      0.28%     51.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1407           78      0.20%     51.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1471          154      0.40%     52.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1535          969      2.52%     54.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1599          195      0.51%     55.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1663          143      0.37%     55.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1727          120      0.31%     55.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1791           89      0.23%     56.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1855           73      0.19%     56.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1919           63      0.16%     56.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1983           55      0.14%     56.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-2047           51      0.13%     56.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2111           51      0.13%     56.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2175           31      0.08%     56.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2239           29      0.08%     57.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2303           27      0.07%     57.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2367           16      0.04%     57.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2431           18      0.05%     57.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2495           16      0.04%     57.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2559           22      0.06%     57.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2623           11      0.03%     57.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2687           16      0.04%     57.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2751            9      0.02%     57.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2815           14      0.04%     57.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2879           16      0.04%     57.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2943           11      0.03%     57.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-3007           14      0.04%     57.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3071            8      0.02%     57.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3135           19      0.05%     57.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3199            9      0.02%     57.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3263            4      0.01%     57.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3327           13      0.03%     57.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3391           10      0.03%     57.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3455            6      0.02%     57.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3519            7      0.02%     57.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3583            3      0.01%     57.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3647            6      0.02%     57.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3711           13      0.03%     57.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3775           10      0.03%     57.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3839            5      0.01%     57.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3903           10      0.03%     57.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3967            3      0.01%     57.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-4031            7      0.02%     57.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4095            8      0.02%     57.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4159           40      0.10%     57.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4223            2      0.01%     57.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4287            4      0.01%     58.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4351            3      0.01%     58.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4415            6      0.02%     58.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4479            4      0.01%     58.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4543            3      0.01%     58.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4607            5      0.01%     58.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4671            6      0.02%     58.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4735            1      0.00%     58.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4799            1      0.00%     58.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4863            3      0.01%     58.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4927            9      0.02%     58.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4991            2      0.01%     58.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-5055            3      0.01%     58.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5119            2      0.01%     58.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5183            9      0.02%     58.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5247            2      0.01%     58.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5311            5      0.01%     58.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5375            4      0.01%     58.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5439            3      0.01%     58.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5503            5      0.01%     58.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5567            4      0.01%     58.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5631            4      0.01%     58.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5695            6      0.02%     58.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5759            2      0.01%     58.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5951            4      0.01%     58.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-6015            1      0.00%     58.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6079            2      0.01%     58.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6143            1      0.00%     58.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6207          184      0.48%     58.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6271            2      0.01%     58.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6335            1      0.00%     58.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6463            2      0.01%     58.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6527            3      0.01%     58.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6591            4      0.01%     58.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6655            1      0.00%     58.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6719            2      0.01%     58.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6783            1      0.00%     58.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6847           15      0.04%     58.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6911            3      0.01%     58.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6975            1      0.00%     58.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-7039            2      0.01%     58.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7103            3      0.01%     58.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7231            4      0.01%     58.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7295            4      0.01%     58.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7359            1      0.00%     58.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7487            2      0.01%     58.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7551            3      0.01%     58.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7615            5      0.01%     58.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7679            3      0.01%     58.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7743            6      0.02%     58.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7807            4      0.01%     58.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7871            4      0.01%     58.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7935            4      0.01%     58.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7999            1      0.00%     58.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8063            1      0.00%     58.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8127            6      0.02%     58.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8191            3      0.01%     58.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8255          327      0.85%     59.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8256-8319            1      0.00%     59.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8576-8639            1      0.00%     59.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8767            1      0.00%     59.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8832-8895            1      0.00%     59.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9279            5      0.01%     59.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9728-9791            1      0.00%     59.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9856-9919            1      0.00%     59.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9984-10047            1      0.00%     59.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10112-10175            2      0.01%     59.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10303           20      0.05%     59.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10624-10687            1      0.00%     59.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11071            1      0.00%     59.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12095            1      0.00%     59.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12351            2      0.01%     59.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12607            1      0.00%     59.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12672-12735            1      0.00%     59.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12863            1      0.00%     59.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13119            1      0.00%     59.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13696-13759            1      0.00%     59.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13824-13887            1      0.00%     59.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14080-14143            2      0.01%     59.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14399            3      0.01%     59.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15423            4      0.01%     59.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15616-15679            1      0.00%     59.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15680-15743            1      0.00%     59.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16128-16191            1      0.00%     59.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16447            1      0.00%     59.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17024-17087            1      0.00%     59.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17152-17215            3      0.01%     59.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17920-17983            1      0.00%     59.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18048-18111            1      0.00%     59.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18176-18239            1      0.00%     60.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18304-18367            1      0.00%     60.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18432-18495            3      0.01%     60.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18688-18751            1      0.00%     60.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19200-19263            1      0.00%     60.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19456-19519            1      0.00%     60.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19712-19775            2      0.01%     60.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19968-20031            1      0.00%     60.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20096-20159            1      0.00%     60.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20288-20351            1      0.00%     60.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20480-20543            1      0.00%     60.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20736-20799            1      0.00%     60.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21248-21311            1      0.00%     60.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21504-21567            1      0.00%     60.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21760-21823            1      0.00%     60.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22016-22079            1      0.00%     60.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22272-22335            2      0.01%     60.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22400-22463            1      0.00%     60.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22528-22591            3      0.01%     60.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23040-23103            2      0.01%     60.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23296-23359            1      0.00%     60.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23424-23487            1      0.00%     60.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23552-23615            2      0.01%     60.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23808-23871            1      0.00%     60.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24064-24127            1      0.00%     60.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24576-24639            2      0.01%     60.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24832-24895            2      0.01%     60.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25088-25151            2      0.01%     60.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25216-25279            1      0.00%     60.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25344-25407            2      0.01%     60.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25600-25663            1      0.00%     60.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25664-25727            1      0.00%     60.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25792-25855            1      0.00%     60.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26112-26175            1      0.00%     60.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26240-26303            1      0.00%     60.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26368-26431            2      0.01%     60.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26624-26687            1      0.00%     60.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26880-26943            2      0.01%     60.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27392-27455            1      0.00%     60.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27648-27711            3      0.01%     60.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28672-28735            2      0.01%     60.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28928-28991            2      0.01%     60.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29184-29247            1      0.00%     60.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29312-29375            1      0.00%     60.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29440-29503            1      0.00%     60.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29632-29695            1      0.00%     60.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29696-29759            2      0.01%     60.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30272-30335            1      0.00%     60.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30464-30527            1      0.00%     60.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30720-30783            4      0.01%     60.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30848-30911            1      0.00%     60.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31424-31487            1      0.00%     60.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31488-31551            1      0.00%     60.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31744-31807            3      0.01%     60.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32256-32319            1      0.00%     60.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32512-32575            1      0.00%     60.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32768-32831            2      0.01%     60.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33024-33087           16      0.04%     60.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33088-33151            1      0.00%     60.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33152-33215           24      0.06%     60.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33280-33343           16      0.04%     60.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33792-33855            1      0.00%     60.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34816-34879            1      0.00%     60.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35072-35135            1      0.00%     60.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36864-36927            1      0.00%     60.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37888-37951            1      0.00%     60.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39168-39231            1      0.00%     60.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39424-39487            1      0.00%     60.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40704-40767            1      0.00%     60.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40960-41023            1      0.00%     60.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41984-42047            2      0.01%     60.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42496-42559            1      0.00%     60.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42752-42815            1      0.00%     60.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43008-43071            1      0.00%     60.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43264-43327            1      0.00%     60.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44032-44095            1      0.00%     60.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44992-45055            1      0.00%     60.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47104-47167            2      0.01%     60.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47616-47679            1      0.00%     60.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48128-48191            1      0.00%     60.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49152-49215            1      0.00%     60.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49920-49983            1      0.00%     60.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50176-50239            1      0.00%     60.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50432-50495            1      0.00%     60.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51200-51263            2      0.01%     60.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51456-51519            1      0.00%     60.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::52736-52799            1      0.00%     60.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::54272-54335            1      0.00%     60.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::55296-55359            1      0.00%     60.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::56320-56383            2      0.01%     60.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::59392-59455            1      0.00%     60.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::62464-62527            1      0.00%     60.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64000-64063            1      0.00%     60.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64768-64831            1      0.00%     60.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65024-65087           19      0.05%     60.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65088-65151            6      0.02%     60.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65152-65215            2      0.01%     60.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65280-65343            6      0.02%     60.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65344-65407            6      0.02%     60.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65408-65471           14      0.04%     60.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65472-65535            6      0.02%     60.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65536-65599        14794     38.44%     99.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::71360-71423            1      0.00%     99.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::76928-76991            1      0.00%     99.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::81536-81599            1      0.00%     99.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::85504-85567            1      0.00%     99.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::95680-95743            1      0.00%     99.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::96064-96127            1      0.00%     99.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::98880-98943            1      0.00%     99.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::100672-100735            1      0.00%     99.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::103488-103551            1      0.00%     99.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::106240-106303            1      0.00%     99.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::106624-106687            1      0.00%     99.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::109440-109503            1      0.00%     99.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::110848-110911            1      0.00%     99.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::111232-111295            1      0.00%     99.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::114048-114111            1      0.00%     99.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::117184-117247            1      0.00%     99.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::118272-118335            1      0.00%     99.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::120000-120063            1      0.00%     99.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::121408-121471            1      0.00%     99.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::121792-121855            1      0.00%     99.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::124608-124671            1      0.00%     99.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::125696-125759            1      0.00%     99.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128832-128895            1      0.00%     99.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::130176-130239            1      0.00%     99.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::130368-130431            1      0.00%     99.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::130432-130495            1      0.00%     99.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::130560-130623            1      0.00%     99.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::130624-130687            1      0.00%     99.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::130688-130751            1      0.00%     99.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::130880-130943            1      0.00%     99.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::131072-131135          328      0.85%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::131200-131263            1      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::132096-132159            3      0.01%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::136576-136639            1      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::156992-157055            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::193280-193343            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::196096-196159            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::196608-196671            2      0.01%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::420352-420415            1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          38488                       # Bytes accessed per row activation
-system.physmem.totQLat                   303199099750                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat              396944112250                       # Sum of mem lat for all requests
-system.physmem.totBusLat                  77472355000                       # Total cycles spent in databus access
-system.physmem.totBankLat                 16272657500                       # Total cycles spent in bank access
-system.physmem.avgQLat                       19568.21                       # Average queueing delay per request
-system.physmem.avgBankLat                     1050.22                       # Average bank access latency per request
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
-system.physmem.avgMemAccLat                  25618.44                       # Average memory access latency
-system.physmem.avgRdBW                         379.12                       # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW                          19.87                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                  50.65                       # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW                   2.57                       # Average consumed write bandwidth in MB/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil                           3.12                       # Data bus utilization in percentage
-system.physmem.avgRdQLen                         0.15                       # Average read queue length over time
-system.physmem.avgWrQLen                        10.84                       # Average write queue length over time
-system.physmem.readRowHits                   15469547                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    798405                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   99.84                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  98.33                       # Row buffer hit rate for writes
-system.physmem.avgGap                       160407.65                       # Average gap between requests
-system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     54136540                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16546595                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16546595                       # Transaction distribution
-system.membus.trans_dist::WriteReq             763368                       # Transaction distribution
-system.membus.trans_dist::WriteResp            763368                       # Transaction distribution
-system.membus.trans_dist::Writeback             57971                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4515                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4515                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            132250                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           132250                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2382988                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1893729                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3850                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4280579                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30670848                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total     30670848                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.bridge.slave      2382988                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.physmem.port     32564577                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.gic.pio         3850                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34951427                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390393                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16525240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7700                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     18923357                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    122683392                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total    122683392                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.bridge.slave      2390393                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.physmem.port    139208632                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.gic.pio         7700                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           141606749                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              141606749                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1206151500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy                5000                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy         17903854000                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.7                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy             3613000                       # Layer occupancy (ticks)
-system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy                1000                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4944443675                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        34633310000                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
-system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.iobus.throughput                      47815955                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq             16518752                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            16518752                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                8166                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               8166                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        29936                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7946                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          534                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1042                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2382988                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30670848                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total     30670848                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart.pio        29936                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.realview_io.pio         7946                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer0.pio          534                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer1.pio         1042                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side     30670848                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                33053836                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39180                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15892                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1068                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2084                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2390393                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    122683392                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total    122683392                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart.pio        39180                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.realview_io.pio        15892                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer0.pio         1068                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer1.pio         2084                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side    122683392                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total            125073785                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus               125073785                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy             21043000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              3978000                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               534000                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               527000                       # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy               445000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy         15335424000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2374822000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         42022039000                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     14996132                       # DTB read hits
-system.cpu.dtb.read_misses                       7340                       # DTB read misses
-system.cpu.dtb.write_hits                    11230462                       # DTB write hits
-system.cpu.dtb.write_misses                      2218                       # DTB write misses
-system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3506                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    194                       # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 15003472                       # DTB read accesses
-system.cpu.dtb.write_accesses                11232680                       # DTB write accesses
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          26226594                       # DTB hits
-system.cpu.dtb.misses                            9558                       # DTB misses
-system.cpu.dtb.accesses                      26236152                       # DTB accesses
-system.cpu.itb.inst_hits                     61492700                       # ITB inst hits
-system.cpu.itb.inst_misses                       4471                       # ITB inst misses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2343                       # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 61497171                       # ITB inst accesses
-system.cpu.itb.hits                          61492700                       # DTB hits
-system.cpu.itb.misses                            4471                       # DTB misses
-system.cpu.itb.accesses                      61497171                       # DTB accesses
-system.cpu.numCycles                       5231466570                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    60198861                       # Number of instructions committed
-system.cpu.committedOps                      76605713                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              68872503                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
-system.cpu.num_func_calls                     2140458                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7948408                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     68872503                       # number of integer instructions
-system.cpu.num_fp_insts                         10269                       # number of float instructions
-system.cpu.num_int_register_reads           394778081                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           74182147                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      27394052                       # number of memory refs
-system.cpu.num_load_insts                    15660178                       # Number of load instructions
-system.cpu.num_store_insts                   11733874                       # Number of store instructions
-system.cpu.num_idle_cycles               4581968820.612248                       # Number of idle cycles
-system.cpu.num_busy_cycles               649497749.387752                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.124152                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.875848                       # Percentage of idle cycles
-system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    83018                       # number of quiesce instructions executed
-system.cpu.icache.tags.replacements                 856294                       # number of replacements
-system.cpu.icache.tags.tagsinuse                510.881133                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 60635894                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                 856806                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                  70.769689                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle            19815360250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     510.881133                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.997815                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.997815                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     60635894                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        60635894                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      60635894                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         60635894                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     60635894                       # number of overall hits
-system.cpu.icache.overall_hits::total        60635894                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       856806                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        856806                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       856806                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         856806                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       856806                       # number of overall misses
-system.cpu.icache.overall_misses::total        856806                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  11768628750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  11768628750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  11768628750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  11768628750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  11768628750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  11768628750                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     61492700                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     61492700                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     61492700                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     61492700                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     61492700                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     61492700                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013933                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.013933                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.013933                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.013933                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.013933                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.013933                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.464913                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13735.464913                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.464913                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13735.464913                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.464913                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13735.464913                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       856806                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       856806                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       856806                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       856806                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       856806                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       856806                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  10049829250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  10049829250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  10049829250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  10049829250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10049829250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  10049829250                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    430705250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    430705250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    430705250                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    430705250                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013933                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013933                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013933                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.013933                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013933                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.013933                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11729.410450                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11729.410450                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11729.410450                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11729.410450                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11729.410450                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11729.410450                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                 62586                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse             50732.763816                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                 1683068                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                127970                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                 13.152051                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle          2564920911000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37695.858347                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.884553                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000692                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   6997.437473                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   6035.582751                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.575193                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000059                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.106772                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.092096                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.774121                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         8720                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3535                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       844565                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       370151                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1226971                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       595786                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       595786                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           26                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           26                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       113434                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       113434                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         8720                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         3535                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       844565                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       483585                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1340405                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         8720                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         3535                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       844565                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       483585                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1340405                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            5                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        10600                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data         9837                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        20444                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2872                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2872                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       133893                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133893                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker            5                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        10600                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       143730                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        154337                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker            5                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        10600                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       143730                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       154337                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker       390500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       122500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    745731750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    700197500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1446442250                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       469980                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       469980                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8609650357                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   8609650357                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       390500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       122500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    745731750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   9309847857                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  10056092607                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       390500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       122500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    745731750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   9309847857                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  10056092607                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         8725                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3537                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       855165                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       379988                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1247415                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       595786                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       595786                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2898                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2898                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       247327                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       247327                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         8725                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         3537                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       855165                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       627315                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1494742                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         8725                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker         3537                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       855165                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       627315                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1494742                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000573                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000565                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012395                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.025888                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.016389                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991028                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991028                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541360                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.541360                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000573                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000565                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012395                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.229119                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.103253                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000573                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000565                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012395                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.229119                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.103253                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        78100                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        61250                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70352.051887                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71179.983735                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70751.430738                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   163.642061                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   163.642061                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64302.468068                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64302.468068                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        78100                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        61250                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70352.051887                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64773.170925                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 65156.719432                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        78100                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        61250                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70352.051887                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64773.170925                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 65156.719432                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        57971                       # number of writebacks
-system.cpu.l2cache.writebacks::total            57971                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            5                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        10600                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         9837                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        20444                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2872                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2872                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133893                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       133893                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            5                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        10600                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       143730                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       154337                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            5                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        10600                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       143730                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       154337                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       326500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker        97500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    612276250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    575969500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1188669750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     28722872                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     28722872                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6933953143                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6933953143                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       326500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker        97500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    612276250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7509922643                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   8122622893                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       326500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker        97500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    612276250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7509922643                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   8122622893                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    339357750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166657272750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166996630500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  16702868810                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  16702868810                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    339357750                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183360141560                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183699499310                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000573                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000565                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012395                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.025888                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.016389                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991028                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991028                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541360                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541360                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000573                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000565                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012395                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.229119                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.103253                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000573                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000565                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012395                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.229119                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.103253                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        65300                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        48750                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57761.910377                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58551.336790                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58142.719135                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51787.271500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51787.271500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        65300                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        48750                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57761.910377                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52250.209720                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52629.135548                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        65300                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        48750                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57761.910377                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52250.209720                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52629.135548                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                 626803                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                511.877792                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                 23655579                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                 627315                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  37.709251                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle              657281250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data     511.877792                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.999761                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.999761                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     13195771                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13195771                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      9972807                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        9972807                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       236302                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       236302                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247801                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247801                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      23168578                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         23168578                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     23168578                       # number of overall hits
-system.cpu.dcache.overall_hits::total        23168578                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       368488                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        368488                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       250225                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       250225                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        11500                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        11500                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       618713                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         618713                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       618713                       # number of overall misses
-system.cpu.dcache.overall_misses::total        618713                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   5386574000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   5386574000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10624198015                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10624198015                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    159892750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    159892750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  16010772015                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  16010772015                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  16010772015                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  16010772015                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13564259                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13564259                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10223032                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10223032                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247802                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       247802                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247801                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247801                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     23787291                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     23787291                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     23787291                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     23787291                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.027166                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.027166                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024477                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.024477                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046408                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046408                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.026010                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.026010                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.026010                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.026010                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14618.044550                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14618.044550                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42458.579339                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 42458.579339                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13903.717391                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13903.717391                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 25877.542601                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 25877.542601                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 25877.542601                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 25877.542601                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       595786                       # number of writebacks
-system.cpu.dcache.writebacks::total            595786                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       368488                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       368488                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       250225                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       250225                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11500                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        11500                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       618713                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       618713                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       618713                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       618713                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4644879500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4644879500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10059088985                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10059088985                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    136816250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    136816250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  14703968485                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  14703968485                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  14703968485                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  14703968485                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050953750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050953750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26234980190                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26234980190                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208285933940                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 208285933940                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.027166                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027166                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024477                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024477                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.046408                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.046408                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026010                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.026010                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026010                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.026010                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12605.239519                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12605.239519                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40200.175782                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40200.175782                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11897.065217                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11897.065217                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23765.410594                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23765.410594                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23765.410594                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23765.410594                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                53012095                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2455185                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2455185                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq        763368                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp       763368                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       595786                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2898                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2898                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       247327                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       247327                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side      1725213                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side      5751160                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma        12463                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma        27463                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count                  7516299                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side     54757044                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side     83692777                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma        14148                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma        34900                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size             138498869                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         138498869                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       166632                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     3009752500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1296058500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2542947575                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy       8926500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      18739250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                         0                       # number of replacements
-system.iocache.tags.tagsinuse                            0                       # Cycle average of tags in use
-system.iocache.tags.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                         0                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                           nan                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1466807214000                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1466807214000                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1466807214000                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1466807214000                       # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status	Wed Aug 07 15:24:58 2013 -0500
@@ -1,1 +1,1 @@
-build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing FAILED!
+build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing FAILED!
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,22 +1,21 @@
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
-warn: 	instruction 'mcr bpiallis' unimplemented
-warn: 	instruction 'mcr icialluis' unimplemented
-warn: 	instruction 'mcr dccimvac' unimplemented
-warn: 	instruction 'mcr dccmvau' unimplemented
-warn: 	instruction 'mcr icimvau' unimplemented
-hack: be nice to actually delete the event here
-warn: LCD dual screen mode not supported
-warn: 	instruction 'mcr icialluis' unimplemented
-warn: 	instruction 'mcr bpiallis' unimplemented
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+Traceback (most recent call last):
+  File "<string>", line 1, in <module>
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/src/python/m5/main.py", line 387, in main
+    exec filecode in scope
+  File "tests/run.py", line 180, in <module>
+    execfile(joinpath(tests_root, 'configs', test_filename + '.py'))
+  File "tests/configs/realview-switcheroo-atomic.py", line 43, in <module>
+    cpu_classes=(AtomicSimpleCPU, AtomicSimpleCPU)
+  File "tests/configs/base_config.py", line 230, in create_root
+    system = self.create_system()
+  File "tests/configs/arm_generic.py", line 65, in create_system
+    None, False)
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/FSConfig.py", line 265, in makeArmSystem
+    self.cf0.childImage(mdesc.disk())
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/Benchmarks.py", line 59, in disk
+    return env.get('LINUX_IMAGE', disk('linux-arm-ael.img'))
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 37, in disk
+    system()
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 59, in system
+    raise ImportError, "Can't find a path to system files."
+ImportError: Can't find a path to system files.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,9346 +1,7 @@
-Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:48:26
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-info: Using bootloader at address 0x80000000
-info: Entering event queue @ 0.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1000000000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2000000000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 3000000000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 4000000000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 5000000000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 6000000000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 6000001000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 7000001000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 8000001000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 9000001000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 9000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 10000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 11000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 12000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 13000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 14000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 15000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 16000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 17000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 18000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 19000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 20000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 21000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 22000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 23000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 24000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 25000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 26000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 27000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 28000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 29000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 30000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 31000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 32000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 33000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 34000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 35000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 36000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 37000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 38000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 39000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 40000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 41000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 42000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 43000002500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 44000002500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 44000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 45000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 46000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 47000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 48000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 49000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 50000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 51000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 52000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 53000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 54000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 55000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 56000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 57000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 58000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 59000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 60000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 61000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 62000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 63000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 64000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 65000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 66000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 67000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 68000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 69000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 70000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 71000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 72000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 73000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 74000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 75000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 76000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 77000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 78000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 79000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 80000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 81000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 82000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 83000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 84000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 85000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 86000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 87000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 88000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 89000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 90000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 91000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 92000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 93000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 94000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 95000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 96000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 97000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 98000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 99000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 100000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 101000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 102000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 103000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 104000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 105000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 106000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 107000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 108000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 109000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 110000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 111000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 112000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 113000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 114000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 115000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 116000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 117000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 118000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 119000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 120000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 121000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 122000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 123000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 124000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 125000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 126000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 127000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 128000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 129000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 130000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 131000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 132000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 133000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 134000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 135000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 136000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 137000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 138000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 139000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 140000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 141000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 142000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 143000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 144000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 145000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 146000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 147000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 148000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 149000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 150000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 151000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 152000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 153000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 154000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 155000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 156000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 157000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 158000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 159000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 160000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 161000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 162000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 163000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 164000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 165000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 166000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 167000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 168000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 169000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 170000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 171000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 172000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 173000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 174000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 175000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 176000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 177000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 178000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 179000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 180000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 181000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 182000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 183000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 184000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 185000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 186000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 187000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 188000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 189000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 190000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 191000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 192000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 193000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 194000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 195000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 196000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 197000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 198000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 199000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 200000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 201000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 202000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 203000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 204000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 205000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 206000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 207000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 208000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 209000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 210000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 211000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 212000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 213000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 214000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 215000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 216000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 217000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 218000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 219000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 220000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 221000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 222000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 223000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 224000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 225000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 226000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 227000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 228000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 229000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 230000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 231000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 232000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 233000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 234000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 235000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 236000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 237000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 238000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 239000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 240000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 241000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 242000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 243000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 244000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 245000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 246000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 247000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 248000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 249000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 250000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 251000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 252000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 253000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 254000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 255000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 256000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 257000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 258000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 259000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 260000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 261000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 262000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 263000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 264000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 265000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 266000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 267000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 268000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 269000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 270000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 271000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 272000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 273000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 274000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 275000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 276000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 277000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 278000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 279000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 280000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 281000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 282000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 283000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 284000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 285000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 286000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 287000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 288000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 289000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 290000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 291000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 292000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 293000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 294000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 295000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 296000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 297000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 298000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 299000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 300000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 301000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 302000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 303000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 304000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 305000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 306000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 307000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 308000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 309000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 310000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 311000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 312000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 313000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 314000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 315000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 316000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 317000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 318000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 319000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 320000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 321000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 322000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 323000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 324000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 325000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 326000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 327000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 328000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 329000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 330000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 331000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 332000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 333000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 334000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 335000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 336000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 337000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 338000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 339000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 340000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 341000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 342000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 343000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 344000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 345000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 346000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 347000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 348000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 349000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 350000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 351000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 352000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 353000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 354000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 355000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 356000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 357000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 358000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 359000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 360000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 361000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 362000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 363000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 364000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 365000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 366000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 367000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 368000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 369000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 370000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 371000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 372000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 373000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 374000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 375000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 376000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 377000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 378000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 379000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 380000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 381000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 382000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 383000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 384000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 385000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 386000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 387000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 388000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 389000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 390000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 391000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 392000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 393000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 394000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 395000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 396000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 397000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 398000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 399000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 400000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 401000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 402000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 403000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 404000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 405000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 406000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 407000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 408000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 409000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 410000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 411000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 412000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 413000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 414000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 415000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 416000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 417000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 418000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 419000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 420000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 421000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 422000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 423000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 424000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 425000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 426000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 427000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 428000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 429000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 430000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 431000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 432000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 433000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 434000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 435000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 436000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 437000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 438000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 439000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 440000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 441000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 442000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 443000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 444000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 445000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 446000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 447000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 448000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 449000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 450000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 451000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 452000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 453000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 454000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 455000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 456000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 457000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 458000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 459000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 460000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 461000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 462000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 463000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 464000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 465000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 466000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 467000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 468000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 469000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 470000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 471000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 472000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 473000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 474000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 475000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 476000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 477000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 478000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 479000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 480000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 481000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 482000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 483000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 484000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 485000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 486000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 487000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 488000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 489000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 490000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 491000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 492000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 493000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 494000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 495000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 496000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 497000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 498000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 499000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 500000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 501000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 502000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 503000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 504000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 505000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 506000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 507000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 508000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 509000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 510000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 511000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 512000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 513000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 514000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 515000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 516000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 517000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 518000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 519000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 520000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 521000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 522000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 523000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 524000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 525000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 526000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 527000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 528000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 529000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 530000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 531000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 532000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 533000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 534000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 535000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 536000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 537000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 538000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 539000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 540000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 541000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 542000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 543000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 544000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 545000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 546000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 547000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 548000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 549000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 550000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 551000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 552000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 553000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 554000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 555000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 556000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 557000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 558000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 559000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 560000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 561000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 562000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 563000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 564000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 565000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 566000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 567000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 568000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 569000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 570000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 571000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 572000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 573000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 574000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 575000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 576000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 577000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 578000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 579000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 580000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 581000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 582000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 583000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 584000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 585000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 586000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 587000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 588000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 589000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 590000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 591000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 592000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 593000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 594000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 595000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 596000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 597000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 598000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 599000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 600000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 601000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 602000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 603000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 604000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 605000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 606000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 607000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 608000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 609000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 610000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 611000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 612000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 613000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 614000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 615000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 616000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 617000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 618000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 619000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 620000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 621000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 622000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 623000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 624000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 625000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 626000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 627000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 628000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 629000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 630000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 631000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 632000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 633000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 634000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 635000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 636000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 637000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 638000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 639000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 640000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 641000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 642000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 643000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 644000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 645000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 646000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 647000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 648000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 649000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 650000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 651000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 652000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 653000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 654000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 655000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 656000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 657000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 658000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 659000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 660000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 661000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 662000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 663000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 664000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 665000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 666000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 667000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 668000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 669000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 670000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 671000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 672000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 673000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 674000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 675000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 676000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 677000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 678000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 679000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 680000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 681000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 682000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 683000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 684000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 685000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 686000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 687000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 688000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 689000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 690000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 691000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 692000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 693000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 694000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 695000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 696000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 697000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 698000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 699000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 700000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 701000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 702000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 703000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 704000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 705000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 706000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 707000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 708000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 709000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 710000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 711000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 712000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 713000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 714000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 715000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 716000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 717000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 718000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 719000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 720000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 721000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 722000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 723000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 724000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 725000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 726000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 727000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 728000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 729000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 730000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 731000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 732000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 733000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 734000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 735000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 736000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 737000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 738000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 739000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 740000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 741000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 742000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 743000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 744000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 745000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 746000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 747000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 748000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 749000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 750000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 751000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 752000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 753000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 754000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 755000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 756000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 757000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 758000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 759000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 760000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 761000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 762000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 763000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 764000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 765000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 766000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 767000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 768000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 769000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 770000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 771000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 772000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 773000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 774000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 775000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 776000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 777000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 778000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 779000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 780000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 781000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 782000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 783000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 784000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 785000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 786000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 787000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 788000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 789000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 790000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 791000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 792000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 793000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 794000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 795000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 796000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 797000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 798000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 799000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 800000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 801000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 802000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 803000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 804000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 805000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 806000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 807000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 808000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 809000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 810000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 811000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 812000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 813000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 814000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 815000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 816000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 817000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 818000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 819000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 820000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 821000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 822000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 823000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 824000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 825000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 826000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 827000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 828000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 829000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 830000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 831000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 832000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 833000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 834000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 835000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 836000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 837000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 838000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 839000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 840000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 841000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 842000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 843000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 844000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 845000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 846000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 847000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 848000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 849000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 850000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 851000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 852000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 853000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 854000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 855000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 856000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 857000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 858000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 859000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 860000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 861000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 862000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 863000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 864000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 865000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 866000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 867000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 868000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 869000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 870000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 871000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 872000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 873000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 874000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 875000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 876000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 877000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 878000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 879000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 880000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 881000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 882000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 883000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 884000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 885000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 886000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 887000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 888000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 889000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 890000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 891000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 892000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 893000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 894000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 895000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 896000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 897000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 898000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 899000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 900000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 901000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 902000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 903000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 904000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 905000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 906000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 907000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 908000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 909000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 910000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 911000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 912000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 913000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 914000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 915000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 916000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 917000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 918000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 919000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 920000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 921000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 922000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 923000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 924000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 925000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 926000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 927000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 928000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 929000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 930000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 931000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 932000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 933000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 934000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 935000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 936000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 937000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 938000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 939000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 940000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 941000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 942000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 943000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 944000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 945000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 946000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 947000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 948000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 949000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 950000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 951000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 952000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 953000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 954000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 955000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 956000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 957000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 958000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 959000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 960000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 961000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 962000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 963000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 964000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 965000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 966000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 967000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 968000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 969000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 970000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 971000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 972000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 973000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 974000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 975000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 976000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 977000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 978000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 979000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 980000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 981000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 982000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 983000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 984000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 985000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 986000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 987000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 988000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 989000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 990000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 991000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 992000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 993000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 994000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 995000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 996000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 997000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 998000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 999000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1000000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1001000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1002000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1003000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1004000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1005000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1006000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1007000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1008000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1009000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1010000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1011000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1012000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1013000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1014000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1015000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1016000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1017000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1018000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1019000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1020000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1021000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1022000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1023000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1024000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1025000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1026000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1027000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1028000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1029000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1030000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1031000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1032000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1033000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1034000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1035000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1036000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1037000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1038000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1039000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1040000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1041000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1042000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1043000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1044000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1045000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1046000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1047000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1048000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1049000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1050000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1051000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1052000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1053000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1054000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1055000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1056000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1057000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1058000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1059000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1060000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1061000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1062000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1063000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1064000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1065000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1066000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1067000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1068000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1069000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1070000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1071000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1072000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1073000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1074000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1075000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1076000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1077000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1078000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1079000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1080000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1081000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1082000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1083000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1084000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1085000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1086000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1087000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1088000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1089000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1090000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1091000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1092000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1093000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1094000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1095000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1096000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1097000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1098000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1099000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1100000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1101000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1102000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1103000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1104000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1105000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1106000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1107000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1108000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1109000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1110000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1111000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1112000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1113000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1114000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1115000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1116000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1117000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1118000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1119000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1120000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1121000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1122000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1123000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1124000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1125000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1126000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1127000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1128000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1129000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1130000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1131000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1132000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1133000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1134000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1135000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1136000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1137000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1138000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1139000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1140000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1141000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1142000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1143000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1144000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1145000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1146000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1147000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1148000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1149000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1150000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1151000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1152000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1153000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1154000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1155000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1156000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1157000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1158000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1159000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1160000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1161000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1162000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1163000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1164000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1165000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1166000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1167000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1168000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1169000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1170000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1171000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1172000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1173000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1174000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1175000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1176000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1177000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1178000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1179000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1180000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1181000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1182000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1183000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1184000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1185000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1186000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1187000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1188000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1189000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1190000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1191000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1192000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1193000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1194000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1195000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1196000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1197000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1198000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1199000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1200000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1201000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1202000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1203000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1204000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1205000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1206000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1207000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1208000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1209000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1210000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1211000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1212000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1213000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1214000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1215000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1216000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1217000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1218000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1219000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1220000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1221000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1222000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1223000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1224000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1225000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1226000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1227000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1228000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1229000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1230000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1231000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1232000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1233000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1234000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1235000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1236000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1237000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1238000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1239000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1240000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1241000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1242000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1243000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1244000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1245000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1246000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1247000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1248000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1249000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1250000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1251000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1252000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1253000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1254000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1255000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1256000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1257000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1258000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1259000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1260000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1261000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1262000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1263000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1264000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1265000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1266000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1267000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1268000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1269000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1270000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1271000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1272000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1273000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1274000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1275000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1276000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1277000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1278000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1279000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1280000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1281000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1282000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1283000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1284000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1285000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1286000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1287000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1288000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1289000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1290000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1291000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1292000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1293000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1294000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1295000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1296000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1297000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1298000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1299000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1300000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1301000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1302000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1303000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1304000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1305000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1306000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1307000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1308000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1309000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1310000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1311000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1312000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1313000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1314000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1315000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1316000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1317000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1318000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1319000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1320000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1321000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1322000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1323000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1324000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1325000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1326000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1327000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1328000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1329000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1330000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1331000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1332000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1333000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1334000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1335000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1336000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1337000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1338000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1339000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1340000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1341000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1342000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1343000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1344000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1345000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1346000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1347000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1348000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1349000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1350000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1351000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1352000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1353000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1354000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1355000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1356000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1357000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1358000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1359000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1360000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1361000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1362000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1363000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1364000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1365000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1366000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1367000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1368000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1369000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1370000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1371000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1372000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1373000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1374000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1375000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1376000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1377000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1378000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1379000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1380000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1381000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1382000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1383000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1384000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1385000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1386000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1387000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1388000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1389000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1390000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1391000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1392000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1393000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1394000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1395000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1396000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1397000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1398000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1399000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1400000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1401000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1402000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1403000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1404000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1405000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1406000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1407000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1408000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1409000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1410000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1411000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1412000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1413000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1414000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1415000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1416000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1417000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1418000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1419000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1420000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1421000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1422000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1423000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1424000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1425000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1426000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1427000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1428000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1429000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1430000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1431000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1432000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1433000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1434000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1435000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1436000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1437000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1438000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1439000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1440000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1441000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1442000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1443000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1444000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1445000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1446000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1447000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1448000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1449000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1450000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1451000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1452000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1453000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1454000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1455000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1456000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1457000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1458000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1459000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1460000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1461000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1462000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1463000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1464000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1465000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1466000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1467000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1468000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1469000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1470000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1471000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1472000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1473000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1474000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1475000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1476000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1477000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1478000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1479000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1480000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1481000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1482000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1483000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1484000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1485000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1486000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1487000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1488000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1489000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1490000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1491000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1492000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1493000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1494000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1495000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1496000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1497000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1498000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1499000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1500000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1501000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1502000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1503000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1504000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1505000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1506000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1507000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1508000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1509000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1510000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1511000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1512000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1513000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1514000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1515000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1516000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1517000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1518000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1519000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1520000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1521000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1522000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1523000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1524000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1525000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1526000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1527000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1528000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1529000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1530000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1531000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1532000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1533000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1534000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1535000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1536000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1537000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1538000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1539000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1540000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1541000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1542000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1543000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1544000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1545000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1546000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1547000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1548000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1549000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1550000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1551000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1552000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1553000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1554000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1555000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1556000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1557000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1558000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1559000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1560000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1561000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1562000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1563000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1564000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1565000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1566000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1567000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1568000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1569000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1570000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1571000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1572000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1573000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1574000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1575000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1576000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1577000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1578000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1579000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1580000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1581000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1582000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1583000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1584000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1585000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1586000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1587000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1588000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1589000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1590000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1591000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1592000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1593000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1594000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1595000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1596000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1597000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1598000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1599000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1600000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1601000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1602000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1603000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1604000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1605000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1606000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1607000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1608000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1609000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1610000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1611000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1612000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1613000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1614000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1615000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1616000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1617000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1618000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1619000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1620000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1621000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1622000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1623000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1624000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1625000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1626000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1627000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1628000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1629000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1630000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1631000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1632000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1633000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1634000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1635000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1636000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1637000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1638000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1639000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1640000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1641000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1642000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1643000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1644000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1645000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1646000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1647000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1648000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1649000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1650000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1651000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1652000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1653000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1654000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1655000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1656000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1657000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1658000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1659000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1660000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1661000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1662000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1663000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1664000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1665000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1666000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1667000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1668000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1669000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1670000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1671000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1672000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1673000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1674000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1675000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1676000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1677000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1678000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1679000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1680000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1681000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1682000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1683000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1684000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1685000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1686000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1687000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1688000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1689000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1690000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1691000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1692000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1693000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1694000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1695000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1696000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1697000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1698000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1699000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1700000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1701000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1702000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1703000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1704000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1705000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1706000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1707000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1708000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1709000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1710000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1711000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1712000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1713000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1714000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1715000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1716000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1717000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1718000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1719000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1720000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1721000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1722000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1723000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1724000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1725000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1726000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1727000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1728000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1729000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1730000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1731000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1732000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1733000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1734000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1735000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1736000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1737000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1738000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1739000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1740000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1741000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1742000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1743000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1744000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1745000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1746000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1747000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1748000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1749000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1750000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1751000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1752000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1753000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1754000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1755000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1756000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1757000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1758000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1759000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1760000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1761000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1762000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1763000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1764000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1765000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1766000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1767000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1768000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1769000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1770000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1771000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1772000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1773000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1774000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1775000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1776000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1777000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1778000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1779000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1780000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1781000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1782000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1783000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1784000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1785000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1786000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1787000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1788000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1789000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1790000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1791000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1792000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1793000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1794000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1795000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1796000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1797000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1798000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1799000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1800000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1801000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1802000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1803000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1804000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1805000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1806000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1807000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1808000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1809000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1810000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1811000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1812000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1813000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1814000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1815000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1816000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1817000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1818000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1819000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1820000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1821000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1822000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1823000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1824000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1825000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1826000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1827000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1828000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1829000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1830000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1831000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1832000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1833000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1834000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1835000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1836000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1837000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1838000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1839000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1840000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1841000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1842000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1843000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1844000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1845000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1846000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1847000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1848000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1849000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1850000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1851000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1852000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1853000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1854000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1855000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1856000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1857000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1858000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1859000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1860000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1861000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1862000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1863000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1864000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1865000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1866000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1867000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1868000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1869000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1870000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1871000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1872000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1873000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1874000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1875000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1876000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1877000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1878000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1879000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1880000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1881000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1882000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1883000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1884000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1885000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1886000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1887000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1888000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1889000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1890000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1891000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1892000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1893000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1894000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1895000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1896000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1897000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1898000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1899000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1900000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1901000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1902000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1903000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1904000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1905000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1906000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1907000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1908000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1909000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1910000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1911000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1912000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1913000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1914000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1915000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1916000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1917000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1918000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1919000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1920000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1921000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1922000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1923000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1924000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1925000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1926000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1927000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1928000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1929000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1930000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1931000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1932000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1933000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1934000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1935000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1936000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1937000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1938000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1939000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1940000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1941000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1942000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1943000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1944000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1945000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1946000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1947000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1948000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1949000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1950000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1951000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1952000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1953000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1954000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1955000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1956000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1957000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1958000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1959000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1960000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1961000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1962000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1963000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1964000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1965000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1966000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1967000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1968000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1969000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1970000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1971000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1972000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1973000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1974000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1975000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1976000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1977000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1978000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1979000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1980000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1981000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1982000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1983000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1984000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1985000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1986000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1987000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1988000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1989000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1990000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1991000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1992000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1993000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1994000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1995000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1996000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1997000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1998000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1999000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2000000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2001000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2002000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2003000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2004000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2005000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2006000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2007000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2008000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2009000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2010000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2011000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2012000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2013000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2014000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2015000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2016000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2017000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2018000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2019000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2020000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2021000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2022000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2023000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2024000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2025000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2026000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2027000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2028000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2029000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2030000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2031000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2032000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2033000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2034000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2035000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2036000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2037000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2038000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2039000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2040000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2041000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2042000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2043000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2044000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2045000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2046000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2047000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2048000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2049000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2050000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2051000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2052000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2053000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2054000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2055000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2056000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2057000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2058000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2059000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2060000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2061000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2062000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2063000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2064000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2065000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2066000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2067000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2068000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2069000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2070000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2071000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2072000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2073000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2074000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2075000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2076000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2077000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2078000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2079000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2080000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2081000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2082000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2083000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2084000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2085000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2086000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2087000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2088000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2089000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2090000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2091000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2092000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2093000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2094000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2095000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2096000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2097000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2098000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2099000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2100000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2101000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2102000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2103000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2104000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2105000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2106000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2107000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2108000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2109000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2110000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2111000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2112000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2113000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2114000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2115000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2116000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2117000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2118000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2119000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2120000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2121000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2122000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2123000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2124000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2125000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2126000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2127000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2128000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2129000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2130000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2131000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2132000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2133000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2134000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2135000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2136000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2137000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2138000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2139000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2140000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2141000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2142000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2143000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2144000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2145000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2146000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2147000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2148000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2149000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2150000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2151000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2152000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2153000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2154000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2155000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2156000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2157000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2158000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2159000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2160000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2161000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2162000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2163000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2164000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2165000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2166000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2167000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2168000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2169000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2170000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2171000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2172000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2173000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2174000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2175000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2176000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2177000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2178000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2179000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2180000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2181000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2182000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2183000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2184000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2185000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2186000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2187000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2188000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2189000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2190000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2191000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2192000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2193000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2194000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2195000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2196000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2197000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2198000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2199000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2200000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2201000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2202000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2203000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2204000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2205000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2206000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2207000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2208000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2209000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2210000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2211000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2212000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2213000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2214000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2215000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2216000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2217000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2218000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2219000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2220000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2221000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2222000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2223000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2224000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2225000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2226000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2227000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2228000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2229000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2230000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2231000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2232000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2233000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2234000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2235000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2236000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2237000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2238000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2239000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2240000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2241000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2242000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2243000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2244000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2245000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2246000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2247000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2248000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2249000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2250000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2251000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2252000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2253000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2254000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2255000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2256000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2257000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2258000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2259000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2260000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2261000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2262000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2263000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2264000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2265000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2266000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2267000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2268000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2269000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2270000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2271000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2272000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2273000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2274000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2275000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2276000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2277000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2278000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2279000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2280000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2281000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2282000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2283000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2284000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2285000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2286000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2287000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2288000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2289000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2290000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2291000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2292000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2293000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2294000004000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2295000004000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2295000006000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2296000006000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2297000006000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2298000006000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2299000006000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2300000006000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2301000006000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2302000006000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2303000006000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2304000006000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2305000006000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2306000006000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2307000006000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2308000006000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2309000006000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2310000006000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2311000006000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2312000006000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2313000006000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2313000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2314000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2315000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2316000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2317000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2318000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2319000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2320000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2321000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2322000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2323000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2324000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2325000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2326000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2327000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2328000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2329000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2330000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2331000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2332000010500.  Starting simulation...
+gem5 compiled Jul 17 2013 12:12:01
+gem5 started Jul 17 2013 12:12:10
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,685 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  2.332810                       # Number of seconds simulated
-sim_ticks                                2332810264000                       # Number of ticks simulated
-final_tick                               2332810264000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 662335                       # Simulator instruction rate (inst/s)
-host_op_rate                                   851722                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            25577480180                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 396424                       # Number of bytes of host memory used
-host_seconds                                    91.21                       # Real time elapsed on the host
-sim_insts                                    60408639                       # Number of instructions simulated
-sim_ops                                      77681819                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd    111673344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           492704                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          6494800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           212416                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2577132                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            121450716                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       492704                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       212416                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          705120                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3703040                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data       1405784                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data       1610060                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6718884                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      13959168                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             13901                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            101515                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              3319                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             40278                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              14118186                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57860                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           351446                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           402515                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811821                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47870736                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker            55                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker            82                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              211206                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             2784110                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               91056                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1104733                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                52061978                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         211206                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          91056                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             302262                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1587373                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data             602614                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data             690180                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2880167                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1587373                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47870736                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker           55                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker           82                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             211206                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            3386724                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              91056                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1794913                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54942145                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                             0                       # Total number of read requests seen
-system.physmem.writeReqs                            0                       # Total number of write requests seen
-system.physmem.cpureqs                              0                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                            0                       # Total number of bytes read from memory
-system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd                      0                       # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15                    0                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
-system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                               0                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                       0                       # Categorize read packet sizes
-system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::6                      0                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::mean             nan                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean            nan                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev            nan                       # Bytes accessed per row activation
-system.physmem.totQLat                              0                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat                         0                       # Sum of mem lat for all requests
-system.physmem.totBusLat                            0                       # Total cycles spent in databus access
-system.physmem.totBankLat                           0                       # Total cycles spent in bank access
-system.physmem.avgQLat                            nan                       # Average queueing delay per request
-system.physmem.avgBankLat                         nan                       # Average bank access latency per request
-system.physmem.avgBusLat                          nan                       # Average bus latency per request
-system.physmem.avgMemAccLat                       nan                       # Average memory access latency
-system.physmem.avgRdBW                           0.00                       # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                   0.00                       # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil                           0.00                       # Data bus utilization in percentage
-system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
-system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
-system.physmem.readRowHits                          0                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                     nan                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                             nan                       # Average gap between requests
-system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst            9                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                9                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst            9                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            9                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst            9                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               9                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     55969561                       # Throughput (bytes/s)
-system.membus.data_through_bus              130566366                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.l2c.tags.replacements                         62242                       # number of replacements
-system.l2c.tags.tagsinuse                     50006.300222                       # Cycle average of tags in use
-system.l2c.tags.total_refs                         1678485                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                        127627                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                         13.151488                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                  2316901489000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks        36900.571453                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker       0.993823                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker       0.993931                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst          4917.298419                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data          3152.525311                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst          2097.421525                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data          2936.495759                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks           0.563058                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker      0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker      0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst            0.075032                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data            0.048104                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst            0.032004                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data            0.044807                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total                0.763036                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker         9005                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         3277                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             473134                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             196972                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         4875                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         2050                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             365737                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             169792                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1224842                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          592682                       # number of Writeback hits
-system.l2c.Writeback_hits::total               592682                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data              12                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              14                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            63335                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            50403                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               113738                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          9005                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          3277                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              473134                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              260307                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          4875                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          2050                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              365737                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              220195                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1338580                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         9005                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         3277                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             473134                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             260307                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         4875                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         2050                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             365737                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             220195                       # number of overall hits
-system.l2c.overall_hits::total                1338580                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker            3                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             7285                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             5807                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             3319                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             4065                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                20481                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          1520                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1399                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2919                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          96488                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          36984                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             133472                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker            3                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              7285                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            102295                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              3319                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             41049                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                153953                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker            3                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             7285                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           102295                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             3319                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            41049                       # number of overall misses
-system.l2c.overall_misses::total               153953                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         9007                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         3280                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         480419                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         202779                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         4875                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         2050                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         369056                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         173857                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1245323                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       592682                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           592682                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         1532                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         1413                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2945                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       159823                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        87387                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           247210                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         9007                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         3280                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          480419                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          362602                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         4875                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         2050                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          369056                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          261244                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1492533                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         9007                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         3280                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         480419                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         362602                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         4875                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         2050                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         369056                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         261244                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1492533                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000915                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.015164                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.028637                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.008993                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.023381                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.016446                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.992167                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.990092                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.991171                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.603718                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.423221                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.539913                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000222                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000915                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.015164                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.282114                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.008993                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.157129                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.103149                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000222                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000915                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.015164                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.282114                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.008993                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.157129                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.103149                       # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               57860                       # number of writebacks
-system.l2c.writebacks::total                    57860                       # number of writebacks
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                    59119250                       # Throughput (bytes/s)
-system.toL2Bus.data_through_bus             137913994                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus               0                       # Total snoop data (bytes)
-system.iobus.throughput                      48895252                       # Throughput (bytes/s)
-system.iobus.data_through_bus               114063346                       # Total data (bytes)
-system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     7929205                       # DTB read hits
-system.cpu0.dtb.read_misses                      6441                       # DTB read misses
-system.cpu0.dtb.write_hits                    6437098                       # DTB write hits
-system.cpu0.dtb.write_misses                     1932                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        1168                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid                752                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    5576                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   136                       # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      240                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 7935646                       # DTB read accesses
-system.cpu0.dtb.write_accesses                6439030                       # DTB write accesses
-system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         14366303                       # DTB hits
-system.cpu0.dtb.misses                           8373                       # DTB misses
-system.cpu0.dtb.accesses                     14374676                       # DTB accesses
-system.cpu0.itb.inst_hits                    32543253                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3703                       # ITB inst misses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        1168                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid                752                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2636                       # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                32546956                       # ITB inst accesses
-system.cpu0.itb.hits                         32543253                       # DTB hits
-system.cpu0.itb.misses                           3703                       # DTB misses
-system.cpu0.itb.accesses                     32546956                       # DTB accesses
-system.cpu0.numCycles                      4633589665                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   31998091                       # Number of instructions committed
-system.cpu0.committedOps                     41901593                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             37065495                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  5364                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1207173                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4285544                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    37065495                       # number of integer instructions
-system.cpu0.num_fp_insts                         5364                       # number of float instructions
-system.cpu0.num_int_register_reads          188704279                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          39536975                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3938                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes               1428                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     15013057                       # number of memory refs
-system.cpu0.num_load_insts                    8304661                       # Number of load instructions
-system.cpu0.num_store_insts                   6708396                       # Number of store instructions
-system.cpu0.num_idle_cycles              186586201.060505                       # Number of idle cycles
-system.cpu0.num_busy_cycles              4447003463.939495                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.959732                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.040268                       # Percentage of idle cycles
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   82795                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements                850590                       # number of replacements
-system.cpu0.icache.tags.tagsinuse               511.678593                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs                60583498                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs                851102                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs                 71.182418                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle            5709383000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   444.510252                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    67.168341                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.868184                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.131188                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total        0.999372                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst     32064735                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     28518763                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       60583498                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     32064735                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     28518763                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        60583498                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     32064735                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     28518763                       # number of overall hits
-system.cpu0.icache.overall_hits::total       60583498                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       481297                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       369805                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       851102                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       481297                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       369805                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        851102                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       481297                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       369805                       # number of overall misses
-system.cpu0.icache.overall_misses::total       851102                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     32546032                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     28888568                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     61434600                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     32546032                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     28888568                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     61434600                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     32546032                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     28888568                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     61434600                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014788                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.012801                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.013854                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014788                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.012801                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.013854                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014788                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.012801                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.013854                       # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements                623334                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse               511.997031                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs                23628284                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs                623846                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs                 37.875187                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle              21763000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   451.298938                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    60.698093                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.881443                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.118551                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total        0.999994                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6995590                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      6184430                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       13180020                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      5776861                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      4185204                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       9962065                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       139289                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        96747                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       236036                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       145935                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       101283                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       247218                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     12772451                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     10369634                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        23142085                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     12772451                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     10369634                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       23142085                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       196132                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       169321                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       365453                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       161355                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        88800                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       250155                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6647                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         4536                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        11183                       # number of LoadLockedReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       357487                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       258121                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        615608                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       357487                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       258121                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       615608                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7191722                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      6353751                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     13545473                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5938216                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      4274004                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     10212220                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       145936                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       101283                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       247219                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       145935                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       101283                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       247218                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     13129938                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     10627755                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     23757693                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     13129938                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     10627755                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     23757693                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.027272                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.026649                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.026980                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027172                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.020777                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.024496                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.045547                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.044785                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.045235                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027227                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024287                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.025912                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027227                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.024287                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.025912                       # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       592682                       # number of writebacks
-system.cpu0.dcache.writebacks::total           592682                       # number of writebacks
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     7038595                       # DTB read hits
-system.cpu1.dtb.read_misses                      4223                       # DTB read misses
-system.cpu1.dtb.write_hits                    4778906                       # DTB write hits
-system.cpu1.dtb.write_misses                     1249                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        1166                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid                687                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2949                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                    82                       # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      212                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 7042818                       # DTB read accesses
-system.cpu1.dtb.write_accesses                4780155                       # DTB write accesses
-system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         11817501                       # DTB hits
-system.cpu1.dtb.misses                           5472                       # DTB misses
-system.cpu1.dtb.accesses                     11822973                       # DTB accesses
-system.cpu1.itb.inst_hits                    28886892                       # ITB inst hits
-system.cpu1.itb.inst_misses                      2463                       # ITB inst misses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        1166                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid                687                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1597                       # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                28889355                       # ITB inst accesses
-system.cpu1.itb.hits                         28886892                       # DTB hits
-system.cpu1.itb.misses                           2463                       # DTB misses
-system.cpu1.itb.accesses                     28889355                       # DTB accesses
-system.cpu1.numCycles                      4279954879                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   28410548                       # Number of instructions committed
-system.cpu1.committedOps                     35780226                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             31730110                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  4905                       # Number of float alu accesses
-system.cpu1.num_func_calls                     928835                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      3656569                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    31730110                       # number of integer instructions
-system.cpu1.num_fp_insts                         4905                       # number of float instructions
-system.cpu1.num_int_register_reads          160619995                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          34566633                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                3555                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               1352                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     12348580                       # number of memory refs
-system.cpu1.num_load_insts                    7334866                       # Number of load instructions
-system.cpu1.num_store_insts                   5013714                       # Number of store instructions
-system.cpu1.num_idle_cycles              8315278901.051629                       # Number of idle cycles
-system.cpu1.num_busy_cycles              -4035324022.051629                       # Number of busy cycles
-system.cpu1.not_idle_fraction               -0.942843                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    1.942843                       # Percentage of idle cycles
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.iocache.tags.replacements                         0                       # number of replacements
-system.iocache.tags.tagsinuse                            0                       # Cycle average of tags in use
-system.iocache.tags.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                         0                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                           nan                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,8 +1,17 @@
-warn: Sockets disabled, not accepting terminal connections
-warn: CoherentBus testsys.membus has no snooping ports attached!
-warn: Sockets disabled, not accepting gdb connections
-warn: CoherentBus drivesys.membus has no snooping ports attached!
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: Obsolete M5 ivlb instruction encountered.
-hack: be nice to actually delete the event here
+Traceback (most recent call last):
+  File "<string>", line 1, in <module>
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/src/python/m5/main.py", line 387, in main
+    exec filecode in scope
+  File "tests/run.py", line 180, in <module>
+    execfile(joinpath(tests_root, 'configs', test_filename + '.py'))
+  File "tests/configs/twosys-tsunami-simple-atomic.py", line 36, in <module>
+    SysConfig('netperf-stream-client.rcS'))
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/FSConfig.py", line 69, in makeLinuxAlphaSystem
+    self.readfile = mdesc.script()
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/Benchmarks.py", line 41, in script
+    return script(self.scriptname)
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 45, in script
+    system()
+  File "/panfs/panasas-01.cs.wisc.edu/scratch/lena/slicc_sucks/configs/common/SysPaths.py", line 59, in system
+    raise ImportError, "Can't find a path to system files."
+ImportError: Can't find a path to system files.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,16 +1,7 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:07:46
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
-      0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
-      0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 4321612280500 because checkpoint
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,794 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.200409                       # Number of seconds simulated
-sim_ticks                                200409284500                       # Number of ticks simulated
-final_tick                               4321214250500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                               10833540                       # Simulator instruction rate (inst/s)
-host_op_rate                                 10833535                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4145057481                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 475668                       # Number of bytes of host memory used
-host_seconds                                    48.35                       # Real time elapsed on the host
-sim_insts                                   523790075                       # Number of instructions simulated
-sim_ops                                     523790075                       # Number of ops (including micro ops) simulated
-testsys.physmem.bytes_read::cpu.inst         81046720                       # Number of bytes read from this memory
-testsys.physmem.bytes_read::cpu.data         27826276                       # Number of bytes read from this memory
-testsys.physmem.bytes_read::tsunami.ethernet     57260496                       # Number of bytes read from this memory
-testsys.physmem.bytes_read::total           166133492                       # Number of bytes read from this memory
-testsys.physmem.bytes_inst_read::cpu.inst     81046720                       # Number of instructions bytes read from this memory
-testsys.physmem.bytes_inst_read::total       81046720                       # Number of instructions bytes read from this memory
-testsys.physmem.bytes_written::cpu.data      16606680                       # Number of bytes written to this memory
-testsys.physmem.bytes_written::tsunami.ethernet          902                       # Number of bytes written to this memory
-testsys.physmem.bytes_written::total         16607582                       # Number of bytes written to this memory
-testsys.physmem.num_reads::cpu.inst          20261680                       # Number of read requests responded to by this memory
-testsys.physmem.num_reads::cpu.data           3842559                       # Number of read requests responded to by this memory
-testsys.physmem.num_reads::tsunami.ethernet      2385836                       # Number of read requests responded to by this memory
-testsys.physmem.num_reads::total             26490075                       # Number of read requests responded to by this memory
-testsys.physmem.num_writes::cpu.data          2258392                       # Number of write requests responded to by this memory
-testsys.physmem.num_writes::tsunami.ethernet           31                       # Number of write requests responded to by this memory
-testsys.physmem.num_writes::total             2258423                       # Number of write requests responded to by this memory
-testsys.physmem.bw_read::cpu.inst           404406014                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::cpu.data           138847240                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::tsunami.ethernet    285717781                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::total              828971035                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::cpu.inst      404406014                       # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::total         404406014                       # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::cpu.data           82863826                       # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::tsunami.ethernet         4501                       # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::total              82868326                       # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.inst          404406014                       # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.data          221711065                       # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::tsunami.ethernet    285722281                       # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::total             911839361                       # Total bandwidth to/from this memory (bytes/s)
-testsys.membus.throughput                   916540501                       # Throughput (bytes/s)
-testsys.membus.data_through_bus             183683226                       # Total data (bytes)
-testsys.membus.snoop_data_through_bus               0                       # Total snoop data (bytes)
-testsys.disk0.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
-testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk0.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
-testsys.disk0.dma_write_full_pages                  0                       # Number of full page size DMA writes.
-testsys.disk0.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
-testsys.disk0.dma_write_txs                         0                       # Number of DMA write transactions.
-testsys.disk2.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
-testsys.disk2.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk2.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
-testsys.disk2.dma_write_full_pages                  0                       # Number of full page size DMA writes.
-testsys.disk2.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
-testsys.disk2.dma_write_txs                         0                       # Number of DMA write transactions.
-testsys.cpu.dtb.fetch_hits                          0                       # ITB hits
-testsys.cpu.dtb.fetch_misses                        0                       # ITB misses
-testsys.cpu.dtb.fetch_acv                           0                       # ITB acv
-testsys.cpu.dtb.fetch_accesses                      0                       # ITB accesses
-testsys.cpu.dtb.read_hits                     3916918                       # DTB read hits
-testsys.cpu.dtb.read_misses                      3287                       # DTB read misses
-testsys.cpu.dtb.read_acv                           80                       # DTB read access violations
-testsys.cpu.dtb.read_accesses                  225414                       # DTB read accesses
-testsys.cpu.dtb.write_hits                    2316885                       # DTB write hits
-testsys.cpu.dtb.write_misses                      528                       # DTB write misses
-testsys.cpu.dtb.write_acv                          81                       # DTB write access violations
-testsys.cpu.dtb.write_accesses                 109988                       # DTB write accesses
-testsys.cpu.dtb.data_hits                     6233803                       # DTB hits
-testsys.cpu.dtb.data_misses                      3815                       # DTB misses
-testsys.cpu.dtb.data_acv                          161                       # DTB access violations
-testsys.cpu.dtb.data_accesses                  335402                       # DTB accesses
-testsys.cpu.itb.fetch_hits                    4052211                       # ITB hits
-testsys.cpu.itb.fetch_misses                     1497                       # ITB misses
-testsys.cpu.itb.fetch_acv                          69                       # ITB acv
-testsys.cpu.itb.fetch_accesses                4053708                       # ITB accesses
-testsys.cpu.itb.read_hits                           0                       # DTB read hits
-testsys.cpu.itb.read_misses                         0                       # DTB read misses
-testsys.cpu.itb.read_acv                            0                       # DTB read access violations
-testsys.cpu.itb.read_accesses                       0                       # DTB read accesses
-testsys.cpu.itb.write_hits                          0                       # DTB write hits
-testsys.cpu.itb.write_misses                        0                       # DTB write misses
-testsys.cpu.itb.write_acv                           0                       # DTB write access violations
-testsys.cpu.itb.write_accesses                      0                       # DTB write accesses
-testsys.cpu.itb.data_hits                           0                       # DTB hits
-testsys.cpu.itb.data_misses                         0                       # DTB misses
-testsys.cpu.itb.data_acv                            0                       # DTB access violations
-testsys.cpu.itb.data_accesses                       0                       # DTB accesses
-testsys.cpu.numCycles                       400804755                       # number of cpu cycles simulated
-testsys.cpu.numWorkItemsStarted                     0                       # number of work items this cpu started
-testsys.cpu.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-testsys.cpu.committedInsts                   20257704                       # Number of instructions committed
-testsys.cpu.committedOps                     20257704                       # Number of ops (including micro ops) committed
-testsys.cpu.num_int_alu_accesses             18837017                       # Number of integer alu accesses
-testsys.cpu.num_fp_alu_accesses                 17380                       # Number of float alu accesses
-testsys.cpu.num_func_calls                    1221180                       # number of times a function call or return occured
-testsys.cpu.num_conditional_control_insts      1442148                       # number of instructions that are conditional controls
-testsys.cpu.num_int_insts                    18837017                       # number of integer instructions
-testsys.cpu.num_fp_insts                        17380                       # number of float instructions
-testsys.cpu.num_int_register_reads           24787248                       # number of times the integer registers were read
-testsys.cpu.num_int_register_writes          14693875                       # number of times the integer registers were written
-testsys.cpu.num_fp_register_reads               11166                       # number of times the floating registers were read
-testsys.cpu.num_fp_register_writes              10823                       # number of times the floating registers were written
-testsys.cpu.num_mem_refs                      6263046                       # number of memory refs
-testsys.cpu.num_load_insts                    3944033                       # Number of load instructions
-testsys.cpu.num_store_insts                   2319013                       # Number of store instructions
-testsys.cpu.num_idle_cycles              380542207.362158                       # Number of idle cycles
-testsys.cpu.num_busy_cycles              20262547.637842                       # Number of busy cycles
-testsys.cpu.not_idle_fraction                0.050555                       # Percentage of non-idle cycles
-testsys.cpu.idle_fraction                    0.949445                       # Percentage of idle cycles
-testsys.cpu.kern.inst.arm                           0                       # number of arm instructions executed
-testsys.cpu.kern.inst.quiesce                   19580                       # number of quiesce instructions executed
-testsys.cpu.kern.inst.hwrei                    153667                       # number of hwrei instructions executed
-testsys.cpu.kern.ipl_count::0                   62779     42.67%     42.67% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::21                  19625     13.34%     56.01% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::22                    205      0.14%     56.15% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::31                  64509     43.85%    100.00% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::total              147118                       # number of times we switched to this ipl
-testsys.cpu.kern.ipl_good::0                    62773     43.18%     43.18% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::21                   19625     13.50%     56.67% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::22                     205      0.14%     56.82% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::31                   62785     43.18%    100.00% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::total               145388                       # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks::0            194346512500     96.98%     96.98% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::21             1588986000      0.79%     97.77% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::22                8815000      0.00%     97.78% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::31             4458282500      2.22%    100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::total        200402596000                       # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_used::0                 0.999904                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::31                0.973275                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::total             0.988241                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.syscall::2                         3      3.61%      3.61% # number of syscalls executed
-testsys.cpu.kern.syscall::3                         7      8.43%     12.05% # number of syscalls executed
-testsys.cpu.kern.syscall::4                         1      1.20%     13.25% # number of syscalls executed
-testsys.cpu.kern.syscall::6                         7      8.43%     21.69% # number of syscalls executed
-testsys.cpu.kern.syscall::17                        7      8.43%     30.12% # number of syscalls executed
-testsys.cpu.kern.syscall::19                        2      2.41%     32.53% # number of syscalls executed
-testsys.cpu.kern.syscall::20                        1      1.20%     33.73% # number of syscalls executed
-testsys.cpu.kern.syscall::33                        3      3.61%     37.35% # number of syscalls executed
-testsys.cpu.kern.syscall::45                       10     12.05%     49.40% # number of syscalls executed
-testsys.cpu.kern.syscall::48                        5      6.02%     55.42% # number of syscalls executed
-testsys.cpu.kern.syscall::54                        1      1.20%     56.63% # number of syscalls executed
-testsys.cpu.kern.syscall::59                        3      3.61%     60.24% # number of syscalls executed
-testsys.cpu.kern.syscall::71                       15     18.07%     78.31% # number of syscalls executed
-testsys.cpu.kern.syscall::74                        4      4.82%     83.13% # number of syscalls executed
-testsys.cpu.kern.syscall::97                        2      2.41%     85.54% # number of syscalls executed
-testsys.cpu.kern.syscall::98                        2      2.41%     87.95% # number of syscalls executed
-testsys.cpu.kern.syscall::101                       2      2.41%     90.36% # number of syscalls executed
-testsys.cpu.kern.syscall::102                       2      2.41%     92.77% # number of syscalls executed
-testsys.cpu.kern.syscall::104                       1      1.20%     93.98% # number of syscalls executed
-testsys.cpu.kern.syscall::105                       3      3.61%     97.59% # number of syscalls executed
-testsys.cpu.kern.syscall::118                       2      2.41%    100.00% # number of syscalls executed
-testsys.cpu.kern.syscall::total                    83                       # number of syscalls executed
-testsys.cpu.kern.callpal::swpctx                  438      0.34%      0.34% # number of callpals executed
-testsys.cpu.kern.callpal::tbi                      20      0.02%      0.36% # number of callpals executed
-testsys.cpu.kern.callpal::swpipl               106830     83.26%     83.62% # number of callpals executed
-testsys.cpu.kern.callpal::rdps                    359      0.28%     83.90% # number of callpals executed
-testsys.cpu.kern.callpal::wrusp                     3      0.00%     83.90% # number of callpals executed
-testsys.cpu.kern.callpal::rdusp                     3      0.00%     83.90% # number of callpals executed
-testsys.cpu.kern.callpal::rti                   20470     15.95%     99.86% # number of callpals executed
-testsys.cpu.kern.callpal::callsys                 140      0.11%     99.97% # number of callpals executed
-testsys.cpu.kern.callpal::imb                      44      0.03%    100.00% # number of callpals executed
-testsys.cpu.kern.callpal::total                128307                       # number of callpals executed
-testsys.cpu.kern.mode_switch::kernel             1280                       # number of protection mode switches
-testsys.cpu.kern.mode_switch::user                702                       # number of protection mode switches
-testsys.cpu.kern.mode_switch::idle              19629                       # number of protection mode switches
-testsys.cpu.kern.mode_good::kernel                707                      
-testsys.cpu.kern.mode_good::user                  702                      
-testsys.cpu.kern.mode_good::idle                    5                      
-testsys.cpu.kern.mode_switch_good::kernel     0.552344                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::idle      0.000255                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::total     0.065430                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_ticks::kernel         994603000     60.01%     60.01% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::user           533068000     32.16%     92.17% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::idle           129740500      7.83%    100.00% # number of ticks spent at the given mode
-testsys.cpu.kern.swap_context                     438                       # number of times the context was actually changed
-testsys.tsunami.ethernet.txBytes                  960                       # Bytes Transmitted
-testsys.tsunami.ethernet.rxBytes                  798                       # Bytes Received
-testsys.tsunami.ethernet.txPackets                  8                       # Number of Packets Transmitted
-testsys.tsunami.ethernet.rxPackets                  5                       # Number of Packets Received
-testsys.tsunami.ethernet.txIpChecksums              2                       # Number of tx IP Checksums done by device
-testsys.tsunami.ethernet.rxIpChecksums              5                       # Number of rx IP Checksums done by device
-testsys.tsunami.ethernet.txTcpChecksums             2                       # Number of tx TCP Checksums done by device
-testsys.tsunami.ethernet.rxTcpChecksums             5                       # Number of rx TCP Checksums done by device
-testsys.tsunami.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-testsys.tsunami.ethernet.rxUdpChecksums             0                       # Number of rx UDP Checksums done by device
-testsys.tsunami.ethernet.descDMAReads         2385801                       # Number of descriptors the device read w/ DMA
-testsys.tsunami.ethernet.descDMAWrites             13                       # Number of descriptors the device wrote w/ DMA
-testsys.tsunami.ethernet.descDmaReadBytes     57259224                       # number of descriptor bytes read w/ DMA
-testsys.tsunami.ethernet.descDmaWriteBytes          104                       # number of descriptor bytes write w/ DMA
-testsys.tsunami.ethernet.totBandwidth           70176                       # Total Bandwidth (bits/s)
-testsys.tsunami.ethernet.totPackets                13                       # Total Packets
-testsys.tsunami.ethernet.totBytes                1758                       # Total Bytes
-testsys.tsunami.ethernet.totPPS                    65                       # Total Tranmission Rate (packets/s)
-testsys.tsunami.ethernet.txBandwidth            38322                       # Transmit Bandwidth (bits/s)
-testsys.tsunami.ethernet.rxBandwidth            31855                       # Receive Bandwidth (bits/s)
-testsys.tsunami.ethernet.txPPS                     40                       # Packet Tranmission Rate (packets/s)
-testsys.tsunami.ethernet.rxPPS                     25                       # Packet Reception Rate (packets/s)
-testsys.tsunami.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-testsys.tsunami.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-testsys.tsunami.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-testsys.tsunami.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-testsys.tsunami.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-testsys.tsunami.ethernet.postedRxDesc               5                       # number of RxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-testsys.tsunami.ethernet.totalRxDesc                5                       # total number of RxDesc written to ISR
-testsys.tsunami.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-testsys.tsunami.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-testsys.tsunami.ethernet.postedTxIdle           19571                       # number of TxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxIdle            1                       # average number of TxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalTxIdle          2385801                       # total number of TxIdle written to ISR
-testsys.tsunami.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-testsys.tsunami.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-testsys.tsunami.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-testsys.tsunami.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-testsys.tsunami.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-testsys.tsunami.ethernet.coalescedTotal             1                       # average number of interrupts coalesced into each post
-testsys.tsunami.ethernet.postedInterrupts      2385819                       # number of posts to CPU
-testsys.tsunami.ethernet.droppedPackets             0                       # number of packets dropped
-testsys.iobus.throughput                    290423421                       # Throughput (bytes/s)
-testsys.iobus.data_through_bus               58203550                       # Total data (bytes)
-drivesys.physmem.bytes_read::cpu.inst        76205572                       # Number of bytes read from this memory
-drivesys.physmem.bytes_read::cpu.data        26284292                       # Number of bytes read from this memory
-drivesys.physmem.bytes_read::tsunami.ethernet     57260526                       # Number of bytes read from this memory
-drivesys.physmem.bytes_read::total          159750390                       # Number of bytes read from this memory
-drivesys.physmem.bytes_inst_read::cpu.inst     76205572                       # Number of instructions bytes read from this memory
-drivesys.physmem.bytes_inst_read::total      76205572                       # Number of instructions bytes read from this memory
-drivesys.physmem.bytes_written::cpu.data     14619632                       # Number of bytes written to this memory
-drivesys.physmem.bytes_written::tsunami.ethernet         1064                       # Number of bytes written to this memory
-drivesys.physmem.bytes_written::total        14620696                       # Number of bytes written to this memory
-drivesys.physmem.num_reads::cpu.inst         19051393                       # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::cpu.data          3647049                       # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::tsunami.ethernet      2385838                       # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::total            25084280                       # Number of read requests responded to by this memory
-drivesys.physmem.num_writes::cpu.data         2024776                       # Number of write requests responded to by this memory
-drivesys.physmem.num_writes::tsunami.ethernet           37                       # Number of write requests responded to by this memory
-drivesys.physmem.num_writes::total            2024813                       # Number of write requests responded to by this memory
-drivesys.physmem.bw_read::cpu.inst          380249708                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::cpu.data          131153065                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::tsunami.ethernet    285717930                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::total             797120704                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::cpu.inst     380249708                       # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::total        380249708                       # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::cpu.data          72948876                       # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::tsunami.ethernet         5309                       # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::total             72954185                       # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.inst         380249708                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.data         204101941                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::tsunami.ethernet    285723240                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::total            870074889                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.membus.throughput                  874808223                       # Throughput (bytes/s)
-drivesys.membus.data_through_bus            175319690                       # Total data (bytes)
-drivesys.membus.snoop_data_through_bus              0                       # Total snoop data (bytes)
-drivesys.disk0.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
-drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk0.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
-drivesys.disk0.dma_write_full_pages                 0                       # Number of full page size DMA writes.
-drivesys.disk0.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
-drivesys.disk0.dma_write_txs                        0                       # Number of DMA write transactions.
-drivesys.disk2.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
-drivesys.disk2.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk2.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
-drivesys.disk2.dma_write_full_pages                 0                       # Number of full page size DMA writes.
-drivesys.disk2.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
-drivesys.disk2.dma_write_txs                        0                       # Number of DMA write transactions.
-drivesys.cpu.dtb.fetch_hits                         0                       # ITB hits
-drivesys.cpu.dtb.fetch_misses                       0                       # ITB misses
-drivesys.cpu.dtb.fetch_acv                          0                       # ITB acv
-drivesys.cpu.dtb.fetch_accesses                     0                       # ITB accesses
-drivesys.cpu.dtb.read_hits                    3725273                       # DTB read hits
-drivesys.cpu.dtb.read_misses                      487                       # DTB read misses
-drivesys.cpu.dtb.read_acv                          30                       # DTB read access violations
-drivesys.cpu.dtb.read_accesses                 267991                       # DTB read accesses
-drivesys.cpu.dtb.write_hits                   2084079                       # DTB write hits
-drivesys.cpu.dtb.write_misses                      82                       # DTB write misses
-drivesys.cpu.dtb.write_acv                         10                       # DTB write access violations
-drivesys.cpu.dtb.write_accesses                133239                       # DTB write accesses
-drivesys.cpu.dtb.data_hits                    5809352                       # DTB hits
-drivesys.cpu.dtb.data_misses                      569                       # DTB misses
-drivesys.cpu.dtb.data_acv                          40                       # DTB access violations
-drivesys.cpu.dtb.data_accesses                 401230                       # DTB accesses
-drivesys.cpu.itb.fetch_hits                   4197628                       # ITB hits
-drivesys.cpu.itb.fetch_misses                     194                       # ITB misses
-drivesys.cpu.itb.fetch_acv                         22                       # ITB acv
-drivesys.cpu.itb.fetch_accesses               4197822                       # ITB accesses
-drivesys.cpu.itb.read_hits                          0                       # DTB read hits
-drivesys.cpu.itb.read_misses                        0                       # DTB read misses
-drivesys.cpu.itb.read_acv                           0                       # DTB read access violations
-drivesys.cpu.itb.read_accesses                      0                       # DTB read accesses
-drivesys.cpu.itb.write_hits                         0                       # DTB write hits
-drivesys.cpu.itb.write_misses                       0                       # DTB write misses
-drivesys.cpu.itb.write_acv                          0                       # DTB write access violations
-drivesys.cpu.itb.write_accesses                     0                       # DTB write accesses
-drivesys.cpu.itb.data_hits                          0                       # DTB hits
-drivesys.cpu.itb.data_misses                        0                       # DTB misses
-drivesys.cpu.itb.data_acv                           0                       # DTB access violations
-drivesys.cpu.itb.data_accesses                      0                       # DTB accesses
-drivesys.cpu.numCycles                      801631448                       # number of cpu cycles simulated
-drivesys.cpu.numWorkItemsStarted                    0                       # number of work items this cpu started
-drivesys.cpu.numWorkItemsCompleted                  0                       # number of work items this cpu completed
-drivesys.cpu.committedInsts                  19050784                       # Number of instructions committed
-drivesys.cpu.committedOps                    19050784                       # Number of ops (including micro ops) committed
-drivesys.cpu.num_int_alu_accesses            17740632                       # Number of integer alu accesses
-drivesys.cpu.num_fp_alu_accesses                 1412                       # Number of float alu accesses
-drivesys.cpu.num_func_calls                   1265024                       # number of times a function call or return occured
-drivesys.cpu.num_conditional_control_insts      1264985                       # number of instructions that are conditional controls
-drivesys.cpu.num_int_insts                   17740632                       # number of integer instructions
-drivesys.cpu.num_fp_insts                        1412                       # number of float instructions
-drivesys.cpu.num_int_register_reads          23072330                       # number of times the integer registers were read
-drivesys.cpu.num_int_register_writes         13981107                       # number of times the integer registers were written
-drivesys.cpu.num_fp_register_reads                760                       # number of times the floating registers were read
-drivesys.cpu.num_fp_register_writes               766                       # number of times the floating registers were written
-drivesys.cpu.num_mem_refs                     5830788                       # number of memory refs
-drivesys.cpu.num_load_insts                   3746196                       # Number of load instructions
-drivesys.cpu.num_store_insts                  2084592                       # Number of store instructions
-drivesys.cpu.num_idle_cycles             782579974.227931                       # Number of idle cycles
-drivesys.cpu.num_busy_cycles             19051473.772069                       # Number of busy cycles
-drivesys.cpu.not_idle_fraction               0.023766                       # Percentage of non-idle cycles
-drivesys.cpu.idle_fraction                   0.976234                       # Percentage of idle cycles
-drivesys.cpu.kern.inst.arm                          0                       # number of arm instructions executed
-drivesys.cpu.kern.inst.quiesce                  19876                       # number of quiesce instructions executed
-drivesys.cpu.kern.inst.hwrei                   143591                       # number of hwrei instructions executed
-drivesys.cpu.kern.ipl_count::0                  60359     42.42%     42.42% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::21                 19727     13.86%     56.28% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::22                   205      0.14%     56.42% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::31                 62011     43.58%    100.00% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::total             142302                       # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_good::0                   60359     42.91%     42.91% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::21                  19727     14.03%     56.94% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::22                    205      0.15%     57.09% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::31                  60360     42.91%    100.00% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::total              140651                       # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_ticks::0           197399332500     98.50%     98.50% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::21             798910750      0.40%     98.90% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::22               4407500      0.00%     98.90% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::31            2205211250      1.10%    100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::total       200407862000                       # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_used::0                       1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::21                      1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::22                      1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::31               0.973376                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::total            0.988398                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.syscall::2                        1      4.55%      4.55% # number of syscalls executed
-drivesys.cpu.kern.syscall::6                        3     13.64%     18.18% # number of syscalls executed
-drivesys.cpu.kern.syscall::17                       2      9.09%     27.27% # number of syscalls executed
-drivesys.cpu.kern.syscall::97                       1      4.55%     31.82% # number of syscalls executed
-drivesys.cpu.kern.syscall::99                       2      9.09%     40.91% # number of syscalls executed
-drivesys.cpu.kern.syscall::101                      2      9.09%     50.00% # number of syscalls executed
-drivesys.cpu.kern.syscall::102                      3     13.64%     63.64% # number of syscalls executed
-drivesys.cpu.kern.syscall::104                      1      4.55%     68.18% # number of syscalls executed
-drivesys.cpu.kern.syscall::105                      3     13.64%     81.82% # number of syscalls executed
-drivesys.cpu.kern.syscall::106                      1      4.55%     86.36% # number of syscalls executed
-drivesys.cpu.kern.syscall::118                      2      9.09%     95.45% # number of syscalls executed
-drivesys.cpu.kern.syscall::150                      1      4.55%    100.00% # number of syscalls executed
-drivesys.cpu.kern.syscall::total                   22                       # number of syscalls executed
-drivesys.cpu.kern.callpal::swpctx                  72      0.06%      0.06% # number of callpals executed
-drivesys.cpu.kern.callpal::tbi                      5      0.00%      0.06% # number of callpals executed
-drivesys.cpu.kern.callpal::swpipl              102333     83.31%     83.37% # number of callpals executed
-drivesys.cpu.kern.callpal::rdps                   354      0.29%     83.66% # number of callpals executed
-drivesys.cpu.kern.callpal::rdusp                    1      0.00%     83.66% # number of callpals executed
-drivesys.cpu.kern.callpal::rti                  20038     16.31%     99.97% # number of callpals executed
-drivesys.cpu.kern.callpal::callsys                 25      0.02%     99.99% # number of callpals executed
-drivesys.cpu.kern.callpal::imb                      7      0.01%    100.00% # number of callpals executed
-drivesys.cpu.kern.callpal::total               122835                       # number of callpals executed
-drivesys.cpu.kern.mode_switch::kernel             214                       # number of protection mode switches
-drivesys.cpu.kern.mode_switch::user               140                       # number of protection mode switches
-drivesys.cpu.kern.mode_switch::idle             19896                       # number of protection mode switches
-drivesys.cpu.kern.mode_good::kernel               144                      
-drivesys.cpu.kern.mode_good::user                 140                      
-drivesys.cpu.kern.mode_good::idle                   4                      
-drivesys.cpu.kern.mode_switch_good::kernel     0.672897                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::user            1                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::idle     0.000201                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::total     0.014222                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_ticks::kernel         78134250      2.63%      2.63% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::user          319668250     10.78%     13.41% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::idle         2567942000     86.59%    100.00% # number of ticks spent at the given mode
-drivesys.cpu.kern.swap_context                     72                       # number of times the context was actually changed
-drivesys.tsunami.ethernet.txBytes                 798                       # Bytes Transmitted
-drivesys.tsunami.ethernet.rxBytes                 960                       # Bytes Received
-drivesys.tsunami.ethernet.txPackets                 5                       # Number of Packets Transmitted
-drivesys.tsunami.ethernet.rxPackets                 8                       # Number of Packets Received
-drivesys.tsunami.ethernet.txIpChecksums             2                       # Number of tx IP Checksums done by device
-drivesys.tsunami.ethernet.rxIpChecksums             8                       # Number of rx IP Checksums done by device
-drivesys.tsunami.ethernet.txTcpChecksums            2                       # Number of tx TCP Checksums done by device
-drivesys.tsunami.ethernet.rxTcpChecksums            8                       # Number of rx TCP Checksums done by device
-drivesys.tsunami.ethernet.txUdpChecksums            0                       # Number of tx UDP Checksums done by device
-drivesys.tsunami.ethernet.rxUdpChecksums            0                       # Number of rx UDP Checksums done by device
-drivesys.tsunami.ethernet.descDMAReads        2385809                       # Number of descriptors the device read w/ DMA
-drivesys.tsunami.ethernet.descDMAWrites            13                       # Number of descriptors the device wrote w/ DMA
-drivesys.tsunami.ethernet.descDmaReadBytes     57259416                       # number of descriptor bytes read w/ DMA
-drivesys.tsunami.ethernet.descDmaWriteBytes          104                       # number of descriptor bytes write w/ DMA
-drivesys.tsunami.ethernet.totBandwidth          70176                       # Total Bandwidth (bits/s)
-drivesys.tsunami.ethernet.totPackets               13                       # Total Packets
-drivesys.tsunami.ethernet.totBytes               1758                       # Total Bytes
-drivesys.tsunami.ethernet.totPPS                   65                       # Total Tranmission Rate (packets/s)
-drivesys.tsunami.ethernet.txBandwidth           31855                       # Transmit Bandwidth (bits/s)
-drivesys.tsunami.ethernet.rxBandwidth           38322                       # Receive Bandwidth (bits/s)
-drivesys.tsunami.ethernet.txPPS                    25                       # Packet Tranmission Rate (packets/s)
-drivesys.tsunami.ethernet.rxPPS                    40                       # Packet Reception Rate (packets/s)
-drivesys.tsunami.ethernet.postedSwi                 0                       # number of software interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedSwi              0                       # average number of Swi's coalesced into each post
-drivesys.tsunami.ethernet.totalSwi                  0                       # total number of Swi written to ISR
-drivesys.tsunami.ethernet.postedRxIdle              0                       # number of rxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-drivesys.tsunami.ethernet.totalRxIdle               0                       # total number of RxIdle written to ISR
-drivesys.tsunami.ethernet.postedRxOk                0                       # number of RxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxOk             0                       # average number of RxOk's coalesced into each post
-drivesys.tsunami.ethernet.totalRxOk                 0                       # total number of RxOk written to ISR
-drivesys.tsunami.ethernet.postedRxDesc              8                       # number of RxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-drivesys.tsunami.ethernet.totalRxDesc               8                       # total number of RxDesc written to ISR
-drivesys.tsunami.ethernet.postedTxOk                0                       # number of TxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxOk             0                       # average number of TxOk's coalesced into each post
-drivesys.tsunami.ethernet.totalTxOk                 0                       # total number of TxOk written to ISR
-drivesys.tsunami.ethernet.postedTxIdle          19726                       # number of TxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxIdle            1                       # average number of TxIdle's coalesced into each post
-drivesys.tsunami.ethernet.totalTxIdle         2385809                       # total number of TxIdle written to ISR
-drivesys.tsunami.ethernet.postedTxDesc              0                       # number of TxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-drivesys.tsunami.ethernet.totalTxDesc               0                       # total number of TxDesc written to ISR
-drivesys.tsunami.ethernet.postedRxOrn               0                       # number of RxOrn posted to CPU
-drivesys.tsunami.ethernet.coalescedRxOrn            0                       # average number of RxOrn's coalesced into each post
-drivesys.tsunami.ethernet.totalRxOrn                0                       # total number of RxOrn written to ISR
-drivesys.tsunami.ethernet.coalescedTotal            1                       # average number of interrupts coalesced into each post
-drivesys.tsunami.ethernet.postedInterrupts      2385830                       # number of posts to CPU
-drivesys.tsunami.ethernet.droppedPackets            0                       # number of packets dropped
-drivesys.iobus.throughput                   290456573                       # Throughput (bytes/s)
-drivesys.iobus.data_through_bus              58210194                       # Total data (bytes)
-
----------- End Simulation Statistics   ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000407                       # Number of seconds simulated
-sim_ticks                                   407341500                       # Number of ticks simulated
-final_tick                               4321621592000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                             5619093232                       # Simulator instruction rate (inst/s)
-host_op_rate                               5617709608                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4367114686                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 475668                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
-sim_insts                                   523862353                       # Number of instructions simulated
-sim_ops                                     523862353                       # Number of ops (including micro ops) simulated
-testsys.physmem.bytes_read::cpu.inst           144504                       # Number of bytes read from this memory
-testsys.physmem.bytes_read::cpu.data            49936                       # Number of bytes read from this memory
-testsys.physmem.bytes_read::tsunami.ethernet       116376                       # Number of bytes read from this memory
-testsys.physmem.bytes_read::total              310816                       # Number of bytes read from this memory
-testsys.physmem.bytes_inst_read::cpu.inst       144504                       # Number of instructions bytes read from this memory
-testsys.physmem.bytes_inst_read::total         144504                       # Number of instructions bytes read from this memory
-testsys.physmem.bytes_written::cpu.data         27704                       # Number of bytes written to this memory
-testsys.physmem.bytes_written::total            27704                       # Number of bytes written to this memory
-testsys.physmem.num_reads::cpu.inst             36126                       # Number of read requests responded to by this memory
-testsys.physmem.num_reads::cpu.data              6905                       # Number of read requests responded to by this memory
-testsys.physmem.num_reads::tsunami.ethernet         4849                       # Number of read requests responded to by this memory
-testsys.physmem.num_reads::total                47880                       # Number of read requests responded to by this memory
-testsys.physmem.num_writes::cpu.data             3814                       # Number of write requests responded to by this memory
-testsys.physmem.num_writes::total                3814                       # Number of write requests responded to by this memory
-testsys.physmem.bw_read::cpu.inst           354749025                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::cpu.data           122590014                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::tsunami.ethernet    285696400                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::total              763035438                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::cpu.inst      354749025                       # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::total         354749025                       # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::cpu.data           68011730                       # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::total              68011730                       # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.inst          354749025                       # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.data          190601743                       # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::tsunami.ethernet    285696400                       # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::total             831047168                       # Total bandwidth to/from this memory (bytes/s)
-testsys.membus.throughput                   835780297                       # Throughput (bytes/s)
-testsys.membus.data_through_bus                340448                       # Total data (bytes)
-testsys.membus.snoop_data_through_bus               0                       # Total snoop data (bytes)
-testsys.disk0.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
-testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk0.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
-testsys.disk0.dma_write_full_pages                  0                       # Number of full page size DMA writes.
-testsys.disk0.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
-testsys.disk0.dma_write_txs                         0                       # Number of DMA write transactions.
-testsys.disk2.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
-testsys.disk2.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk2.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
-testsys.disk2.dma_write_full_pages                  0                       # Number of full page size DMA writes.
-testsys.disk2.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
-testsys.disk2.dma_write_txs                         0                       # Number of DMA write transactions.
-testsys.cpu.dtb.fetch_hits                          0                       # ITB hits
-testsys.cpu.dtb.fetch_misses                        0                       # ITB misses
-testsys.cpu.dtb.fetch_acv                           0                       # ITB acv
-testsys.cpu.dtb.fetch_accesses                      0                       # ITB accesses
-testsys.cpu.dtb.read_hits                        7065                       # DTB read hits
-testsys.cpu.dtb.read_misses                         0                       # DTB read misses
-testsys.cpu.dtb.read_acv                            0                       # DTB read access violations
-testsys.cpu.dtb.read_accesses                       0                       # DTB read accesses
-testsys.cpu.dtb.write_hits                       3935                       # DTB write hits
-testsys.cpu.dtb.write_misses                        0                       # DTB write misses
-testsys.cpu.dtb.write_acv                           0                       # DTB write access violations
-testsys.cpu.dtb.write_accesses                      0                       # DTB write accesses
-testsys.cpu.dtb.data_hits                       11000                       # DTB hits
-testsys.cpu.dtb.data_misses                         0                       # DTB misses
-testsys.cpu.dtb.data_acv                            0                       # DTB access violations
-testsys.cpu.dtb.data_accesses                       0                       # DTB accesses
-testsys.cpu.itb.fetch_hits                       5992                       # ITB hits
-testsys.cpu.itb.fetch_misses                        0                       # ITB misses
-testsys.cpu.itb.fetch_acv                           0                       # ITB acv
-testsys.cpu.itb.fetch_accesses                   5992                       # ITB accesses
-testsys.cpu.itb.read_hits                           0                       # DTB read hits
-testsys.cpu.itb.read_misses                         0                       # DTB read misses
-testsys.cpu.itb.read_acv                            0                       # DTB read access violations
-testsys.cpu.itb.read_accesses                       0                       # DTB read accesses
-testsys.cpu.itb.write_hits                          0                       # DTB write hits
-testsys.cpu.itb.write_misses                        0                       # DTB write misses
-testsys.cpu.itb.write_acv                           0                       # DTB write access violations
-testsys.cpu.itb.write_accesses                      0                       # DTB write accesses
-testsys.cpu.itb.data_hits                           0                       # DTB hits
-testsys.cpu.itb.data_misses                         0                       # DTB misses
-testsys.cpu.itb.data_acv                            0                       # DTB access violations
-testsys.cpu.itb.data_accesses                       0                       # DTB accesses
-testsys.cpu.numCycles                          821016                       # number of cpu cycles simulated
-testsys.cpu.numWorkItemsStarted                     0                       # number of work items this cpu started
-testsys.cpu.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-testsys.cpu.committedInsts                      36126                       # Number of instructions committed
-testsys.cpu.committedOps                        36126                       # Number of ops (including micro ops) committed
-testsys.cpu.num_int_alu_accesses                33492                       # Number of integer alu accesses
-testsys.cpu.num_fp_alu_accesses                     0                       # Number of float alu accesses
-testsys.cpu.num_func_calls                       2384                       # number of times a function call or return occured
-testsys.cpu.num_conditional_control_insts         2346                       # number of instructions that are conditional controls
-testsys.cpu.num_int_insts                       33492                       # number of integer instructions
-testsys.cpu.num_fp_insts                            0                       # number of float instructions
-testsys.cpu.num_int_register_reads              43747                       # number of times the integer registers were read
-testsys.cpu.num_int_register_writes             26476                       # number of times the integer registers were written
-testsys.cpu.num_fp_register_reads                   0                       # number of times the floating registers were read
-testsys.cpu.num_fp_register_writes                  0                       # number of times the floating registers were written
-testsys.cpu.num_mem_refs                        11041                       # number of memory refs
-testsys.cpu.num_load_insts                       7105                       # Number of load instructions
-testsys.cpu.num_store_insts                      3936                       # Number of store instructions
-testsys.cpu.num_idle_cycles              784609.171892                       # Number of idle cycles
-testsys.cpu.num_busy_cycles              36406.828108                       # Number of busy cycles
-testsys.cpu.not_idle_fraction                0.044344                       # Percentage of non-idle cycles
-testsys.cpu.idle_fraction                    0.955656                       # Percentage of idle cycles
-testsys.cpu.kern.inst.arm                           0                       # number of arm instructions executed
-testsys.cpu.kern.inst.quiesce                      40                       # number of quiesce instructions executed
-testsys.cpu.kern.inst.hwrei                       295                       # number of hwrei instructions executed
-testsys.cpu.kern.ipl_count::0                     123     41.84%     41.84% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::21                     40     13.61%     55.44% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::22                      1      0.34%     55.78% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::31                    130     44.22%    100.00% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::total                 294                       # number of times we switched to this ipl
-testsys.cpu.kern.ipl_good::0                      123     42.86%     42.86% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::21                      40     13.94%     56.79% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::22                       1      0.35%     57.14% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::31                     123     42.86%    100.00% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::total                  287                       # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks::0               397967000     96.95%     96.95% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::21                3240000      0.79%     97.73% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::22                  43000      0.01%     97.74% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::31                9258000      2.26%    100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::total           410508000                       # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_used::0                        1                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::31                0.946154                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::total             0.976190                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.callpal::swpipl                  212     83.46%     83.46% # number of callpals executed
-testsys.cpu.kern.callpal::rdps                      1      0.39%     83.86% # number of callpals executed
-testsys.cpu.kern.callpal::rti                      41     16.14%    100.00% # number of callpals executed
-testsys.cpu.kern.callpal::total                   254                       # number of callpals executed
-testsys.cpu.kern.mode_switch::kernel                0                       # number of protection mode switches
-testsys.cpu.kern.mode_switch::user                  0                       # number of protection mode switches
-testsys.cpu.kern.mode_switch::idle                 41                       # number of protection mode switches
-testsys.cpu.kern.mode_good::kernel                  0                      
-testsys.cpu.kern.mode_good::user                    0                      
-testsys.cpu.kern.mode_good::idle                    0                      
-testsys.cpu.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::idle             0                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::total            0                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
-testsys.cpu.kern.swap_context                       0                       # number of times the context was actually changed
-testsys.tsunami.ethernet.descDMAReads            4849                       # Number of descriptors the device read w/ DMA
-testsys.tsunami.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
-testsys.tsunami.ethernet.descDmaReadBytes       116376                       # number of descriptor bytes read w/ DMA
-testsys.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-testsys.tsunami.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-testsys.tsunami.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-testsys.tsunami.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-testsys.tsunami.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-testsys.tsunami.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-testsys.tsunami.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-testsys.tsunami.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-testsys.tsunami.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-testsys.tsunami.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-testsys.tsunami.ethernet.postedTxIdle              40                       # number of TxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxIdle            1                       # average number of TxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalTxIdle             4849                       # total number of TxIdle written to ISR
-testsys.tsunami.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-testsys.tsunami.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-testsys.tsunami.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-testsys.tsunami.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-testsys.tsunami.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-testsys.tsunami.ethernet.coalescedTotal             1                       # average number of interrupts coalesced into each post
-testsys.tsunami.ethernet.postedInterrupts         4849                       # number of posts to CPU
-testsys.tsunami.ethernet.droppedPackets             0                       # number of packets dropped
-testsys.iobus.throughput                    290429529                       # Throughput (bytes/s)
-testsys.iobus.data_through_bus                 118304                       # Total data (bytes)
-drivesys.physmem.bytes_read::cpu.inst          144608                       # Number of bytes read from this memory
-drivesys.physmem.bytes_read::cpu.data           49952                       # Number of bytes read from this memory
-drivesys.physmem.bytes_read::tsunami.ethernet       116400                       # Number of bytes read from this memory
-drivesys.physmem.bytes_read::total             310960                       # Number of bytes read from this memory
-drivesys.physmem.bytes_inst_read::cpu.inst       144608                       # Number of instructions bytes read from this memory
-drivesys.physmem.bytes_inst_read::total        144608                       # Number of instructions bytes read from this memory
-drivesys.physmem.bytes_written::cpu.data        27688                       # Number of bytes written to this memory
-drivesys.physmem.bytes_written::total           27688                       # Number of bytes written to this memory
-drivesys.physmem.num_reads::cpu.inst            36152                       # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::cpu.data             6909                       # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::tsunami.ethernet         4850                       # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::total               47911                       # Number of read requests responded to by this memory
-drivesys.physmem.num_writes::cpu.data            3812                       # Number of write requests responded to by this memory
-drivesys.physmem.num_writes::total               3812                       # Number of write requests responded to by this memory
-drivesys.physmem.bw_read::cpu.inst          355004339                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::cpu.data          122629293                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::tsunami.ethernet    285755318                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::total             763388950                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::cpu.inst     355004339                       # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::total        355004339                       # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::cpu.data          67972451                       # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::total             67972451                       # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.inst         355004339                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.data         190601743                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::tsunami.ethernet    285755318                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::total            831361401                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.membus.throughput                  836094530                       # Throughput (bytes/s)
-drivesys.membus.data_through_bus               340576                       # Total data (bytes)
-drivesys.membus.snoop_data_through_bus              0                       # Total snoop data (bytes)
-drivesys.disk0.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
-drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk0.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
-drivesys.disk0.dma_write_full_pages                 0                       # Number of full page size DMA writes.
-drivesys.disk0.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
-drivesys.disk0.dma_write_txs                        0                       # Number of DMA write transactions.
-drivesys.disk2.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
-drivesys.disk2.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk2.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
-drivesys.disk2.dma_write_full_pages                 0                       # Number of full page size DMA writes.
-drivesys.disk2.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
-drivesys.disk2.dma_write_txs                        0                       # Number of DMA write transactions.
-drivesys.cpu.dtb.fetch_hits                         0                       # ITB hits
-drivesys.cpu.dtb.fetch_misses                       0                       # ITB misses
-drivesys.cpu.dtb.fetch_acv                          0                       # ITB acv
-drivesys.cpu.dtb.fetch_accesses                     0                       # ITB accesses
-drivesys.cpu.dtb.read_hits                       7069                       # DTB read hits
-drivesys.cpu.dtb.read_misses                        0                       # DTB read misses
-drivesys.cpu.dtb.read_acv                           0                       # DTB read access violations
-drivesys.cpu.dtb.read_accesses                      0                       # DTB read accesses
-drivesys.cpu.dtb.write_hits                      3933                       # DTB write hits
-drivesys.cpu.dtb.write_misses                       0                       # DTB write misses
-drivesys.cpu.dtb.write_acv                          0                       # DTB write access violations
-drivesys.cpu.dtb.write_accesses                     0                       # DTB write accesses
-drivesys.cpu.dtb.data_hits                      11002                       # DTB hits
-drivesys.cpu.dtb.data_misses                        0                       # DTB misses
-drivesys.cpu.dtb.data_acv                           0                       # DTB access violations
-drivesys.cpu.dtb.data_accesses                      0                       # DTB accesses
-drivesys.cpu.itb.fetch_hits                      5992                       # ITB hits
-drivesys.cpu.itb.fetch_misses                       0                       # ITB misses
-drivesys.cpu.itb.fetch_acv                          0                       # ITB acv
-drivesys.cpu.itb.fetch_accesses                  5992                       # ITB accesses
-drivesys.cpu.itb.read_hits                          0                       # DTB read hits
-drivesys.cpu.itb.read_misses                        0                       # DTB read misses
-drivesys.cpu.itb.read_acv                           0                       # DTB read access violations
-drivesys.cpu.itb.read_accesses                      0                       # DTB read accesses
-drivesys.cpu.itb.write_hits                         0                       # DTB write hits
-drivesys.cpu.itb.write_misses                       0                       # DTB write misses
-drivesys.cpu.itb.write_acv                          0                       # DTB write access violations
-drivesys.cpu.itb.write_accesses                     0                       # DTB write accesses
-drivesys.cpu.itb.data_hits                          0                       # DTB hits
-drivesys.cpu.itb.data_misses                        0                       # DTB misses
-drivesys.cpu.itb.data_acv                           0                       # DTB access violations
-drivesys.cpu.itb.data_accesses                      0                       # DTB accesses
-drivesys.cpu.numCycles                        1626240                       # number of cpu cycles simulated
-drivesys.cpu.numWorkItemsStarted                    0                       # number of work items this cpu started
-drivesys.cpu.numWorkItemsCompleted                  0                       # number of work items this cpu completed
-drivesys.cpu.committedInsts                     36152                       # Number of instructions committed
-drivesys.cpu.committedOps                       36152                       # Number of ops (including micro ops) committed
-drivesys.cpu.num_int_alu_accesses               33516                       # Number of integer alu accesses
-drivesys.cpu.num_fp_alu_accesses                    0                       # Number of float alu accesses
-drivesys.cpu.num_func_calls                      2388                       # number of times a function call or return occured
-drivesys.cpu.num_conditional_control_insts         2347                       # number of instructions that are conditional controls
-drivesys.cpu.num_int_insts                      33516                       # number of integer instructions
-drivesys.cpu.num_fp_insts                           0                       # number of float instructions
-drivesys.cpu.num_int_register_reads             43772                       # number of times the integer registers were read
-drivesys.cpu.num_int_register_writes            26499                       # number of times the integer registers were written
-drivesys.cpu.num_fp_register_reads                  0                       # number of times the floating registers were read
-drivesys.cpu.num_fp_register_writes                 0                       # number of times the floating registers were written
-drivesys.cpu.num_mem_refs                       11043                       # number of memory refs
-drivesys.cpu.num_load_insts                      7109                       # Number of load instructions
-drivesys.cpu.num_store_insts                     3934                       # Number of store instructions
-drivesys.cpu.num_idle_cycles             1590157.359061                       # Number of idle cycles
-drivesys.cpu.num_busy_cycles             36082.640939                       # Number of busy cycles
-drivesys.cpu.not_idle_fraction               0.022188                       # Percentage of non-idle cycles
-drivesys.cpu.idle_fraction                   0.977812                       # Percentage of idle cycles
-drivesys.cpu.kern.inst.arm                          0                       # number of arm instructions executed
-drivesys.cpu.kern.inst.quiesce                     41                       # number of quiesce instructions executed
-drivesys.cpu.kern.inst.hwrei                      295                       # number of hwrei instructions executed
-drivesys.cpu.kern.ipl_count::0                    123     41.84%     41.84% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::21                    40     13.61%     55.44% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::22                     1      0.34%     55.78% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::31                   130     44.22%    100.00% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::total                294                       # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_good::0                     123     42.86%     42.86% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::21                     40     13.94%     56.79% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::22                      1      0.35%     57.14% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::31                    123     42.86%    100.00% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::total                 287                       # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_ticks::0              400289000     98.46%     98.46% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::21               1620000      0.40%     98.86% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::22                 21500      0.01%     98.86% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::31               4629500      1.14%    100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::total          406560000                       # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_used::0                       1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::21                      1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::22                      1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::31               0.946154                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::total            0.976190                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.callpal::swpipl                 212     83.46%     83.46% # number of callpals executed
-drivesys.cpu.kern.callpal::rdps                     1      0.39%     83.86% # number of callpals executed
-drivesys.cpu.kern.callpal::rti                     41     16.14%    100.00% # number of callpals executed
-drivesys.cpu.kern.callpal::total                  254                       # number of callpals executed
-drivesys.cpu.kern.mode_switch::kernel               0                       # number of protection mode switches
-drivesys.cpu.kern.mode_switch::user                 0                       # number of protection mode switches
-drivesys.cpu.kern.mode_switch::idle                41                       # number of protection mode switches
-drivesys.cpu.kern.mode_good::kernel                 0                      
-drivesys.cpu.kern.mode_good::user                   0                      
-drivesys.cpu.kern.mode_good::idle                   0                      
-drivesys.cpu.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::user          nan                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::idle            0                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::total            0                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_ticks::kernel                0                       # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::user                  0                       # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::idle                  0                       # number of ticks spent at the given mode
-drivesys.cpu.kern.swap_context                      0                       # number of times the context was actually changed
-drivesys.tsunami.ethernet.descDMAReads           4850                       # Number of descriptors the device read w/ DMA
-drivesys.tsunami.ethernet.descDMAWrites             0                       # Number of descriptors the device wrote w/ DMA
-drivesys.tsunami.ethernet.descDmaReadBytes       116400                       # number of descriptor bytes read w/ DMA
-drivesys.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-drivesys.tsunami.ethernet.postedSwi                 0                       # number of software interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedSwi              0                       # average number of Swi's coalesced into each post
-drivesys.tsunami.ethernet.totalSwi                  0                       # total number of Swi written to ISR
-drivesys.tsunami.ethernet.postedRxIdle              0                       # number of rxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-drivesys.tsunami.ethernet.totalRxIdle               0                       # total number of RxIdle written to ISR
-drivesys.tsunami.ethernet.postedRxOk                0                       # number of RxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxOk             0                       # average number of RxOk's coalesced into each post
-drivesys.tsunami.ethernet.totalRxOk                 0                       # total number of RxOk written to ISR
-drivesys.tsunami.ethernet.postedRxDesc              0                       # number of RxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-drivesys.tsunami.ethernet.totalRxDesc               0                       # total number of RxDesc written to ISR
-drivesys.tsunami.ethernet.postedTxOk                0                       # number of TxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxOk             0                       # average number of TxOk's coalesced into each post
-drivesys.tsunami.ethernet.totalTxOk                 0                       # total number of TxOk written to ISR
-drivesys.tsunami.ethernet.postedTxIdle             40                       # number of TxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxIdle            1                       # average number of TxIdle's coalesced into each post
-drivesys.tsunami.ethernet.totalTxIdle            4850                       # total number of TxIdle written to ISR
-drivesys.tsunami.ethernet.postedTxDesc              0                       # number of TxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-drivesys.tsunami.ethernet.totalTxDesc               0                       # total number of TxDesc written to ISR
-drivesys.tsunami.ethernet.postedRxOrn               0                       # number of RxOrn posted to CPU
-drivesys.tsunami.ethernet.coalescedRxOrn            0                       # average number of RxOrn's coalesced into each post
-drivesys.tsunami.ethernet.totalRxOrn                0                       # total number of RxOrn written to ISR
-drivesys.tsunami.ethernet.coalescedTotal            1                       # average number of interrupts coalesced into each post
-drivesys.tsunami.ethernet.postedInterrupts         4850                       # number of posts to CPU
-drivesys.tsunami.ethernet.droppedPackets            0                       # number of packets dropped
-drivesys.iobus.throughput                   290488448                       # Throughput (bytes/s)
-drivesys.iobus.data_through_bus                118328                       # Total data (bytes)
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +29,10 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=InOrderCPU
 children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -36,7 +40,7 @@
 branchPred=system.cpu.branchPred
 cachePorts=2
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 div16Latency=1
 div16RepeatRate=1
@@ -66,6 +70,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 stageTracing=false
 stageWidth=4
 switched_out=false
@@ -84,11 +89,9 @@
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -96,10 +99,11 @@
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,22 +114,32 @@
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -136,12 +150,21 @@
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -154,10 +177,11 @@
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -168,16 +192,25 @@
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -207,10 +240,14 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -221,19 +258,21 @@
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
-lines_per_rowbuffer=32
+lines_per_rowbuffer=128
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -244,6 +283,5 @@
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,14 +1,12 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:17:23
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 18737000 because target called exit()
+Exiting @ tick 25046000 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,11 +4,11 @@
 sim_ticks                                    25046000                       # Number of ticks simulated
 final_tick                                   25046000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  25238                       # Simulator instruction rate (inst/s)
-host_op_rate                                    25236                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               98905790                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225424                       # Number of bytes of host memory used
-host_seconds                                     0.25                       # Real time elapsed on the host
+host_inst_rate                                  95102                       # Simulator instruction rate (inst/s)
+host_op_rate                                    95065                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              372483053                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251296                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             19200                       # Number of bytes read from this memory
@@ -307,15 +307,15 @@
 system.cpu.stage4.idleCycles                    45635                       # Number of cycles 0 instructions are processed.
 system.cpu.stage4.runCycles                      4458                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage4.utilization                8.899447                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.icache.tags.replacements                      0                       # number of replacements
-system.cpu.icache.tags.tagsinuse                141.294375                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                      560                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    301                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                   1.860465                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     141.294375                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.068991                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.068991                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements                 0                       # number of replacements
+system.cpu.icache.tags.tagsinuse           141.294375                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                 560                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               301                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              1.860465                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   141.294375                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.068991                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.068991                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst          560                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total             560                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst           560                       # number of demand (read+write) hits
@@ -410,17 +410,17 @@
 system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        278750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               197.784355                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                       1                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   395                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  0.002532                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    141.343624                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     56.440731                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          197.784355                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              395                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.002532                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   141.343624                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    56.440731                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004313                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001722                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.006036                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006036                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
@@ -535,15 +535,15 @@
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58120.535714                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56425.373134                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                103.103023                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                     1601                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    168                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                   9.529762                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data     103.103023                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.025172                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.025172                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           103.103023                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1601                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               168                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              9.529762                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   103.103023                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.025172                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.025172                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1086                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1086                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          515                       # number of WriteReq hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +29,10 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +47,7 @@
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +96,7 @@
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +126,9 @@
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +136,11 @@
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +151,21 @@
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
@@ -422,10 +435,11 @@
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -436,12 +450,21 @@
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -454,10 +477,11 @@
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -468,16 +492,25 @@
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -507,10 +540,14 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -521,19 +558,21 @@
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
-lines_per_rowbuffer=32
+lines_per_rowbuffer=128
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -544,6 +583,5 @@
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,14 +1,12 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 14:39:12
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 16032500 because target called exit()
+Exiting @ tick 20671000 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,11 +4,11 @@
 sim_ticks                                    20671000                       # Number of ticks simulated
 final_tick                                   20671000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  25591                       # Simulator instruction rate (inst/s)
-host_op_rate                                    25589                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               83008053                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 227468                       # Number of bytes of host memory used
-host_seconds                                     0.25                       # Real time elapsed on the host
+host_inst_rate                                  88473                       # Simulator instruction rate (inst/s)
+host_op_rate                                    88437                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              286800280                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251964                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        6372                       # Number of instructions simulated
 sim_ops                                          6372                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             20032                       # Number of bytes read from this memory
@@ -525,15 +525,15 @@
 system.cpu.toL2Bus.respLayer0.utilization          2.6                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        281250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                      0                       # number of replacements
-system.cpu.icache.tags.tagsinuse                159.268512                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                     1898                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    314                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                   6.044586                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     159.268512                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.077768                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.077768                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements                 0                       # number of replacements
+system.cpu.icache.tags.tagsinuse           159.268512                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1898                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               314                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.044586                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   159.268512                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.077768                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.077768                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         1898                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            1898                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          1898                       # number of demand (read+write) hits
@@ -609,17 +609,17 @@
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67819.841270                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 67819.841270                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               218.982908                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                       1                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   414                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  0.002415                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    159.353389                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     59.629519                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          218.982908                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              414                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.002415                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   159.353389                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    59.629519                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004863                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001820                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.006683                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006683                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
@@ -734,15 +734,15 @@
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62693.965517                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57354.508197                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                106.762654                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                     2236                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    174                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  12.850575                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data     106.762654                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.026065                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.026065                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           106.762654                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2236                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               174                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.850575                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   106.762654                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.026065                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.026065                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1730                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1730                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          506                       # number of WriteReq hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +29,16 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +57,10 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -99,11 +107,16 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -112,13 +125,12 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:33:24
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,11 +4,11 @@
 sim_ticks                                     3208000                       # Number of ticks simulated
 final_tick                                    3208000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                   2502                       # Simulator instruction rate (inst/s)
-host_op_rate                                     2502                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1255935                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215792                       # Number of bytes of host memory used
-host_seconds                                     2.55                       # Real time elapsed on the host
+host_inst_rate                                 970296                       # Simulator instruction rate (inst/s)
+host_op_rate                                   964138                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              481112221                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 242172                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             25600                       # Number of bytes read from this memory
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu physmem ruby sys_port_proxy
+children=clk_domain cpu physmem ruby sys_port_proxy
 boot_osflags=a
-clock=1
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +29,16 @@
 work_item_id=-1
 system_port=system.sys_port_proxy.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1
+
 [system.cpu]
 type=TimingSimpleCPU
-children=dtb interrupts isa itb tracer workload
+children=clk_domain dtb interrupts isa itb tracer workload
 branchPred=Null
 checker=Null
-clock=1
+clk_domain=system.cpu.clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +56,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -59,6 +64,10 @@
 dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
 icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
 
+[system.cpu.clk_domain]
+type=SrcClockDomain
+clock=1
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
@@ -98,31 +107,34 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=0.000000
-clock=1
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30
 latency_var=0
 null=true
 range=0:134217727
-zero=false
 
 [system.ruby]
 type=RubySystem
-children=dir_cntrl0 l1_cntrl0 network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler
 block_size_bytes=64
-clock=1
+clk_domain=system.ruby.clk_domain
 mem_size=134217728
 no_mem_vec=false
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
 
+[system.ruby.clk_domain]
+type=SrcClockDomain
+clock=1
+
 [system.ruby.dir_cntrl0]
 type=Directory_Controller
 children=directory memBuffer
 buffer_size=0
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=1
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
@@ -149,7 +161,7 @@
 bank_queue_size=12
 banks_per_rank=8
 basic_bus_busy_time=2
-clock=3
+clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
 mem_ctl_latency=12
@@ -170,7 +182,7 @@
 buffer_size=0
 cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=0
 issue_latency=2
 number_of_TBEs=256
@@ -199,7 +211,7 @@
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
 access_phys_mem=false
-clock=1
+clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
 icache=system.ruby.l1_cntrl0.cacheMemory
@@ -213,12 +225,17 @@
 version=0
 slave=system.cpu.icache_port system.cpu.dcache_port
 
+[system.ruby.memctrl_clk_domain]
+type=DerivedClockDomain
+clk_divider=3
+clk_domain=system.ruby.clk_domain
+
 [system.ruby.network]
 type=SimpleNetwork
 children=ext_links0 ext_links1 int_links0 int_links1
 adaptive_routing=false
 buffer_size=0
-clock=1
+clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
@@ -240,7 +257,7 @@
 
 [system.ruby.network.ext_links0.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=0
 virt_nets=10
 
@@ -256,7 +273,7 @@
 
 [system.ruby.network.ext_links1.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=1
 virt_nets=10
 
@@ -272,7 +289,7 @@
 
 [system.ruby.network.int_links0.node_b]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=2
 virt_nets=10
 
@@ -295,7 +312,7 @@
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-clock=1
+clk_domain=system.clk_domain
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats	Wed Aug 07 15:24:58 2013 -0500
@@ -1,4 +1,4 @@
-Real time: Jun/24/2013 23:54:11
+Real time: Jul/17/2013 12:17:46
 
 Profiler Stats
 --------------
@@ -7,18 +7,18 @@
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.56
-Virtual_time_in_minutes: 0.00933333
-Virtual_time_in_hours:   0.000155556
-Virtual_time_in_days:    6.48148e-06
+Virtual_time_in_seconds: 0.7
+Virtual_time_in_minutes: 0.0116667
+Virtual_time_in_hours:   0.000194444
+Virtual_time_in_days:    8.10185e-06
 
 Ruby_current_time: 143853
 Ruby_start_time: 0
 Ruby_cycles: 143853
 
-mbytes_resident: 56.2734
-mbytes_total: 150.727
-resident_ratio: 0.3734
+mbytes_resident: 49.2773
+mbytes_total: 128.367
+resident_ratio: 0.384
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -77,7 +77,7 @@
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11329
+page_reclaims: 10218
 page_faults: 0
 swaps: 0
 block_inputs: 0
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,6 +1,6 @@
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 hack: be nice to actually delete the event here
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:45:23
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,11 +4,11 @@
 sim_ticks                                      143853                       # Number of ticks simulated
 final_tick                                     143853                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  39172                       # Simulator instruction rate (inst/s)
-host_op_rate                                    39167                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 881633                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 145628                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
+host_inst_rate                                  59144                       # Simulator instruction rate (inst/s)
+host_op_rate                                    59131                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1330885                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 131452                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         6718                       # Number of cache demand hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +29,16 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +56,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +66,11 @@
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,32 @@
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +117,21 @@
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -119,10 +144,11 @@
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -133,17 +159,27 @@
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -171,11 +207,16 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -184,13 +225,12 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:45:47
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,11 +4,11 @@
 sim_ticks                                    32544000                       # Number of ticks simulated
 final_tick                                   32544000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  19861                       # Simulator instruction rate (inst/s)
-host_op_rate                                    19860                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              101141711                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224276                       # Number of bytes of host memory used
-host_seconds                                     0.32                       # Real time elapsed on the host
+host_inst_rate                                 480030                       # Simulator instruction rate (inst/s)
+host_op_rate                                   479039                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2435434312                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 250812                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             17792                       # Number of bytes read from this memory
@@ -97,15 +97,15 @@
 system.cpu.num_busy_cycles                      65088                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.icache.tags.replacements                      0                       # number of replacements
-system.cpu.icache.tags.tagsinuse                127.998991                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                     6122                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    279                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                  21.942652                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     127.998991                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.062500                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.062500                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements                 0                       # number of replacements
+system.cpu.icache.tags.tagsinuse           127.998991                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                6122                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               279                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             21.942652                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   127.998991                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.062500                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.062500                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         6122                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            6122                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          6122                       # number of demand (read+write) hits
@@ -175,17 +175,17 @@
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               184.497210                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                       1                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   373                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  0.002681                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    128.017765                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     56.479444                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          184.497210                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              373                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.002681                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   128.017765                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    56.479444                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003907                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001724                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.005630                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005630                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
@@ -300,15 +300,15 @@
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                103.762109                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                     1880                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    168                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  11.190476                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data     103.762109                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.025333                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.025333                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           103.762109                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1880                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               168                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.190476                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   103.762109                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.025333                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.025333                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1088                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1088                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          792                       # number of WriteReq hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +29,10 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +47,7 @@
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +96,7 @@
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +126,9 @@
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +136,11 @@
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +151,21 @@
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
@@ -422,10 +435,11 @@
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -436,12 +450,21 @@
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -454,10 +477,11 @@
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -468,16 +492,25 @@
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -507,10 +540,14 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -521,19 +558,21 @@
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
-lines_per_rowbuffer=32
+lines_per_rowbuffer=128
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -544,6 +583,5 @@
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,14 +1,12 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 14:39:13
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 9350000 because target called exit()
+Exiting @ tick 11933500 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,11 +4,11 @@
 sim_ticks                                    11933500                       # Number of ticks simulated
 final_tick                                   11933500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                    492                       # Simulator instruction rate (inst/s)
-host_op_rate                                      492                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                2461163                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226156                       # Number of bytes of host memory used
-host_seconds                                     4.85                       # Real time elapsed on the host
+host_inst_rate                                  64250                       # Simulator instruction rate (inst/s)
+host_op_rate                                    64183                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              320658748                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251060                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
 sim_ops                                          2387                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             12032                       # Number of bytes read from this memory
@@ -521,15 +521,15 @@
 system.cpu.toL2Bus.respLayer0.utilization          2.7                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        135500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                      0                       # number of replacements
-system.cpu.icache.tags.tagsinuse                 91.523450                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                      816                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    188                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                   4.340426                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst      91.523450                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.044689                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.044689                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements                 0                       # number of replacements
+system.cpu.icache.tags.tagsinuse            91.523450                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                 816                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               188                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              4.340426                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst    91.523450                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.044689                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.044689                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst          816                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total             816                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst           816                       # number of demand (read+write) hits
@@ -605,17 +605,17 @@
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68062.494681                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 68062.494681                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               119.912589                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                       0                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   249                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                         0                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst     91.722261                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     28.190328                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          119.912589                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              249                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    91.722261                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    28.190328                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002799                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000860                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.003659                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.003659                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_misses::cpu.inst          188                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           61                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total          249                       # number of ReadReq misses
@@ -724,15 +724,15 @@
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61447.058824                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56620.879121                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                 44.879167                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                      758                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                     85                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                   8.917647                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data      44.879167                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.010957                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.010957                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            44.879167                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                 758                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.917647                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data    44.879167                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.010957                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.010957                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data          545                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             545                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          213                       # number of WriteReq hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +29,16 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +57,10 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -99,11 +107,16 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -112,13 +125,12 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:45:35
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,10 +4,10 @@
 sim_ticks                                     1297500                       # Number of ticks simulated
 final_tick                                    1297500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 388869                       # Simulator instruction rate (inst/s)
-host_op_rate                                   388153                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              195100518                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215488                       # Number of bytes of host memory used
+host_inst_rate                                 322423                       # Simulator instruction rate (inst/s)
+host_op_rate                                   321403                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              161368996                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 241248                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu physmem ruby sys_port_proxy
+children=clk_domain cpu physmem ruby sys_port_proxy
 boot_osflags=a
-clock=1
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +29,16 @@
 work_item_id=-1
 system_port=system.sys_port_proxy.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1
+
 [system.cpu]
 type=TimingSimpleCPU
-children=dtb interrupts isa itb tracer workload
+children=clk_domain dtb interrupts isa itb tracer workload
 branchPred=Null
 checker=Null
-clock=1
+clk_domain=system.cpu.clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +56,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -59,6 +64,10 @@
 dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
 icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
 
+[system.cpu.clk_domain]
+type=SrcClockDomain
+clock=1
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
@@ -98,31 +107,34 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=0.000000
-clock=1
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30
 latency_var=0
 null=true
 range=0:134217727
-zero=false
 
 [system.ruby]
 type=RubySystem
-children=dir_cntrl0 l1_cntrl0 network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler
 block_size_bytes=64
-clock=1
+clk_domain=system.ruby.clk_domain
 mem_size=134217728
 no_mem_vec=false
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
 
+[system.ruby.clk_domain]
+type=SrcClockDomain
+clock=1
+
 [system.ruby.dir_cntrl0]
 type=Directory_Controller
 children=directory memBuffer
 buffer_size=0
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=1
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
@@ -149,7 +161,7 @@
 bank_queue_size=12
 banks_per_rank=8
 basic_bus_busy_time=2
-clock=3
+clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
 mem_ctl_latency=12
@@ -170,7 +182,7 @@
 buffer_size=0
 cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=0
 issue_latency=2
 number_of_TBEs=256
@@ -199,7 +211,7 @@
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
 access_phys_mem=false
-clock=1
+clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
 icache=system.ruby.l1_cntrl0.cacheMemory
@@ -213,12 +225,17 @@
 version=0
 slave=system.cpu.icache_port system.cpu.dcache_port
 
+[system.ruby.memctrl_clk_domain]
+type=DerivedClockDomain
+clk_divider=3
+clk_domain=system.ruby.clk_domain
+
 [system.ruby.network]
 type=SimpleNetwork
 children=ext_links0 ext_links1 int_links0 int_links1
 adaptive_routing=false
 buffer_size=0
-clock=1
+clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
@@ -240,7 +257,7 @@
 
 [system.ruby.network.ext_links0.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=0
 virt_nets=10
 
@@ -256,7 +273,7 @@
 
 [system.ruby.network.ext_links1.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=1
 virt_nets=10
 
@@ -272,7 +289,7 @@
 
 [system.ruby.network.int_links0.node_b]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=2
 virt_nets=10
 
@@ -295,7 +312,7 @@
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-clock=1
+clk_domain=system.clk_domain
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats	Wed Aug 07 15:24:58 2013 -0500
@@ -1,4 +1,4 @@
-Real time: Jun/24/2013 23:54:11
+Real time: Jul/17/2013 12:17:46
 
 Profiler Stats
 --------------
@@ -7,18 +7,18 @@
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.48
-Virtual_time_in_minutes: 0.008
-Virtual_time_in_hours:   0.000133333
-Virtual_time_in_days:    5.55556e-06
+Virtual_time_in_seconds: 0.62
+Virtual_time_in_minutes: 0.0103333
+Virtual_time_in_hours:   0.000172222
+Virtual_time_in_days:    7.17593e-06
 
 Ruby_current_time: 52498
 Ruby_start_time: 0
 Ruby_cycles: 52498
 
-mbytes_resident: 54.1094
-mbytes_total: 148.324
-resident_ratio: 0.364857
+mbytes_resident: 47.0742
+mbytes_total: 126.273
+resident_ratio: 0.37292
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -77,7 +77,7 @@
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11286
+page_reclaims: 9646
 page_faults: 0
 swaps: 0
 block_inputs: 0
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,6 +1,6 @@
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:29:25
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,11 +4,11 @@
 sim_ticks                                       52498                       # Number of ticks simulated
 final_tick                                      52498                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  30872                       # Simulator instruction rate (inst/s)
-host_op_rate                                    30864                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 628609                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 144188                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                  55482                       # Simulator instruction rate (inst/s)
+host_op_rate                                    55444                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1128930                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 129308                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         2668                       # Number of cache demand hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +29,16 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +56,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +66,11 @@
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,32 @@
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +117,21 @@
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -119,10 +144,11 @@
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -133,17 +159,27 @@
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -171,11 +207,16 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -184,13 +225,12 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:46:30
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,10 +4,10 @@
 sim_ticks                                    16524000                       # Number of ticks simulated
 final_tick                                   16524000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 252355                       # Simulator instruction rate (inst/s)
-host_op_rate                                   251860                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1611932908                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223992                       # Number of bytes of host memory used
+host_inst_rate                                 260754                       # Simulator instruction rate (inst/s)
+host_op_rate                                   260052                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1663681591                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 249880                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
@@ -97,15 +97,15 @@
 system.cpu.num_busy_cycles                      33048                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.icache.tags.replacements                      0                       # number of replacements
-system.cpu.icache.tags.tagsinuse                 80.050296                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                     2423                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    163                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                  14.865031                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst      80.050296                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.039087                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.039087                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements                 0                       # number of replacements
+system.cpu.icache.tags.tagsinuse            80.050296                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                2423                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               163                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             14.865031                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst    80.050296                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.039087                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.039087                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         2423                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            2423                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          2423                       # number of demand (read+write) hits
@@ -175,17 +175,17 @@
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               107.162861                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                       0                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   218                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                         0                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst     80.168669                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     26.994192                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          107.162861                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              218                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    80.168669                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    26.994192                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002447                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000824                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.003270                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.003270                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_misses::cpu.inst          163                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           55                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total          218                       # number of ReadReq misses
@@ -294,15 +294,15 @@
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                 47.437790                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                      627                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                     82                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                   7.646341                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data      47.437790                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.011581                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.011581                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            47.437790                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                 627                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs                82                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              7.646341                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data    47.437790                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.011581                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.011581                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data          360                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             360                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          267                       # number of WriteReq hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +29,10 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +47,7 @@
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=system.cpu.checker
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +96,7 @@
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +126,9 @@
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -136,7 +139,7 @@
 children=dtb isa itb tracer
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -155,6 +158,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.checker.tracer
@@ -170,7 +174,7 @@
 
 [system.cpu.checker.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[5]
@@ -200,7 +204,7 @@
 
 [system.cpu.checker.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[4]
@@ -210,10 +214,11 @@
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -224,12 +229,21 @@
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -238,7 +252,7 @@
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -508,10 +522,11 @@
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -522,12 +537,21 @@
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -556,17 +580,18 @@
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -577,16 +602,25 @@
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -616,10 +650,14 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -630,19 +668,21 @@
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
-lines_per_rowbuffer=32
+lines_per_rowbuffer=128
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -653,6 +693,5 @@
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,13 +1,11 @@
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 26 2013 15:15:53
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
+gem5 compiled Jul 17 2013 12:12:01
+gem5 started Jul 17 2013 12:12:10
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 13706000 because target called exit()
+Exiting @ tick 16494000 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,11 +4,11 @@
 sim_ticks                                    16494000                       # Number of ticks simulated
 final_tick                                   16494000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  31208                       # Simulator instruction rate (inst/s)
-host_op_rate                                    38937                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              112083077                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 244336                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
+host_inst_rate                                  54524                       # Simulator instruction rate (inst/s)
+host_op_rate                                    68019                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              195775919                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 266688                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5729                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             17344                       # Number of bytes read from this memory
@@ -577,15 +577,15 @@
 system.cpu.toL2Bus.respLayer0.utilization          2.9                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        231495                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                      4                       # number of replacements
-system.cpu.icache.tags.tagsinuse                145.483199                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                     1583                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    291                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                   5.439863                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     145.483199                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.071037                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.071037                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements                 4                       # number of replacements
+system.cpu.icache.tags.tagsinuse           145.483199                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1583                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               291                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.439863                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   145.483199                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.071037                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.071037                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         1583                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            1583                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          1583                       # number of demand (read+write) hits
@@ -661,17 +661,17 @@
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               183.328645                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                      40                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   352                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  0.113636                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    136.957008                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     46.371637                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          183.328645                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                 40                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              352                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.113636                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   136.957008                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    46.371637                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004180                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001415                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.005595                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005595                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst           20                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           20                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total             40                       # number of ReadReq hits
@@ -795,15 +795,15 @@
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                 85.893510                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                     2390                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    146                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  16.369863                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data      85.893510                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.020970                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.020970                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            85.893510                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2390                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             16.369863                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data    85.893510                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.020970                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.020970                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1763                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1763                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          606                       # number of WriteReq hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +29,10 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +47,7 @@
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +96,7 @@
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +126,9 @@
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +136,11 @@
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +151,21 @@
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -161,7 +174,7 @@
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -431,10 +444,11 @@
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -445,12 +459,21 @@
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -479,17 +502,18 @@
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -500,16 +524,25 @@
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -539,10 +572,14 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -553,19 +590,21 @@
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
-lines_per_rowbuffer=32
+lines_per_rowbuffer=128
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -576,6 +615,5 @@
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,13 +1,11 @@
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 26 2013 15:15:53
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
+gem5 compiled Jul 17 2013 12:12:01
+gem5 started Jul 17 2013 12:12:10
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 13706000 because target called exit()
+Exiting @ tick 16494000 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,10 +4,10 @@
 sim_ticks                                    16494000                       # Number of ticks simulated
 final_tick                                   16494000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  66928                       # Simulator instruction rate (inst/s)
-host_op_rate                                    83502                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              240363471                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 244336                       # Number of bytes of host memory used
+host_inst_rate                                  62486                       # Simulator instruction rate (inst/s)
+host_op_rate                                    77950                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              224351425                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 266364                       # Number of bytes of host memory used
 host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5729                       # Number of ops (including micro ops) simulated
@@ -532,15 +532,15 @@
 system.cpu.toL2Bus.respLayer0.utilization          2.9                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        231495                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                      4                       # number of replacements
-system.cpu.icache.tags.tagsinuse                145.483199                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                     1583                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    291                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                   5.439863                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     145.483199                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.071037                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.071037                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements                 4                       # number of replacements
+system.cpu.icache.tags.tagsinuse           145.483199                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1583                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               291                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.439863                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   145.483199                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.071037                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.071037                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         1583                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            1583                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          1583                       # number of demand (read+write) hits
@@ -616,17 +616,17 @@
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               183.328645                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                      40                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   352                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  0.113636                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    136.957008                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     46.371637                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          183.328645                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                 40                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              352                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.113636                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   136.957008                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    46.371637                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004180                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001415                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.005595                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005595                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst           20                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           20                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total             40                       # number of ReadReq hits
@@ -750,15 +750,15 @@
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                 85.893510                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                     2390                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    146                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  16.369863                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data      85.893510                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.020970                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.020970                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            85.893510                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2390                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             16.369863                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data    85.893510                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.020970                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.020970                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1763                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1763                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          606                       # number of WriteReq hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +29,16 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=checker dtb interrupts isa itb tracer workload
 branchPred=Null
 checker=system.cpu.checker
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +57,10 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -68,12 +76,13 @@
 children=dtb isa itb tracer
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=-1
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.checker.dtb
+exitOnError=false
 function_trace=false
 function_trace_start=0
 interrupts=Null
@@ -86,9 +95,12 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.checker.tracer
+updateOnError=false
+warnOnlyOnLoadError=true
 workload=system.cpu.workload
 
 [system.cpu.checker.dtb]
@@ -99,7 +111,7 @@
 
 [system.cpu.checker.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 
@@ -128,7 +140,7 @@
 
 [system.cpu.checker.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 
@@ -143,7 +155,7 @@
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
@@ -176,7 +188,7 @@
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
@@ -203,11 +215,16 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -216,13 +233,12 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:44:07
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker
+gem5 compiled Jul 17 2013 12:12:01
+gem5 started Jul 17 2013 12:12:09
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,10 +4,10 @@
 sim_ticks                                     2870500                       # Number of ticks simulated
 final_tick                                    2870500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 686137                       # Simulator instruction rate (inst/s)
-host_op_rate                                   854515                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              427336749                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 232512                       # Number of bytes of host memory used
+host_inst_rate                                 656289                       # Simulator instruction rate (inst/s)
+host_op_rate                                   816155                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              407546098                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 256632                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5729                       # Number of ops (including micro ops) simulated
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +29,16 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +57,10 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -71,7 +79,7 @@
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
@@ -104,7 +112,7 @@
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
@@ -131,11 +139,16 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -144,13 +157,12 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:43:56
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic
+gem5 compiled Jul 17 2013 12:12:01
+gem5 started Jul 17 2013 12:12:09
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,10 +4,10 @@
 sim_ticks                                     2870500                       # Number of ticks simulated
 final_tick                                    2870500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 723203                       # Simulator instruction rate (inst/s)
-host_op_rate                                   900650                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              450384934                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 232532                       # Number of bytes of host memory used
+host_inst_rate                                 695515                       # Simulator instruction rate (inst/s)
+host_op_rate                                   864282                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              431510017                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 256528                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5729                       # Number of ops (including micro ops) simulated
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +29,16 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +56,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +66,11 @@
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,12 +81,21 @@
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -89,17 +104,18 @@
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,12 +126,21 @@
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -144,17 +169,18 @@
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -165,17 +191,27 @@
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -203,11 +239,16 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -216,13 +257,12 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:44:20
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing
+gem5 compiled Jul 17 2013 12:12:01
+gem5 started Jul 17 2013 12:12:10
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,11 +4,11 @@
 sim_ticks                                    25969000                       # Number of ticks simulated
 final_tick                                   25969000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 220478                       # Simulator instruction rate (inst/s)
-host_op_rate                                   273604                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1251201624                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 241012                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 387501                       # Simulator instruction rate (inst/s)
+host_op_rate                                   480458                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2195506520                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 264956                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4565                       # Number of instructions simulated
 sim_ops                                          5672                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             14400                       # Number of bytes read from this memory
@@ -107,15 +107,15 @@
 system.cpu.num_busy_cycles                      51938                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.icache.tags.replacements                      1                       # number of replacements
-system.cpu.icache.tags.tagsinuse                114.614391                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                     4364                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    241                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                  18.107884                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     114.614391                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.055964                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.055964                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements                 1                       # number of replacements
+system.cpu.icache.tags.tagsinuse           114.614391                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                4364                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               241                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             18.107884                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   114.614391                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.055964                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.055964                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         4364                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            4364                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          4364                       # number of demand (read+write) hits
@@ -185,17 +185,17 @@
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               154.071129                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                      32                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   307                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  0.104235                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    105.889758                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     48.181371                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          154.071129                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                 32                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              307                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.104235                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   105.889758                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    48.181371                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003231                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001470                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.004702                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.004702                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst           16                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           16                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total             32                       # number of ReadReq hits
@@ -313,15 +313,15 @@
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                 83.000387                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                     1940                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    141                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  13.758865                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data      83.000387                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.020264                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.020264                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            83.000387                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1940                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               141                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             13.758865                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data    83.000387                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.020264                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.020264                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1048                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1048                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          870                       # number of WriteReq hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +29,10 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=InOrderCPU
 children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -36,7 +40,7 @@
 branchPred=system.cpu.branchPred
 cachePorts=2
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 div16Latency=1
 div16RepeatRate=1
@@ -66,6 +70,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 stageTracing=false
 stageWidth=4
 switched_out=false
@@ -84,11 +89,9 @@
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -96,10 +99,11 @@
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,22 +114,32 @@
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=MipsTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -136,12 +150,21 @@
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=MipsInterrupts
 
@@ -156,10 +179,11 @@
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -170,16 +194,25 @@
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -209,10 +242,14 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -223,19 +260,21 @@
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
-lines_per_rowbuffer=32
+lines_per_rowbuffer=128
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -246,6 +285,5 @@
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,14 +1,12 @@
-Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing/simout
-Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:56:08
-gem5 started Mar 26 2013 14:56:29
-gem5 executing on ribera.cs.wisc.edu
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing
+gem5 compiled Jul 17 2013 12:18:02
+gem5 started Jul 17 2013 12:18:16
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 19339000 because target called exit()
+Exiting @ tick 24587000 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,11 +4,11 @@
 sim_ticks                                    24587000                       # Number of ticks simulated
 final_tick                                   24587000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  41260                       # Simulator instruction rate (inst/s)
-host_op_rate                                    41253                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              174426700                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226212                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
+host_inst_rate                                  70886                       # Simulator instruction rate (inst/s)
+host_op_rate                                    70856                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              299498621                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 252172                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        5814                       # Number of instructions simulated
 sim_ops                                          5814                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             20288                       # Number of bytes read from this memory
@@ -293,15 +293,15 @@
 system.cpu.stage4.idleCycles                    46285                       # Number of cycles 0 instructions are processed.
 system.cpu.stage4.runCycles                      2890                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage4.utilization                5.876970                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.icache.tags.replacements                     13                       # number of replacements
-system.cpu.icache.tags.tagsinuse                150.350232                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                      428                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    319                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                   1.341693                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     150.350232                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.073413                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.073413                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements                13                       # number of replacements
+system.cpu.icache.tags.tagsinuse           150.350232                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                 428                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               319                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              1.341693                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   150.350232                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.073413                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.073413                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst          428                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total             428                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst           428                       # number of demand (read+write) hits
@@ -396,17 +396,17 @@
 system.cpu.toL2Bus.respLayer0.utilization          2.2                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        228000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               208.008874                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                       2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   404                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  0.004950                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    152.043119                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     55.965756                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          208.008874                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              404                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.004950                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   152.043119                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    55.965756                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004640                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001708                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.006348                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006348                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
@@ -521,15 +521,15 @@
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62804.347826                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59360.439560                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                 89.984709                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                     1638                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    138                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  11.869565                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data      89.984709                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.021969                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.021969                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            89.984709                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1638                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               138                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.869565                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data    89.984709                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021969                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021969                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1066                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1066                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          572                       # number of WriteReq hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +29,10 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +47,7 @@
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +96,7 @@
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +126,9 @@
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +136,11 @@
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +151,21 @@
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=MipsTLB
 size=64
@@ -422,10 +435,11 @@
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -436,12 +450,21 @@
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=MipsInterrupts
 
@@ -456,10 +479,11 @@
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -470,16 +494,25 @@
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -509,10 +542,14 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -523,19 +560,21 @@
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
-lines_per_rowbuffer=32
+lines_per_rowbuffer=128
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -546,6 +585,5 @@
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,14 +1,12 @@
-Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simout
-Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:56:08
-gem5 started Mar 26 2013 14:56:29
-gem5 executing on ribera.cs.wisc.edu
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
+gem5 compiled Jul 17 2013 12:18:02
+gem5 started Jul 17 2013 12:18:16
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 17026500 because target called exit()
+Exiting @ tick 21805500 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,11 +4,11 @@
 sim_ticks                                    21805500                       # Number of ticks simulated
 final_tick                                   21805500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  79844                       # Simulator instruction rate (inst/s)
-host_op_rate                                    79828                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              337538221                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228256                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  51478                       # Simulator instruction rate (inst/s)
+host_op_rate                                    51457                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              217537578                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 252932                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        5156                       # Number of instructions simulated
 sim_ops                                          5156                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             21440                       # Number of bytes read from this memory
@@ -509,15 +509,15 @@
 system.cpu.toL2Bus.respLayer0.utilization          2.6                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        230000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                     17                       # number of replacements
-system.cpu.icache.tags.tagsinuse                160.845390                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                     1531                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    338                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                   4.529586                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     160.845390                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.078538                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.078538                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements                17                       # number of replacements
+system.cpu.icache.tags.tagsinuse           160.845390                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1531                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               338                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              4.529586                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   160.845390                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.078538                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.078538                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         1531                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            1531                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          1531                       # number of demand (read+write) hits
@@ -593,17 +593,17 @@
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70585.798817                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 70585.798817                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               220.792115                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                       3                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   426                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  0.007042                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    163.133804                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     57.658310                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          220.792115                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  3                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              426                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.007042                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   163.133804                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    57.658310                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004978                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001760                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.006738                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006738                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            3                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            3                       # number of demand (read+write) hits
@@ -718,15 +718,15 @@
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64862.676056                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59663.522013                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                 91.308892                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                     2395                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    142                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  16.866197                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data      91.308892                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.022292                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.022292                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            91.308892                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2395                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               142                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             16.866197                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data    91.308892                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.022292                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.022292                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1832                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1832                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          563                       # number of WriteReq hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +29,16 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +57,10 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -101,11 +109,16 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -114,13 +127,12 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic/simout
-Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:16:48
-gem5 started Jan 23 2013 15:17:17
-gem5 executing on ribera.cs.wisc.edu
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic
+gem5 compiled Jul 17 2013 12:18:02
+gem5 started Jul 17 2013 12:18:16
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,10 +4,10 @@
 sim_ticks                                     2907000                       # Number of ticks simulated
 final_tick                                    2907000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 727521                       # Simulator instruction rate (inst/s)
-host_op_rate                                   725084                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              361375060                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216568                       # Number of bytes of host memory used
+host_inst_rate                                 517575                       # Simulator instruction rate (inst/s)
+host_op_rate                                   515908                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              257164650                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 243156                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5814                       # Number of instructions simulated
 sim_ops                                          5814                       # Number of ops (including micro ops) simulated
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu physmem ruby sys_port_proxy
+children=clk_domain cpu physmem ruby sys_port_proxy
 boot_osflags=a
-clock=1
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +29,16 @@
 work_item_id=-1
 system_port=system.sys_port_proxy.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1
+
 [system.cpu]
 type=TimingSimpleCPU
-children=dtb interrupts isa itb tracer workload
+children=clk_domain dtb interrupts isa itb tracer workload
 branchPred=Null
 checker=Null
-clock=1
+clk_domain=system.cpu.clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +56,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -59,6 +64,10 @@
 dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
 icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
 
+[system.cpu.clk_domain]
+type=SrcClockDomain
+clock=1
+
 [system.cpu.dtb]
 type=MipsTLB
 size=64
@@ -100,31 +109,34 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=0.000000
-clock=1
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30
 latency_var=0
 null=true
 range=0:134217727
-zero=false
 
 [system.ruby]
 type=RubySystem
-children=dir_cntrl0 l1_cntrl0 network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler
 block_size_bytes=64
-clock=1
+clk_domain=system.ruby.clk_domain
 mem_size=134217728
 no_mem_vec=false
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
 
+[system.ruby.clk_domain]
+type=SrcClockDomain
+clock=1
+
 [system.ruby.dir_cntrl0]
 type=Directory_Controller
 children=directory memBuffer
 buffer_size=0
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=1
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
@@ -151,7 +163,7 @@
 bank_queue_size=12
 banks_per_rank=8
 basic_bus_busy_time=2
-clock=3
+clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
 mem_ctl_latency=12
@@ -172,7 +184,7 @@
 buffer_size=0
 cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=0
 issue_latency=2
 number_of_TBEs=256
@@ -201,7 +213,7 @@
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
 access_phys_mem=false
-clock=1
+clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
 icache=system.ruby.l1_cntrl0.cacheMemory
@@ -215,12 +227,17 @@
 version=0
 slave=system.cpu.icache_port system.cpu.dcache_port
 
+[system.ruby.memctrl_clk_domain]
+type=DerivedClockDomain
+clk_divider=3
+clk_domain=system.ruby.clk_domain
+
 [system.ruby.network]
 type=SimpleNetwork
 children=ext_links0 ext_links1 int_links0 int_links1
 adaptive_routing=false
 buffer_size=0
-clock=1
+clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
@@ -242,7 +259,7 @@
 
 [system.ruby.network.ext_links0.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=0
 virt_nets=10
 
@@ -258,7 +275,7 @@
 
 [system.ruby.network.ext_links1.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=1
 virt_nets=10
 
@@ -274,7 +291,7 @@
 
 [system.ruby.network.int_links0.node_b]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=2
 virt_nets=10
 
@@ -297,7 +314,7 @@
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-clock=1
+clk_domain=system.clk_domain
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,6 +1,6 @@
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 hack: be nice to actually delete the event here
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby/simout
-Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:16:48
-gem5 started Jan 23 2013 15:17:40
-gem5 executing on ribera.cs.wisc.edu
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
+gem5 compiled Jul 17 2013 12:18:02
+gem5 started Jul 17 2013 12:18:16
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,10 +4,10 @@
 sim_ticks                                      125334                       # Number of ticks simulated
 final_tick                                     125334                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  43626                       # Simulator instruction rate (inst/s)
-host_op_rate                                    43619                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 940162                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 147408                       # Number of bytes of host memory used
+host_inst_rate                                  45524                       # Simulator instruction rate (inst/s)
+host_op_rate                                    45510                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 980769                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 133116                       # Number of bytes of host memory used
 host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                        5814                       # Number of instructions simulated
 sim_ops                                          5814                       # Number of ops (including micro ops) simulated
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +29,16 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +56,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +66,11 @@
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,32 @@
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=MipsTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +117,21 @@
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=MipsInterrupts
 
@@ -121,10 +146,11 @@
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -135,17 +161,27 @@
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -173,11 +209,16 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -186,13 +227,12 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simout
-Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:16:48
-gem5 started Jan 23 2013 15:17:28
-gem5 executing on ribera.cs.wisc.edu
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing
+gem5 compiled Jul 17 2013 12:18:02
+gem5 started Jul 17 2013 12:18:16
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,11 +4,11 @@
 sim_ticks                                    31633000                       # Number of ticks simulated
 final_tick                                   31633000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 482351                       # Simulator instruction rate (inst/s)
-host_op_rate                                   481309                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2613274672                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225064                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 347947                       # Simulator instruction rate (inst/s)
+host_op_rate                                   347211                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1885436193                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251540                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5814                       # Number of instructions simulated
 sim_ops                                          5814                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             19264                       # Number of bytes read from this memory
@@ -83,15 +83,15 @@
 system.cpu.num_busy_cycles                      63266                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.icache.tags.replacements                     13                       # number of replacements
-system.cpu.icache.tags.tagsinuse                132.545353                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                     5513                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    303                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                  18.194719                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     132.545353                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.064719                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.064719                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements                13                       # number of replacements
+system.cpu.icache.tags.tagsinuse           132.545353                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                5513                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               303                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             18.194719                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   132.545353                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.064719                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.064719                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         5513                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            5513                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          5513                       # number of demand (read+write) hits
@@ -161,17 +161,17 @@
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               188.114191                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                       2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   388                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  0.005155                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    133.890657                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     54.223533                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          188.114191                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              388                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.005155                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   133.890657                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    54.223533                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004086                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001655                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.005741                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005741                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
@@ -286,15 +286,15 @@
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                 87.492114                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                     1950                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    138                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  14.130435                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data      87.492114                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.021360                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.021360                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            87.492114                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1950                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               138                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             14.130435                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data    87.492114                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021360                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021360                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1076                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1076                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          874                       # number of WriteReq hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +29,10 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -44,7 +48,7 @@
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -93,6 +97,7 @@
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -122,11 +127,9 @@
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -134,10 +137,11 @@
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -148,12 +152,21 @@
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=PowerTLB
 size=64
@@ -423,10 +436,11 @@
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -437,12 +451,21 @@
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=PowerInterrupts
 
@@ -455,10 +478,11 @@
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -469,16 +493,25 @@
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -508,10 +541,14 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -522,19 +559,21 @@
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
-lines_per_rowbuffer=32
+lines_per_rowbuffer=128
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -545,6 +584,5 @@
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,13 +1,11 @@
-Redirecting stdout to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simout
-Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:59:37
-gem5 started Mar 26 2013 14:59:57
-gem5 executing on ribera.cs.wisc.edu
-command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
+gem5 compiled Jul 17 2013 12:18:34
+gem5 started Jul 17 2013 12:18:48
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 14724500 because target called exit()
+Exiting @ tick 18469500 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,11 +4,11 @@
 sim_ticks                                    18469500                       # Number of ticks simulated
 final_tick                                   18469500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  54927                       # Simulator instruction rate (inst/s)
-host_op_rate                                    54916                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              175080000                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224296                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_inst_rate                                  93610                       # Simulator instruction rate (inst/s)
+host_op_rate                                    93575                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              298285386                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 249708                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        5792                       # Number of instructions simulated
 sim_ops                                          5792                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             22080                       # Number of bytes read from this memory
@@ -507,15 +507,15 @@
 system.cpu.toL2Bus.respLayer0.utilization          3.2                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        163000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                      0                       # number of replacements
-system.cpu.icache.tags.tagsinuse                167.253035                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                     1372                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    351                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                   3.908832                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     167.253035                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.081667                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.081667                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements                 0                       # number of replacements
+system.cpu.icache.tags.tagsinuse           167.253035                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1372                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               351                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              3.908832                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   167.253035                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.081667                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.081667                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         1372                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            1372                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          1372                       # number of demand (read+write) hits
@@ -591,17 +591,17 @@
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66831.196581                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 66831.196581                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               197.401673                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                       7                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   399                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  0.017544                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    166.141608                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     31.260065                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          197.401673                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  7                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              399                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.017544                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   166.141608                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    31.260065                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005070                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000954                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.006024                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006024                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            6                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              7                       # number of ReadReq hits
@@ -719,15 +719,15 @@
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64608.910891                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56546.524664                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                 63.117277                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                     2192                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    102                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  21.490196                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data      63.117277                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.015409                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.015409                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            63.117277                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2192                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               102                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             21.490196                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data    63.117277                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.015409                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.015409                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1473                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1473                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          719                       # number of WriteReq hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,13 +29,17 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
 UnifiedTLB=true
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -54,6 +58,10 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -100,11 +108,16 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -113,13 +126,12 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic/simout
-Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:33:02
-gem5 started Jan 23 2013 15:33:19
-gem5 executing on ribera.cs.wisc.edu
-command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic
+gem5 compiled Jul 17 2013 12:18:34
+gem5 started Jul 17 2013 12:18:48
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,10 +4,10 @@
 sim_ticks                                     2896000                       # Number of ticks simulated
 final_tick                                    2896000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 671850                       # Simulator instruction rate (inst/s)
-host_op_rate                                   669870                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              333940022                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 212612                       # Number of bytes of host memory used
+host_inst_rate                                1069696                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1064970                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              530143005                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 240076                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5793                       # Number of instructions simulated
 sim_ops                                          5793                       # Number of ops (including micro ops) simulated
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +29,10 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=InOrderCPU
 children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -36,7 +40,7 @@
 branchPred=system.cpu.branchPred
 cachePorts=2
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 div16Latency=1
 div16RepeatRate=1
@@ -66,6 +70,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 stageTracing=false
 stageWidth=4
 switched_out=false
@@ -84,11 +89,9 @@
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -96,10 +99,11 @@
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,22 +114,32 @@
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -136,12 +150,21 @@
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=SparcInterrupts
 
@@ -154,10 +177,11 @@
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -168,16 +192,25 @@
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -207,10 +240,14 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -221,19 +258,21 @@
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
-lines_per_rowbuffer=32
+lines_per_rowbuffer=128
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -244,6 +283,5 @@
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:04:14
-gem5 started Mar 26 2013 15:04:37
-gem5 executing on ribera.cs.wisc.edu
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing
+gem5 compiled Jul 17 2013 12:19:08
+gem5 started Jul 17 2013 12:19:19
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Hello World!Exiting @ tick 16783500 because target called exit()
+Hello World!Exiting @ tick 20802500 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,11 +4,11 @@
 sim_ticks                                    20802500                       # Number of ticks simulated
 final_tick                                   20802500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  39959                       # Simulator instruction rate (inst/s)
-host_op_rate                                    39952                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              155990706                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 232536                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
+host_inst_rate                                  52456                       # Simulator instruction rate (inst/s)
+host_op_rate                                    52442                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              204744149                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253624                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             18496                       # Number of bytes read from this memory
@@ -275,15 +275,15 @@
 system.cpu.stage4.idleCycles                    38449                       # Number of cycles 0 instructions are processed.
 system.cpu.stage4.runCycles                      3157                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage4.utilization                7.587848                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.icache.tags.replacements                      0                       # number of replacements
-system.cpu.icache.tags.tagsinuse                142.145699                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                      892                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    291                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                   3.065292                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     142.145699                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.069407                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.069407                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements                 0                       # number of replacements
+system.cpu.icache.tags.tagsinuse           142.145699                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                 892                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               291                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              3.065292                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   142.145699                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.069407                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.069407                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst          892                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total             892                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst           892                       # number of demand (read+write) hits
@@ -378,17 +378,17 @@
 system.cpu.toL2Bus.respLayer0.utilization          2.4                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        219500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               168.511029                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                       3                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   342                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  0.008772                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    141.570095                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     26.940934                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          168.511029                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  3                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              342                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.008772                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   141.570095                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    26.940934                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004320                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000822                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.005143                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005143                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
@@ -506,15 +506,15 @@
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59138.059701                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58940.307329                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                 84.821490                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                      914                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    135                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                   6.770370                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data      84.821490                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.020708                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.020708                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            84.821490                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                 914                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               135                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              6.770370                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data    84.821490                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.020708                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.020708                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data          654                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             654                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          260                       # number of WriteReq hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +29,16 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +57,10 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -99,11 +107,16 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -112,13 +125,12 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 16:12:14
-gem5 executing on ribera.cs.wisc.edu
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic
+gem5 compiled Jul 17 2013 12:19:08
+gem5 started Jul 17 2013 12:19:19
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 2694500 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,10 +4,10 @@
 sim_ticks                                     2694500                       # Number of ticks simulated
 final_tick                                    2694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 565055                       # Simulator instruction rate (inst/s)
-host_op_rate                                   563581                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              284338324                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222908                       # Number of bytes of host memory used
+host_inst_rate                                 602982                       # Simulator instruction rate (inst/s)
+host_op_rate                                   599827                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              302068234                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 244360                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu physmem ruby sys_port_proxy
+children=clk_domain cpu physmem ruby sys_port_proxy
 boot_osflags=a
-clock=1
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +29,16 @@
 work_item_id=-1
 system_port=system.sys_port_proxy.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1
+
 [system.cpu]
 type=TimingSimpleCPU
-children=dtb interrupts isa itb tracer workload
+children=clk_domain dtb interrupts isa itb tracer workload
 branchPred=Null
 checker=Null
-clock=1
+clk_domain=system.cpu.clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +56,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -59,6 +64,10 @@
 dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
 icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
 
+[system.cpu.clk_domain]
+type=SrcClockDomain
+clock=1
+
 [system.cpu.dtb]
 type=SparcTLB
 size=64
@@ -98,31 +107,34 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=0.000000
-clock=1
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30
 latency_var=0
 null=true
 range=0:134217727
-zero=false
 
 [system.ruby]
 type=RubySystem
-children=dir_cntrl0 l1_cntrl0 network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler
 block_size_bytes=64
-clock=1
+clk_domain=system.ruby.clk_domain
 mem_size=134217728
 no_mem_vec=false
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
 
+[system.ruby.clk_domain]
+type=SrcClockDomain
+clock=1
+
 [system.ruby.dir_cntrl0]
 type=Directory_Controller
 children=directory memBuffer
 buffer_size=0
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=1
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
@@ -149,7 +161,7 @@
 bank_queue_size=12
 banks_per_rank=8
 basic_bus_busy_time=2
-clock=3
+clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
 mem_ctl_latency=12
@@ -170,7 +182,7 @@
 buffer_size=0
 cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=0
 issue_latency=2
 number_of_TBEs=256
@@ -199,7 +211,7 @@
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
 access_phys_mem=false
-clock=1
+clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
 icache=system.ruby.l1_cntrl0.cacheMemory
@@ -213,12 +225,17 @@
 version=0
 slave=system.cpu.icache_port system.cpu.dcache_port
 
+[system.ruby.memctrl_clk_domain]
+type=DerivedClockDomain
+clk_divider=3
+clk_domain=system.ruby.clk_domain
+
 [system.ruby.network]
 type=SimpleNetwork
 children=ext_links0 ext_links1 int_links0 int_links1
 adaptive_routing=false
 buffer_size=0
-clock=1
+clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
@@ -240,7 +257,7 @@
 
 [system.ruby.network.ext_links0.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=0
 virt_nets=10
 
@@ -256,7 +273,7 @@
 
 [system.ruby.network.ext_links1.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=1
 virt_nets=10
 
@@ -272,7 +289,7 @@
 
 [system.ruby.network.int_links0.node_b]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=2
 virt_nets=10
 
@@ -295,7 +312,7 @@
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-clock=1
+clk_domain=system.clk_domain
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats	Wed Aug 07 15:24:58 2013 -0500
@@ -1,4 +1,4 @@
-Real time: Jun/24/2013 23:56:22
+Real time: Jul/17/2013 12:19:20
 
 Profiler Stats
 --------------
@@ -7,18 +7,18 @@
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.51
-Virtual_time_in_minutes: 0.0085
-Virtual_time_in_hours:   0.000141667
-Virtual_time_in_days:    5.90278e-06
+Virtual_time_in_seconds: 0.71
+Virtual_time_in_minutes: 0.0118333
+Virtual_time_in_hours:   0.000197222
+Virtual_time_in_days:    8.21759e-06
 
 Ruby_current_time: 107952
 Ruby_start_time: 0
 Ruby_cycles: 107952
 
-mbytes_resident: 56.8633
-mbytes_total: 157.191
-resident_ratio: 0.361795
+mbytes_resident: 49.8125
+mbytes_total: 130.812
+resident_ratio: 0.380883
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -77,7 +77,7 @@
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11996
+page_reclaims: 10355
 page_faults: 0
 swaps: 0
 block_inputs: 0
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,6 +1,6 @@
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 hack: be nice to actually delete the event here
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 16:01:36
-gem5 executing on ribera.cs.wisc.edu
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby
+gem5 compiled Jul 17 2013 12:19:08
+gem5 started Jul 17 2013 12:19:20
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 107952 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,11 +4,11 @@
 sim_ticks                                      107952                       # Number of ticks simulated
 final_tick                                     107952                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  37306                       # Simulator instruction rate (inst/s)
-host_op_rate                                    37301                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 755806                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 148468                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
+host_inst_rate                                  56537                       # Simulator instruction rate (inst/s)
+host_op_rate                                    56519                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1145017                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 134088                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         5469                       # Number of cache demand hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +29,16 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +56,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +66,11 @@
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,32 @@
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +117,21 @@
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=SparcInterrupts
 
@@ -119,10 +144,11 @@
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -133,17 +159,27 @@
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -171,11 +207,16 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -184,13 +225,12 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 16:12:36
-gem5 executing on ribera.cs.wisc.edu
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing
+gem5 compiled Jul 17 2013 12:19:08
+gem5 started Jul 17 2013 12:19:19
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 27800000 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,11 +4,11 @@
 sim_ticks                                    27800000                       # Number of ticks simulated
 final_tick                                   27800000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 413138                       # Simulator instruction rate (inst/s)
-host_op_rate                                   412367                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2148212772                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 231400                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 314968                       # Simulator instruction rate (inst/s)
+host_op_rate                                   314217                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1636244102                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 252740                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             16320                       # Number of bytes read from this memory
@@ -65,15 +65,15 @@
 system.cpu.num_busy_cycles                      55600                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.icache.tags.replacements                      0                       # number of replacements
-system.cpu.icache.tags.tagsinuse                117.043638                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                     5114                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    257                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                  19.898833                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     117.043638                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.057150                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.057150                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements                 0                       # number of replacements
+system.cpu.icache.tags.tagsinuse           117.043638                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                5114                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               257                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             19.898833                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   117.043638                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.057150                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.057150                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         5114                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            5114                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          5114                       # number of demand (read+write) hits
@@ -143,17 +143,17 @@
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               142.183999                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                       3                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   308                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  0.009740                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    116.519250                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     25.664749                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          142.183999                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  3                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              308                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.009740                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   116.519250                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    25.664749                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003556                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000783                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.004339                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.004339                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
@@ -271,15 +271,15 @@
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                 82.118455                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                     1253                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    135                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                   9.281481                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data      82.118455                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.020048                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.020048                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            82.118455                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1253                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               135                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              9.281481                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data    82.118455                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.020048                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.020048                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data          661                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             661                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          592                       # number of WriteReq hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +29,10 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1
@@ -43,7 +47,7 @@
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +96,7 @@
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +126,9 @@
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=2
@@ -133,10 +136,11 @@
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +151,21 @@
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
@@ -422,10 +435,11 @@
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -436,12 +450,21 @@
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -457,10 +480,11 @@
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -471,16 +495,25 @@
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -529,10 +562,14 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -543,19 +580,21 @@
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
-lines_per_rowbuffer=32
+lines_per_rowbuffer=128
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -566,6 +605,5 @@
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,16 +1,14 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 14:39:13
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 Hello world!
 Hello world!
-Exiting @ tick 24422500 because target called exit()
+Exiting @ tick 24404000 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,11 +4,11 @@
 sim_ticks                                    24404000                       # Number of ticks simulated
 final_tick                                   24404000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  52847                       # Simulator instruction rate (inst/s)
-host_op_rate                                    52845                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              101181200                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228064                       # Number of bytes of host memory used
-host_seconds                                     0.24                       # Real time elapsed on the host
+host_inst_rate                                  77188                       # Simulator instruction rate (inst/s)
+host_op_rate                                    77176                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              147756650                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 252540                       # Number of bytes of host memory used
+host_seconds                                     0.17                       # Real time elapsed on the host
 sim_insts                                       12745                       # Number of instructions simulated
 sim_ops                                         12745                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             39936                       # Number of bytes read from this memory
@@ -676,17 +676,17 @@
 system.cpu.toL2Bus.respLayer0.utilization          4.2                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        566500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
-system.cpu.icache.tags.replacements::0                   6                       # number of replacements
-system.cpu.icache.tags.replacements::1                   0                       # number of replacements
-system.cpu.icache.tags.replacements::total               6                       # number of replacements
-system.cpu.icache.tags.tagsinuse                309.632563                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                     4375                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    626                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                   6.988818                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     309.632563                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.151188                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.151188                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements::0              6                       # number of replacements
+system.cpu.icache.tags.replacements::1              0                       # number of replacements
+system.cpu.icache.tags.replacements::total            6                       # number of replacements
+system.cpu.icache.tags.tagsinuse           309.632563                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                4375                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               626                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.988818                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   309.632563                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.151188                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.151188                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         4375                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            4375                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          4375                       # number of demand (read+write) hits
@@ -762,19 +762,19 @@
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75077.070288                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 75077.070288                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements::0                  0                       # number of replacements
-system.cpu.l2cache.tags.replacements::1                  0                       # number of replacements
-system.cpu.l2cache.tags.replacements::total              0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               428.856997                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                       2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   828                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  0.002415                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    310.126222                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    118.730775                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements::0             0                       # number of replacements
+system.cpu.l2cache.tags.replacements::1             0                       # number of replacements
+system.cpu.l2cache.tags.replacements::total            0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          428.856997                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              828                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.002415                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   310.126222                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   118.730775                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009464                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.003623                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.013088                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.013088                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
@@ -889,17 +889,17 @@
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        68000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64037.987680                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements::0                   0                       # number of replacements
-system.cpu.dcache.tags.replacements::1                   0                       # number of replacements
-system.cpu.dcache.tags.replacements::total               0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                211.884963                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                     4493                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    350                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  12.837143                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data     211.884963                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.051730                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.051730                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements::0              0                       # number of replacements
+system.cpu.dcache.tags.replacements::1              0                       # number of replacements
+system.cpu.dcache.tags.replacements::total            0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           211.884963                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                4493                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               350                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.837143                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   211.884963                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.051730                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.051730                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         3469                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            3469                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data         1024                       # number of WriteReq hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +29,10 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=InOrderCPU
 children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -36,7 +40,7 @@
 branchPred=system.cpu.branchPred
 cachePorts=2
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 div16Latency=1
 div16RepeatRate=1
@@ -66,6 +70,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 stageTracing=false
 stageWidth=4
 switched_out=false
@@ -84,11 +89,9 @@
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -96,10 +99,11 @@
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,22 +114,32 @@
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -136,12 +150,21 @@
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=SparcInterrupts
 
@@ -154,10 +177,11 @@
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -168,16 +192,25 @@
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -207,10 +240,14 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -221,19 +258,21 @@
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
-lines_per_rowbuffer=32
+lines_per_rowbuffer=128
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -244,6 +283,5 @@
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,2 +1,4 @@
-warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
+fatal: Can't load object file tests/test-progs/insttest/bin/sparc/linux/insttest
+ @ cycle 0
+[create:build/SPARC/sim/process.cc, line 613]
+Memory Usage: 242116 KBytes
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,23 +1,8 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 16:09:42
-gem5 executing on ribera.cs.wisc.edu
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing
+gem5 compiled Jul 17 2013 12:19:08
+gem5 started Jul 17 2013 12:19:20
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-Begining test of difficult SPARC instructions...
-LDSTUB:		Passed
-SWAP:		Passed
-CAS FAIL:	Passed
-CAS WORK:	Passed
-CASX FAIL:	Passed
-CASX WORK:	Passed
-LDTX:		Passed
-LDTW:		Passed
-STTW:		Passed
-Done
-Exiting @ tick 22838500 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,617 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000027                       # Number of seconds simulated
-sim_ticks                                    27282000                       # Number of ticks simulated
-final_tick                                   27282000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  50184                       # Simulator instruction rate (inst/s)
-host_op_rate                                    50180                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               90285398                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 232468                       # Number of bytes of host memory used
-host_seconds                                     0.30                       # Real time elapsed on the host
-sim_insts                                       15162                       # Number of instructions simulated
-sim_ops                                         15162                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             19072                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                27904                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        19072                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           19072                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                298                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   436                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            699068983                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            323729932                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1022798915                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       699068983                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          699068983                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           699068983                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           323729932                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1022798915                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           436                       # Total number of read requests seen
-system.physmem.writeReqs                            0                       # Total number of write requests seen
-system.physmem.cpureqs                            436                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                        27904                       # Total number of bytes read from memory
-system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd                  27904                       # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                    97                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                    28                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                    38                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                    20                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                    16                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                    29                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                    32                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                     4                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                     1                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10                    1                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12                   48                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13                   31                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14                   58                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15                   33                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
-system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                        27248500                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                     436                       # Categorize read packet sizes
-system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::6                      0                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                       276                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       116                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        32                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        10                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           49                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      344.816327                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     179.016062                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     498.456939                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64                18     36.73%     36.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128                9     18.37%     55.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192                3      6.12%     61.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256                5     10.20%     71.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320                3      6.12%     77.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384                1      2.04%     79.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448                1      2.04%     81.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576                2      4.08%     85.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704                1      2.04%     87.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768                1      2.04%     89.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896                1      2.04%     91.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600               1      2.04%     93.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856               1      2.04%     95.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920               1      2.04%     97.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048               1      2.04%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             49                       # Bytes accessed per row activation
-system.physmem.totQLat                        1525500                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat                  10030500                       # Sum of mem lat for all requests
-system.physmem.totBusLat                      2180000                       # Total cycles spent in databus access
-system.physmem.totBankLat                     6325000                       # Total cycles spent in bank access
-system.physmem.avgQLat                        3498.85                       # Average queueing delay per request
-system.physmem.avgBankLat                    14506.88                       # Average bank access latency per request
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
-system.physmem.avgMemAccLat                  23005.73                       # Average memory access latency
-system.physmem.avgRdBW                        1022.80                       # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                1022.80                       # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil                           7.99                       # Data bus utilization in percentage
-system.physmem.avgRdQLen                         0.37                       # Average read queue length over time
-system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
-system.physmem.readRowHits                        387                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   88.76                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        62496.56                       # Average gap between requests
-system.membus.throughput                   1020453046                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 351                       # Transaction distribution
-system.membus.trans_dist::ReadResp                350                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                85                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               85                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side          871                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count                           871                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side        27840                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size                      27840                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                  27840                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              519000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4055250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             14.9                       # Layer utilization (%)
-system.cpu.branchPred.lookups                    5146                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              3529                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect              2366                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 4100                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                    2719                       # Number of BTB hits
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             66.317073                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     174                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                  5                       # Number of incorrect RAS predictions.
-system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            54565                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.predictedTaken         2893                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken         2253                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads        14397                       # Number of Reads from Int. Register File
-system.cpu.regfile_manager.intRegFileWrites        11099                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses        25496                       # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads            0                       # Number of Reads from FP Register File
-system.cpu.regfile_manager.floatRegFileWrites            0                       # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses            0                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards           5052                       # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens                       3844                       # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect         1541                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect          762                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted           2303                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted              1055                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct     68.582490                       # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions            11045                       # Number of Instructions Executed.
-system.cpu.mult_div_unit.multiplies                 0                       # Number of Multipy Operations Executed
-system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
-system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                         21826                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
-system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             430                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           36997                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                            17568                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         32.196463                       # Percentage of cycles cpu is active
-system.cpu.comLoads                              2225                       # Number of Load instructions committed
-system.cpu.comStores                             1448                       # Number of Store instructions committed
-system.cpu.comBranches                           3358                       # Number of Branches instructions committed
-system.cpu.comNops                                726                       # Number of Nop instructions committed
-system.cpu.comNonSpec                             222                       # Number of Non-Speculative instructions committed
-system.cpu.comInts                               7166                       # Number of Integer instructions committed
-system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                       15162                       # Number of Instructions committed (Per-Thread)
-system.cpu.committedOps                         15162                       # Number of Ops committed (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
-system.cpu.committedInsts_total                 15162                       # Number of Instructions committed (Total)
-system.cpu.cpi                               3.598800                       # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         3.598800                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.277870                       # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.277870                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                    41139                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                     13426                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               24.605516                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    45212                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                      9353                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization               17.141024                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    45762                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                      8803                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization               16.133052                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    51687                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                      2878                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                5.274443                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    45256                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                      9309                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               17.060387                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.icache.tags.replacements                      0                       # number of replacements
-system.cpu.icache.tags.tagsinuse                168.400745                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                     3004                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    299                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                  10.046823                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     168.400745                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.082227                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.082227                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         3004                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            3004                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          3004                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             3004                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         3004                       # number of overall hits
-system.cpu.icache.overall_hits::total            3004                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          381                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           381                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          381                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            381                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          381                       # number of overall misses
-system.cpu.icache.overall_misses::total           381                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     25440250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     25440250                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     25440250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     25440250                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     25440250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     25440250                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         3385                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         3385                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         3385                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         3385                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         3385                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         3385                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.112555                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.112555                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.112555                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.112555                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.112555                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.112555                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66772.309711                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 66772.309711                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 66772.309711                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 66772.309711                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 66772.309711                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 66772.309711                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           80                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           80                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           80                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           80                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           80                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           80                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          301                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          301                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          301                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          301                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          301                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          301                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     19991500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     19991500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     19991500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     19991500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     19991500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     19991500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.088922                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.088922                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.088922                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.088922                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.088922                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.088922                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66416.943522                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66416.943522                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66416.943522                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 66416.943522                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66416.943522                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 66416.943522                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput              1025144784                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq            354                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           352                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           85                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           85                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side          600                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side          276                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count                      876                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side        19136                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side         8832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size                 27968                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus             27968                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy         219500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        507000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        223250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               199.371038                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                       2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   350                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  0.005714                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    167.740493                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     31.630545                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005119                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.000965                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.006084                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
-system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          299                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          352                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data           85                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           85                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          299                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           437                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          299                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          437                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     19668000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3736000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     23404000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5885250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5885250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     19668000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      9621250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     29289250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     19668000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      9621250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     29289250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          301                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           53                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          354                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data           85                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           85                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          301                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          138                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          439                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          301                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          138                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          439                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993355                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.994350                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993355                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.995444                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993355                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.995444                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65779.264214                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70490.566038                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 66488.636364                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69238.235294                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69238.235294                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65779.264214                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69719.202899                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 67023.455378                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65779.264214                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69719.202899                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 67023.455378                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          299                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          352                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           85                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           85                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          299                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          437                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          299                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          437                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15937500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3076000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     19013500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4840750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4840750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     15937500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7916750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     23854250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     15937500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7916750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     23854250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993355                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.994350                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993355                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.995444                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993355                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.995444                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53302.675585                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58037.735849                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54015.625000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        56950                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        56950                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53302.675585                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57367.753623                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54586.384439                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53302.675585                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57367.753623                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54586.384439                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                 98.106033                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                     3193                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    138                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  23.137681                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data      98.106033                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.023952                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.023952                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         2167                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            2167                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data         1020                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total           1020                       # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data          3187                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             3187                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         3187                       # number of overall hits
-system.cpu.dcache.overall_hits::total            3187                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data           58                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total            58                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          422                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          422                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          480                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            480                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          480                       # number of overall misses
-system.cpu.dcache.overall_misses::total           480                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      4310500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4310500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     25385000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     25385000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     29695500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     29695500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     29695500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     29695500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         2225                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         2225                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         3667                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         3667                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         3667                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         3667                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.026067                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.026067                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.292649                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.292649                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.130897                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.130897                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.130897                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.130897                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74318.965517                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 74318.965517                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60154.028436                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60154.028436                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 61865.625000                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 61865.625000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 61865.625000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 61865.625000                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         1022                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                33                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    30.969697                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data            5                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          337                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          337                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          342                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          342                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          342                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          342                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           53                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           85                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           85                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3790500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      3790500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5973250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5973250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9763750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      9763750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9763750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      9763750                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.023820                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.023820                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.058946                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.058946                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037633                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.037633                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037633                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.037633                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71518.867925                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71518.867925                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70273.529412                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70273.529412                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70751.811594                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 70751.811594                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70751.811594                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 70751.811594                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +29,10 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +47,7 @@
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +96,7 @@
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +126,9 @@
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +136,11 @@
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +151,21 @@
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=SparcTLB
 size=64
@@ -422,10 +435,11 @@
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -436,12 +450,21 @@
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=SparcInterrupts
 
@@ -454,10 +477,11 @@
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -468,16 +492,25 @@
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -507,10 +540,14 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -521,19 +558,21 @@
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
-lines_per_rowbuffer=32
+lines_per_rowbuffer=128
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -544,6 +583,5 @@
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,2 +1,4 @@
-warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
+fatal: Can't load object file tests/test-progs/insttest/bin/sparc/linux/insttest
+ @ cycle 0
+[create:build/SPARC/sim/process.cc, line 613]
+Memory Usage: 242424 KBytes
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,23 +1,8 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:04:14
-gem5 started Mar 26 2013 15:04:37
-gem5 executing on ribera.cs.wisc.edu
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
+gem5 compiled Jul 17 2013 12:19:08
+gem5 started Jul 17 2013 12:19:20
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-Begining test of difficult SPARC instructions...
-LDSTUB:		Passed
-SWAP:		Passed
-CAS FAIL:	Passed
-CAS WORK:	Passed
-CASX FAIL:	Passed
-CASX WORK:	Passed
-LDTX:		Passed
-LDTW:		Passed
-STTW:		Passed
-Done
-Exiting @ tick 23775500 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,809 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000027                       # Number of seconds simulated
-sim_ticks                                    26524500                       # Number of ticks simulated
-final_tick                                   26524500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  52714                       # Simulator instruction rate (inst/s)
-host_op_rate                                    52709                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               96835127                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234512                       # Number of bytes of host memory used
-host_seconds                                     0.27                       # Real time elapsed on the host
-sim_insts                                       14436                       # Number of instructions simulated
-sim_ops                                         14436                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             21440                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              9408                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                30848                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        21440                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           21440                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                335                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                147                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   482                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            808309299                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            354690946                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1163000245                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       808309299                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          808309299                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           808309299                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           354690946                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1163000245                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           482                       # Total number of read requests seen
-system.physmem.writeReqs                            0                       # Total number of write requests seen
-system.physmem.cpureqs                            482                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                        30848                       # Total number of bytes read from memory
-system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd                  30848                       # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                   102                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                    29                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                    50                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                    24                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                    19                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                     0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                    32                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                    35                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                     4                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                     1                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10                    1                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11                    0                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12                   57                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13                   31                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14                   61                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15                   36                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
-system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                        26363500                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                     482                       # Categorize read packet sizes
-system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::6                      0                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                       287                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       134                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        50                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         7                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           52                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      361.846154                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     181.816034                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     531.077461                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64                20     38.46%     38.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128                7     13.46%     51.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192                5      9.62%     61.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256                5      9.62%     71.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320                3      5.77%     76.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384                2      3.85%     80.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512                1      1.92%     82.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640                1      1.92%     84.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768                1      1.92%     86.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832                1      1.92%     88.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960                2      3.85%     92.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856               2      3.85%     96.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112               1      1.92%     98.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176               1      1.92%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             52                       # Bytes accessed per row activation
-system.physmem.totQLat                        1755500                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat                  10930500                       # Sum of mem lat for all requests
-system.physmem.totBusLat                      2410000                       # Total cycles spent in databus access
-system.physmem.totBankLat                     6765000                       # Total cycles spent in bank access
-system.physmem.avgQLat                        3642.12                       # Average queueing delay per request
-system.physmem.avgBankLat                    14035.27                       # Average bank access latency per request
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
-system.physmem.avgMemAccLat                  22677.39                       # Average memory access latency
-system.physmem.avgRdBW                        1163.00                       # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                1163.00                       # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil                           9.09                       # Data bus utilization in percentage
-system.physmem.avgRdQLen                         0.41                       # Average read queue length over time
-system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
-system.physmem.readRowHits                        430                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.21                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        54696.06                       # Average gap between requests
-system.membus.throughput                   1163000245                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 399                       # Transaction distribution
-system.membus.trans_dist::ReadResp                399                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                83                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               83                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side          964                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count                           964                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side        30848                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size                      30848                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                  30848                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              608000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4504750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             17.0                       # Layer utilization (%)
-system.cpu.branchPred.lookups                    6716                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              4456                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect              1076                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 5022                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                    2432                       # Number of BTB hits
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             48.426922                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     444                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                168                       # Number of incorrect RAS predictions.
-system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            53050                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles              12402                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          31129                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        6716                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               2876                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          9133                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    3044                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   8789                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                    4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           999                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      5380                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   469                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              33199                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.937649                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.130205                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    24066     72.49%     72.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     4510     13.58%     86.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      474      1.43%     87.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      392      1.18%     88.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      680      2.05%     90.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      706      2.13%     92.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      235      0.71%     93.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      253      0.76%     94.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1883      5.67%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                33199                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.126598                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.586786                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    13000                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  9785                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      8344                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   198                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1872                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  29016                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                   1872                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    13643                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     503                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           8756                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      7952                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   473                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  26657                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents                      2                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   147                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               23951                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 49456                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            49456                       # Number of integer rename lookups
-system.cpu.rename.CommittedMaps                 13819                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    10132                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                691                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            694                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      2734                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 3529                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                2285                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                 4                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      22518                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 655                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     21122                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                97                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            7904                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         5498                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            180                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         33199                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.636224                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.261129                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               23956     72.16%     72.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                3556     10.71%     82.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                2322      6.99%     89.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1703      5.13%     94.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 887      2.67%     97.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 470      1.42%     99.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 240      0.72%     99.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  45      0.14%     99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  20      0.06%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           33199                       # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      46     31.29%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     26     17.69%     48.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    75     51.02%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 15651     74.10%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 3362     15.92%     90.02% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                2109      9.98%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  21122                       # Type of FU issued
-system.cpu.iq.rate                           0.398153                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         147                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006960                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              75687                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             31103                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        19522                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                   0                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                  0                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  21269                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                       0                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               29                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1304                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           26                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          837                       # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            28                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1872                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     359                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    19                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               24307                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               399                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  3529                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2285                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                655                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      3                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             26                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            264                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          946                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                 1210                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 20074                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  3202                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1048                       # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1134                       # number of nop insts executed
-system.cpu.iew.exec_refs                         5224                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     4239                       # Number of branches executed
-system.cpu.iew.exec_stores                       2022                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.378398                       # Inst execution rate
-system.cpu.iew.wb_sent                          19749                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         19522                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      9120                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     11235                       # num instructions consuming a value
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.367992                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.811749                       # average fanout of values written-back
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            9047                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls             475                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts              1076                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        31327                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.483991                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.181452                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        24007     76.63%     76.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         4072     13.00%     89.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1361      4.34%     93.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          763      2.44%     96.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          348      1.11%     97.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          270      0.86%     98.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          322      1.03%     99.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           67      0.21%     99.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          117      0.37%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        31327                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts                15162                       # Number of instructions committed
-system.cpu.commit.committedOps                  15162                       # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                           3673                       # Number of memory references committed
-system.cpu.commit.loads                          2225                       # Number of loads committed
-system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.branches                       3358                       # Number of branches committed
-system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                     12174                       # Number of committed integer instructions.
-system.cpu.commit.function_calls                  187                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                   117                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        54596                       # The number of ROB reads
-system.cpu.rob.rob_writes                       50298                       # The number of ROB writes
-system.cpu.timesIdled                             214                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           19851                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                       14436                       # Number of Instructions Simulated
-system.cpu.committedOps                         14436                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total                 14436                       # Number of Instructions Simulated
-system.cpu.cpi                               3.674841                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.674841                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.272121                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.272121                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    32043                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   17841                       # number of integer regfile writes
-system.cpu.misc_regfile_reads                    6919                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                    569                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1167825972                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq            401                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           401                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           83                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           83                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side          674                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side          294                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count                      968                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side        21568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side         9408                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size                 30976                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus             30976                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy         242000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        570000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        235750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                      0                       # number of replacements
-system.cpu.icache.tags.tagsinuse                187.665560                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                     4873                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    337                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                  14.459941                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     187.665560                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.091634                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.091634                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         4873                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            4873                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          4873                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             4873                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         4873                       # number of overall hits
-system.cpu.icache.overall_hits::total            4873                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          507                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           507                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          507                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            507                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          507                       # number of overall misses
-system.cpu.icache.overall_misses::total           507                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     31160500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     31160500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     31160500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     31160500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     31160500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     31160500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         5380                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         5380                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         5380                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         5380                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         5380                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         5380                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.094238                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.094238                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.094238                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.094238                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.094238                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.094238                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61460.552268                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 61460.552268                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 61460.552268                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 61460.552268                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 61460.552268                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 61460.552268                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          170                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          170                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          170                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          170                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          170                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          170                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          337                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          337                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          337                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          337                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          337                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          337                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22334500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     22334500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22334500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     22334500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22334500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     22334500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.062639                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.062639                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.062639                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.062639                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.062639                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.062639                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66274.480712                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66274.480712                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66274.480712                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 66274.480712                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66274.480712                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 66274.480712                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               221.542392                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                       2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   399                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  0.005013                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    187.054257                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     34.488135                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005708                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001052                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.006761                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
-system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          335                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           64                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          399                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data           83                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           83                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          335                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          147                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           482                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          335                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          147                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          482                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     21977500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4600000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     26577500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5717750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5717750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     21977500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     10317750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     32295250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     21977500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     10317750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     32295250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          337                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           64                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          401                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data           83                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           83                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          337                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          147                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          484                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          337                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          147                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          484                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.994065                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.995012                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.994065                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.995868                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.994065                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.995868                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65604.477612                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        71875                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 66610.275689                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68888.554217                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68888.554217                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65604.477612                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70188.775510                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 67002.593361                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65604.477612                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70188.775510                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 67002.593361                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          335                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           64                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          399                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           83                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           83                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          335                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          147                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          482                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          335                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          482                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     17752000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3813000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     21565000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4699750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4699750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     17752000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8512750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     26264750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     17752000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8512750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     26264750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.994065                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995012                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.994065                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.995868                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.994065                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.995868                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52991.044776                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59578.125000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54047.619048                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56623.493976                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56623.493976                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52991.044776                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57909.863946                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54491.182573                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52991.044776                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.863946                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54491.182573                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                 98.809715                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                     4001                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    147                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  27.217687                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data      98.809715                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.024123                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.024123                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         2962                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            2962                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data         1033                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total           1033                       # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data          3995                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             3995                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         3995                       # number of overall hits
-system.cpu.dcache.overall_hits::total            3995                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          126                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           126                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          409                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          409                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          535                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            535                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          535                       # number of overall misses
-system.cpu.dcache.overall_misses::total           535                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7983250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7983250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     24700974                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     24700974                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     32684224                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     32684224                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     32684224                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     32684224                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         3088                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         3088                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         4530                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         4530                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         4530                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         4530                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040803                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040803                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.283634                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.283634                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.118102                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.118102                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.118102                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.118102                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63359.126984                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63359.126984                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60393.579462                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60393.579462                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 61092.007477                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 61092.007477                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 61092.007477                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 61092.007477                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          729                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                28                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    26.035714                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           62                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           62                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          326                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          326                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          388                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          388                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          388                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          388                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           64                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           64                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           83                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           83                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          147                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          147                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          147                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4664500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4664500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5801750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5801750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10466250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10466250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10466250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10466250                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.020725                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.020725                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.057559                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.057559                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.032450                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.032450                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032450                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.032450                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72882.812500                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72882.812500                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69900.602410                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69900.602410                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71198.979592                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 71198.979592                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71198.979592                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 71198.979592                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +29,16 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +57,10 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -99,11 +107,16 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -112,13 +125,12 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,3 +1,4 @@
-warn: CoherentBus system.membus has no snooping ports attached!
-warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
+fatal: Can't load object file tests/test-progs/insttest/bin/sparc/linux/insttest
+ @ cycle 0
+[create:build/SPARC/sim/process.cc, line 613]
+Memory Usage: 241900 KBytes
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,23 +1,8 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 15:49:34
-gem5 executing on ribera.cs.wisc.edu
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic
+gem5 compiled Jul 17 2013 12:19:08
+gem5 started Jul 17 2013 12:19:19
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-Begining test of difficult SPARC instructions...
-LDSTUB:		Passed
-SWAP:		Passed
-CAS FAIL:	Passed
-CAS WORK:	Passed
-CASX FAIL:	Passed
-CASX WORK:	Passed
-LDTX:		Passed
-LDTW:		Passed
-STTW:		Passed
-Done
-Exiting @ tick 7612000 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,65 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000008                       # Number of seconds simulated
-sim_ticks                                     7612000                       # Number of ticks simulated
-final_tick                                    7612000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 451796                       # Simulator instruction rate (inst/s)
-host_op_rate                                   451441                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              226479305                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222832                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
-sim_insts                                       15162                       # Number of instructions simulated
-sim_ops                                         15162                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             60828                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             11342                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                72170                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        60828                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           60828                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data           9042                       # Number of bytes written to this memory
-system.physmem.bytes_written::total              9042                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              15207                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               2225                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 17432                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data              1442                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                 1442                       # Number of write requests responded to by this memory
-system.physmem.num_other::cpu.data                  6                       # Number of other requests responded to by this memory
-system.physmem.num_other::total                     6                       # Number of other requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7991066737                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1490015765                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              9481082501                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7991066737                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7991066737                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1187861272                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1187861272                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7991066737                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2677877036                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            10668943773                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                  10676563321                       # Throughput (bytes/s)
-system.membus.data_through_bus                  81270                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            15225                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                       15162                       # Number of instructions committed
-system.cpu.committedOps                         15162                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                 12219                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                         385                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts         2434                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                        12219                       # number of integer instructions
-system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads               29037                       # number of times the integer registers were read
-system.cpu.num_int_register_writes              13819                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          3683                       # number of memory refs
-system.cpu.num_load_insts                        2231                       # Number of load instructions
-system.cpu.num_store_insts                       1452                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      15225                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +29,16 @@
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +56,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +66,11 @@
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,32 @@
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +117,21 @@
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=SparcInterrupts
 
@@ -119,10 +144,11 @@
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -133,17 +159,27 @@
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -171,11 +207,16 @@
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -184,13 +225,12 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,2 +1,4 @@
-warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
+fatal: Can't load object file tests/test-progs/insttest/bin/sparc/linux/insttest
+ @ cycle 0
+[create:build/SPARC/sim/process.cc, line 613]
+Memory Usage: 241900 KBytes
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,23 +1,8 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 15:49:45
-gem5 executing on ribera.cs.wisc.edu
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing
+gem5 compiled Jul 17 2013 12:19:08
+gem5 started Jul 17 2013 12:19:19
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-Begining test of difficult SPARC instructions...
-LDSTUB:		Passed
-SWAP:		Passed
-CAS FAIL:	Passed
-CAS WORK:	Passed
-CASX FAIL:	Passed
-CASX WORK:	Passed
-LDTX:		Passed
-LDTW:		Passed
-STTW:		Passed
-Done
-Exiting @ tick 41368000 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,393 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000041                       # Number of seconds simulated
-sim_ticks                                    41368000                       # Number of ticks simulated
-final_tick                                   41368000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 479032                       # Simulator instruction rate (inst/s)
-host_op_rate                                   478642                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1304958787                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 231320                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
-sim_insts                                       15162                       # Number of instructions simulated
-sim_ops                                         15162                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             17792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                26624                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        17792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           17792                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                278                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   416                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            430090892                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            213498356                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               643589248                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       430090892                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          430090892                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           430090892                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           213498356                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              643589248                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                    643589248                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 331                       # Transaction distribution
-system.membus.trans_dist::ReadResp                331                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                85                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               85                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side          832                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count                           832                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side        26624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size                      26624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                  26624                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              416000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3744000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              9.1                       # Layer utilization (%)
-system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            82736                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                       15162                       # Number of instructions committed
-system.cpu.committedOps                         15162                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                 12219                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                         385                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts         2434                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                        12219                       # number of integer instructions
-system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads               29037                       # number of times the integer registers were read
-system.cpu.num_int_register_writes              13818                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          3683                       # number of memory refs
-system.cpu.num_load_insts                        2231                       # Number of load instructions
-system.cpu.num_store_insts                       1452                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      82736                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.icache.tags.replacements                      0                       # number of replacements
-system.cpu.icache.tags.tagsinuse                153.782734                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                    14928                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    280                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                  53.314286                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     153.782734                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.075089                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.075089                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst        14928                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total           14928                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst         14928                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total            14928                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst        14928                       # number of overall hits
-system.cpu.icache.overall_hits::total           14928                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          280                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           280                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          280                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            280                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          280                       # number of overall misses
-system.cpu.icache.overall_misses::total           280                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     15316000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     15316000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     15316000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     15316000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     15316000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     15316000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst        15208                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total        15208                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst        15208                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total        15208                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst        15208                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total        15208                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.018411                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.018411                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.018411                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.018411                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.018411                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.018411                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        54700                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total        54700                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst        54700                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total        54700                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst        54700                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total        54700                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          280                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          280                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          280                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          280                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          280                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          280                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     14756000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     14756000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14756000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     14756000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14756000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     14756000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.018411                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.018411                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.018411                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.018411                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.018411                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.018411                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        52700                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total        52700                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        52700                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total        52700                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        52700                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total        52700                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               184.632038                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                       2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   331                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  0.006042                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    153.110886                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     31.521152                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004673                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.000962                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.005635                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
-system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          278                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          331                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data           85                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           85                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          278                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           416                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          278                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          416                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     14456000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2756000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     17212000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4420000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      4420000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     14456000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      7176000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     21632000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     14456000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      7176000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     21632000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          280                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           53                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          333                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data           85                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           85                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          280                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          138                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          418                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          280                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          138                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          418                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.992857                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.993994                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.992857                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.995215                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.992857                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.995215                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          278                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          331                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           85                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           85                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          278                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          416                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          278                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          416                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11120000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2120000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     13240000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3400000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3400000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11120000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5520000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     16640000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11120000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5520000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     16640000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.992857                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.993994                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.992857                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.995215                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.992857                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.995215                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                 97.994344                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                     3535                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    138                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  25.615942                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data      97.994344                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.023924                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.023924                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         2172                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            2172                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data         1357                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total           1357                       # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data          3529                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             3529                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         3529                       # number of overall hits
-system.cpu.dcache.overall_hits::total            3529                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total            53                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data           85                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total           85                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            138                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          138                       # number of overall misses
-system.cpu.dcache.overall_misses::total           138                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      2915000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      2915000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      4675000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      4675000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data      7590000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      7590000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data      7590000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      7590000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         2225                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         2225                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         3667                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         3667                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         3667                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         3667                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.023820                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.023820                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.058946                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.058946                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037633                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037633                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.037633                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037633                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        55000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total        55000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        55000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        55000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data        55000                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total        55000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data        55000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total        55000                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           53                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           85                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           85                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2809000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      2809000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4505000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4505000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7314000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      7314000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7314000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      7314000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.023820                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.023820                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.058946                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.058946                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037633                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.037633                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037633                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.037633                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               646683427                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq            333                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           333                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           85                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           85                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side          560                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side          276                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count                      836                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side        17920                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side         8832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size                 26752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus             26752                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy         209000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        420000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        207000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,7 +0,0 @@
-warn: CoherentBus system.membus has no snooping ports attached!
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here
-
-gzip: stdout: Broken pipe
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  8 2013 10:00:13
-gem5 started Jun  8 2013 10:00:28
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-main dictionary has 1245 entries
-49508 bytes wasted
->Exiting @ tick 250015500 because a thread reached the max instruction count
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/se/20.eio-short/alpha/eio/simple-atomic
+Skipping test: Test requires the 'EioProcess' SimObject.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,95 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000250                       # Number of seconds simulated
-sim_ticks                                   250015500                       # Number of ticks simulated
-final_tick                                  250015500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2804892                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2804630                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1402273759                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217844                       # Number of bytes of host memory used
-host_seconds                                     0.18                       # Real time elapsed on the host
-sim_insts                                      500001                       # Number of instructions simulated
-sim_ops                                        500001                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst           2000076                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            872600                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              2872676                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      2000076                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         2000076                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data         417562                       # Number of bytes written to this memory
-system.physmem.bytes_written::total            417562                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst             500019                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             124435                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                624454                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data             56340                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                56340                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7999808012                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           3490183609                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             11489991621                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7999808012                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7999808012                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1670144451                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1670144451                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7999808012                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          5160328060                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            13160136072                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                  13160136072                       # Throughput (bytes/s)
-system.membus.data_through_bus                3290238                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                       124435                       # DTB read hits
-system.cpu.dtb.read_misses                          8                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                   124443                       # DTB read accesses
-system.cpu.dtb.write_hits                       56340                       # DTB write hits
-system.cpu.dtb.write_misses                        10                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                   56350                       # DTB write accesses
-system.cpu.dtb.data_hits                       180775                       # DTB hits
-system.cpu.dtb.data_misses                         18                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                   180793                       # DTB accesses
-system.cpu.itb.fetch_hits                      500019                       # ITB hits
-system.cpu.itb.fetch_misses                        13                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                  500032                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                           500032                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                      500001                       # Number of instructions committed
-system.cpu.committedOps                        500001                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                474689                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     32                       # Number of float alu accesses
-system.cpu.num_func_calls                       14357                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                       474689                       # number of integer instructions
-system.cpu.num_fp_insts                            32                       # number of float instructions
-system.cpu.num_int_register_reads              654286                       # number of times the integer registers were read
-system.cpu.num_int_register_writes             371542                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                   32                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
-system.cpu.num_mem_refs                        180793                       # number of memory refs
-system.cpu.num_load_insts                      124443                       # Number of load instructions
-system.cpu.num_store_insts                      56350                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     500032                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,6 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here
-
-gzip: stdout: Broken pipe
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  8 2013 10:00:13
-gem5 started Jun  8 2013 10:00:28
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-main dictionary has 1245 entries
-49508 bytes wasted
->Exiting @ tick 727072000 because a thread reached the max instruction count
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/20.eio-short/alpha/eio/simple-timing
+Skipping test: Test requires the 'EioProcess' SimObject.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,415 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000727                       # Number of seconds simulated
-sim_ticks                                   727072000                       # Number of ticks simulated
-final_tick                                  727072000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1476552                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1476467                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2146892777                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226332                       # Number of bytes of host memory used
-host_seconds                                     0.34                       # Real time elapsed on the host
-sim_insts                                      500001                       # Number of instructions simulated
-sim_ops                                        500001                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             25792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             29056                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                54848                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           25792                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   857                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst             35473791                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             39963030                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                75436821                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        35473791                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           35473791                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            35473791                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            39963030                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               75436821                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     75436821                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 718                       # Transaction distribution
-system.membus.trans_dist::ReadResp                718                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               139                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              139                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side         1714                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count                          1714                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side        54848                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size                      54848                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                  54848                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              857000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            7713000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                       124435                       # DTB read hits
-system.cpu.dtb.read_misses                          8                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                   124443                       # DTB read accesses
-system.cpu.dtb.write_hits                       56340                       # DTB write hits
-system.cpu.dtb.write_misses                        10                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                   56350                       # DTB write accesses
-system.cpu.dtb.data_hits                       180775                       # DTB hits
-system.cpu.dtb.data_misses                         18                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                   180793                       # DTB accesses
-system.cpu.itb.fetch_hits                      500020                       # ITB hits
-system.cpu.itb.fetch_misses                        13                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                  500033                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                          1454144                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                      500001                       # Number of instructions committed
-system.cpu.committedOps                        500001                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                474689                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     32                       # Number of float alu accesses
-system.cpu.num_func_calls                       14357                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                       474689                       # number of integer instructions
-system.cpu.num_fp_insts                            32                       # number of float instructions
-system.cpu.num_int_register_reads              654286                       # number of times the integer registers were read
-system.cpu.num_int_register_writes             371542                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                   32                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
-system.cpu.num_mem_refs                        180793                       # number of memory refs
-system.cpu.num_load_insts                      124443                       # Number of load instructions
-system.cpu.num_store_insts                      56350                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                    1454144                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.icache.tags.replacements                      0                       # number of replacements
-system.cpu.icache.tags.tagsinuse                265.013024                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                   499617                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    403                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                1239.744417                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     265.013024                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.129401                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.129401                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst       499617                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total          499617                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst        499617                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total           499617                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst       499617                       # number of overall hits
-system.cpu.icache.overall_hits::total          499617                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          403                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           403                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          403                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            403                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          403                       # number of overall misses
-system.cpu.icache.overall_misses::total           403                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     22165000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     22165000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     22165000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     22165000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     22165000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     22165000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst       500020                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total       500020                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst       500020                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total       500020                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst       500020                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total       500020                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000806                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000806                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000806                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000806                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000806                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000806                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        55000                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total        55000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst        55000                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total        55000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst        55000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total        55000                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          403                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          403                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          403                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          403                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          403                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          403                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     21359000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     21359000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     21359000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     21359000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     21359000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     21359000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000806                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000806                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000806                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000806                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000806                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000806                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               481.542013                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                       0                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   718                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                         0                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    265.019675                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    216.522338                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.008088                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.006608                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.014695                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_misses::cpu.inst          403                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          315                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          718                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data          139                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total          139                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          403                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          454                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           857                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          403                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          454                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          857                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     20956000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     16380000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     37336000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      7228000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      7228000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     20956000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     23608000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     44564000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     20956000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     23608000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     44564000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          403                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          315                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          718                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data          139                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total          139                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          403                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          454                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          857                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          403                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          454                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          857                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total            1                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          403                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          315                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          718                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          139                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          139                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          403                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          454                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          857                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          403                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          454                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          857                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16120000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     12600000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     28720000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5560000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5560000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16120000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     18160000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     34280000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16120000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     18160000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     34280000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                287.259400                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                   180321                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    454                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                 397.182819                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data     287.259400                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.070132                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.070132                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data       124120                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total          124120                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data        56201                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total          56201                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data        180321                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total           180321                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data       180321                       # number of overall hits
-system.cpu.dcache.overall_hits::total          180321                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          315                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           315                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          139                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          454                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            454                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          454                       # number of overall misses
-system.cpu.dcache.overall_misses::total           454                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     17325000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     17325000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      7645000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      7645000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     24970000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     24970000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     24970000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     24970000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data       180775                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data       180775                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002531                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002531                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.002511                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002511                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.002511                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002511                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        55000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total        55000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        55000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        55000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data        55000                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total        55000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data        55000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total        55000                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          315                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          315                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data          139                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          454                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          454                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          454                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          454                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     16695000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     16695000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      7367000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      7367000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     24062000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     24062000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     24062000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     24062000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002531                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002531                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002511                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002511                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002511                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002511                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                75436821                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq            718                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           718                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq          139                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp          139                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side          806                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side          908                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count                     1714                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side        25792                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side        29056                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size                 54848                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus             54848                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy         428500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        604500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        681000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,8 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,18 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  8 2013 10:00:13
-gem5 started Jun  8 2013 10:00:28
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
->>>>Exiting @ tick 250015500 because a thread reached the max instruction count
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA/tests/fast/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
+Skipping test: Test requires the 'EioProcess' SimObject.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,824 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000250                       # Number of seconds simulated
-sim_ticks                                   250015500                       # Number of ticks simulated
-final_tick                                  250015500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3032804                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3032728                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              379104441                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1154504                       # Number of bytes of host memory used
-host_seconds                                     0.66                       # Real time elapsed on the host
-sim_insts                                     2000004                       # Number of instructions simulated
-sim_ops                                       2000004                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst            25792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data            29056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            25792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data            29056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst            25792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data            29056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst            25792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data            29056                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               219392                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst        25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst        25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst        25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          103168                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst               403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data               454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst               403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data               454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst               403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data               454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst               403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data               454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  3428                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst           103161604                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data           116216795                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst           103161604                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data           116216795                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst           103161604                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data           116216795                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst           103161604                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data           116216795                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               877513594                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      103161604                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst      103161604                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst      103161604                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst      103161604                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          412646416                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          103161604                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data          116216795                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst          103161604                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data          116216795                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst          103161604                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data          116216795                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst          103161604                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data          116216795                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              877513594                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                    877513594                       # Throughput (bytes/s)
-system.membus.data_through_bus                 219392                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.toL2Bus.throughput                   977859373                       # Throughput (bytes/s)
-system.toL2Bus.data_through_bus                244480                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus               0                       # Total snoop data (bytes)
-system.cpu0.dtb.fetch_hits                          0                       # ITB hits
-system.cpu0.dtb.fetch_misses                        0                       # ITB misses
-system.cpu0.dtb.fetch_acv                           0                       # ITB acv
-system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                      124435                       # DTB read hits
-system.cpu0.dtb.read_misses                         8                       # DTB read misses
-system.cpu0.dtb.read_acv                            0                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu0.dtb.write_hits                      56340                       # DTB write hits
-system.cpu0.dtb.write_misses                       10                       # DTB write misses
-system.cpu0.dtb.write_acv                           0                       # DTB write access violations
-system.cpu0.dtb.write_accesses                  56350                       # DTB write accesses
-system.cpu0.dtb.data_hits                      180775                       # DTB hits
-system.cpu0.dtb.data_misses                        18                       # DTB misses
-system.cpu0.dtb.data_acv                            0                       # DTB access violations
-system.cpu0.dtb.data_accesses                  180793                       # DTB accesses
-system.cpu0.itb.fetch_hits                     500019                       # ITB hits
-system.cpu0.itb.fetch_misses                       13                       # ITB misses
-system.cpu0.itb.fetch_acv                           0                       # ITB acv
-system.cpu0.itb.fetch_accesses                 500032                       # ITB accesses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.read_acv                            0                       # DTB read access violations
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.write_acv                           0                       # DTB write access violations
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.data_hits                           0                       # DTB hits
-system.cpu0.itb.data_misses                         0                       # DTB misses
-system.cpu0.itb.data_acv                            0                       # DTB access violations
-system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.workload.num_syscalls                  18                       # Number of system calls
-system.cpu0.numCycles                          500032                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                     500001                       # Number of instructions committed
-system.cpu0.committedOps                       500001                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu0.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                      474689                       # number of integer instructions
-system.cpu0.num_fp_insts                           32                       # number of float instructions
-system.cpu0.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                       180793                       # number of memory refs
-system.cpu0.num_load_insts                     124443                       # Number of load instructions
-system.cpu0.num_store_insts                     56350                       # Number of store instructions
-system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu0.num_busy_cycles                    500032                       # Number of busy cycles
-system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu0.icache.tags.replacements                   152                       # number of replacements
-system.cpu0.icache.tags.tagsinuse               218.086151                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs                  499556                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs               1078.954644                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   218.086151                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.425950                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total        0.425950                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst       499556                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst       499556                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total          499556                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst       499556                       # number of overall hits
-system.cpu0.icache.overall_hits::total         499556                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          463                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          463                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          463                       # number of overall misses
-system.cpu0.icache.overall_misses::total          463                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst       500019                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total       500019                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst       500019                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total       500019                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.000926                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.000926                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements                    61                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse               276.872320                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs                  180312                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs                389.442765                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   276.872320                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.540766                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total        0.540766                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data       124111                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        56201                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
-system.cpu0.dcache.demand_hits::cpu0.data       180312                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data       180312                       # number of overall hits
-system.cpu0.dcache.overall_hits::total         180312                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          324                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data          139                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu0.dcache.demand_misses::cpu0.data          463                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data          463                       # number of overall misses
-system.cpu0.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data       180775                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data       180775                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.002561                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.002561                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu0.dcache.writebacks::total               29                       # number of writebacks
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dtb.fetch_hits                          0                       # ITB hits
-system.cpu1.dtb.fetch_misses                        0                       # ITB misses
-system.cpu1.dtb.fetch_acv                           0                       # ITB acv
-system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                      124435                       # DTB read hits
-system.cpu1.dtb.read_misses                         8                       # DTB read misses
-system.cpu1.dtb.read_acv                            0                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu1.dtb.write_hits                      56340                       # DTB write hits
-system.cpu1.dtb.write_misses                       10                       # DTB write misses
-system.cpu1.dtb.write_acv                           0                       # DTB write access violations
-system.cpu1.dtb.write_accesses                  56350                       # DTB write accesses
-system.cpu1.dtb.data_hits                      180775                       # DTB hits
-system.cpu1.dtb.data_misses                        18                       # DTB misses
-system.cpu1.dtb.data_acv                            0                       # DTB access violations
-system.cpu1.dtb.data_accesses                  180793                       # DTB accesses
-system.cpu1.itb.fetch_hits                     500019                       # ITB hits
-system.cpu1.itb.fetch_misses                       13                       # ITB misses
-system.cpu1.itb.fetch_acv                           0                       # ITB acv
-system.cpu1.itb.fetch_accesses                 500032                       # ITB accesses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.read_acv                            0                       # DTB read access violations
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.write_acv                           0                       # DTB write access violations
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.data_hits                           0                       # DTB hits
-system.cpu1.itb.data_misses                         0                       # DTB misses
-system.cpu1.itb.data_acv                            0                       # DTB access violations
-system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.workload.num_syscalls                  18                       # Number of system calls
-system.cpu1.numCycles                          500032                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                     500001                       # Number of instructions committed
-system.cpu1.committedOps                       500001                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu1.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                      474689                       # number of integer instructions
-system.cpu1.num_fp_insts                           32                       # number of float instructions
-system.cpu1.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                       180793                       # number of memory refs
-system.cpu1.num_load_insts                     124443                       # Number of load instructions
-system.cpu1.num_store_insts                     56350                       # Number of store instructions
-system.cpu1.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu1.num_busy_cycles                    500032                       # Number of busy cycles
-system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu1.icache.tags.replacements                   152                       # number of replacements
-system.cpu1.icache.tags.tagsinuse               218.086151                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs                  499556                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs               1078.954644                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   218.086151                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.425950                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total        0.425950                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst       499556                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst       499556                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total          499556                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst       499556                       # number of overall hits
-system.cpu1.icache.overall_hits::total         499556                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          463                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          463                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          463                       # number of overall misses
-system.cpu1.icache.overall_misses::total          463                       # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst       500019                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total       500019                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst       500019                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total       500019                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.000926                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.000926                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements                    61                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse               276.872320                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs                  180312                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs                389.442765                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   276.872320                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.540766                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total        0.540766                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data       124111                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        56201                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
-system.cpu1.dcache.demand_hits::cpu1.data       180312                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data       180312                       # number of overall hits
-system.cpu1.dcache.overall_hits::total         180312                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          324                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          139                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          463                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          463                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data       180775                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data       180775                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.002561                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.002561                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu1.dcache.writebacks::total               29                       # number of writebacks
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dtb.fetch_hits                          0                       # ITB hits
-system.cpu2.dtb.fetch_misses                        0                       # ITB misses
-system.cpu2.dtb.fetch_acv                           0                       # ITB acv
-system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu2.dtb.read_hits                      124435                       # DTB read hits
-system.cpu2.dtb.read_misses                         8                       # DTB read misses
-system.cpu2.dtb.read_acv                            0                       # DTB read access violations
-system.cpu2.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu2.dtb.write_hits                      56340                       # DTB write hits
-system.cpu2.dtb.write_misses                       10                       # DTB write misses
-system.cpu2.dtb.write_acv                           0                       # DTB write access violations
-system.cpu2.dtb.write_accesses                  56350                       # DTB write accesses
-system.cpu2.dtb.data_hits                      180775                       # DTB hits
-system.cpu2.dtb.data_misses                        18                       # DTB misses
-system.cpu2.dtb.data_acv                            0                       # DTB access violations
-system.cpu2.dtb.data_accesses                  180793                       # DTB accesses
-system.cpu2.itb.fetch_hits                     500019                       # ITB hits
-system.cpu2.itb.fetch_misses                       13                       # ITB misses
-system.cpu2.itb.fetch_acv                           0                       # ITB acv
-system.cpu2.itb.fetch_accesses                 500032                       # ITB accesses
-system.cpu2.itb.read_hits                           0                       # DTB read hits
-system.cpu2.itb.read_misses                         0                       # DTB read misses
-system.cpu2.itb.read_acv                            0                       # DTB read access violations
-system.cpu2.itb.read_accesses                       0                       # DTB read accesses
-system.cpu2.itb.write_hits                          0                       # DTB write hits
-system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.write_acv                           0                       # DTB write access violations
-system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.data_hits                           0                       # DTB hits
-system.cpu2.itb.data_misses                         0                       # DTB misses
-system.cpu2.itb.data_acv                            0                       # DTB access violations
-system.cpu2.itb.data_accesses                       0                       # DTB accesses
-system.cpu2.workload.num_syscalls                  18                       # Number of system calls
-system.cpu2.numCycles                          500032                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                     500001                       # Number of instructions committed
-system.cpu2.committedOps                       500001                       # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu2.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu2.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu2.num_int_insts                      474689                       # number of integer instructions
-system.cpu2.num_fp_insts                           32                       # number of float instructions
-system.cpu2.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu2.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu2.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu2.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu2.num_mem_refs                       180793                       # number of memory refs
-system.cpu2.num_load_insts                     124443                       # Number of load instructions
-system.cpu2.num_store_insts                     56350                       # Number of store instructions
-system.cpu2.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu2.num_busy_cycles                    500032                       # Number of busy cycles
-system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu2.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu2.icache.tags.replacements                   152                       # number of replacements
-system.cpu2.icache.tags.tagsinuse               218.086151                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs                  499556                       # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs               1078.954644                       # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst   218.086151                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.425950                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total        0.425950                       # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits::cpu2.inst       499556                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst       499556                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total          499556                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst       499556                       # number of overall hits
-system.cpu2.icache.overall_hits::total         499556                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          463                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          463                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          463                       # number of overall misses
-system.cpu2.icache.overall_misses::total          463                       # number of overall misses
-system.cpu2.icache.ReadReq_accesses::cpu2.inst       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst       500019                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total       500019                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst       500019                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total       500019                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.000926                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.000926                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
-system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dcache.tags.replacements                    61                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse               276.872320                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs                  180312                       # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs                389.442765                       # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data   276.872320                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.540766                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total        0.540766                       # Average percentage of cache occupancy
-system.cpu2.dcache.ReadReq_hits::cpu2.data       124111                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        56201                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
-system.cpu2.dcache.demand_hits::cpu2.data       180312                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data       180312                       # number of overall hits
-system.cpu2.dcache.overall_hits::total         180312                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          324                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          139                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          463                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          463                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu2.dcache.ReadReq_accesses::cpu2.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data       180775                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data       180775                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.002561                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.002561                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu2.dcache.writebacks::total               29                       # number of writebacks
-system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dtb.fetch_hits                          0                       # ITB hits
-system.cpu3.dtb.fetch_misses                        0                       # ITB misses
-system.cpu3.dtb.fetch_acv                           0                       # ITB acv
-system.cpu3.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu3.dtb.read_hits                      124435                       # DTB read hits
-system.cpu3.dtb.read_misses                         8                       # DTB read misses
-system.cpu3.dtb.read_acv                            0                       # DTB read access violations
-system.cpu3.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu3.dtb.write_hits                      56340                       # DTB write hits
-system.cpu3.dtb.write_misses                       10                       # DTB write misses
-system.cpu3.dtb.write_acv                           0                       # DTB write access violations
-system.cpu3.dtb.write_accesses                  56350                       # DTB write accesses
-system.cpu3.dtb.data_hits                      180775                       # DTB hits
-system.cpu3.dtb.data_misses                        18                       # DTB misses
-system.cpu3.dtb.data_acv                            0                       # DTB access violations
-system.cpu3.dtb.data_accesses                  180793                       # DTB accesses
-system.cpu3.itb.fetch_hits                     500019                       # ITB hits
-system.cpu3.itb.fetch_misses                       13                       # ITB misses
-system.cpu3.itb.fetch_acv                           0                       # ITB acv
-system.cpu3.itb.fetch_accesses                 500032                       # ITB accesses
-system.cpu3.itb.read_hits                           0                       # DTB read hits
-system.cpu3.itb.read_misses                         0                       # DTB read misses
-system.cpu3.itb.read_acv                            0                       # DTB read access violations
-system.cpu3.itb.read_accesses                       0                       # DTB read accesses
-system.cpu3.itb.write_hits                          0                       # DTB write hits
-system.cpu3.itb.write_misses                        0                       # DTB write misses
-system.cpu3.itb.write_acv                           0                       # DTB write access violations
-system.cpu3.itb.write_accesses                      0                       # DTB write accesses
-system.cpu3.itb.data_hits                           0                       # DTB hits
-system.cpu3.itb.data_misses                         0                       # DTB misses
-system.cpu3.itb.data_acv                            0                       # DTB access violations
-system.cpu3.itb.data_accesses                       0                       # DTB accesses
-system.cpu3.workload.num_syscalls                  18                       # Number of system calls
-system.cpu3.numCycles                          500032                       # number of cpu cycles simulated
-system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.committedInsts                     500001                       # Number of instructions committed
-system.cpu3.committedOps                       500001                       # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu3.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu3.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu3.num_int_insts                      474689                       # number of integer instructions
-system.cpu3.num_fp_insts                           32                       # number of float instructions
-system.cpu3.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu3.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu3.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu3.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu3.num_mem_refs                       180793                       # number of memory refs
-system.cpu3.num_load_insts                     124443                       # Number of load instructions
-system.cpu3.num_store_insts                     56350                       # Number of store instructions
-system.cpu3.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu3.num_busy_cycles                    500032                       # Number of busy cycles
-system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu3.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu3.icache.tags.replacements                   152                       # number of replacements
-system.cpu3.icache.tags.tagsinuse               218.086151                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs                  499556                       # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs               1078.954644                       # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst   218.086151                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.425950                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total        0.425950                       # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits::cpu3.inst       499556                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst       499556                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total          499556                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst       499556                       # number of overall hits
-system.cpu3.icache.overall_hits::total         499556                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          463                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          463                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          463                       # number of overall misses
-system.cpu3.icache.overall_misses::total          463                       # number of overall misses
-system.cpu3.icache.ReadReq_accesses::cpu3.inst       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst       500019                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total       500019                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst       500019                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total       500019                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.000926                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.000926                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
-system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dcache.tags.replacements                    61                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse               276.872320                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs                  180312                       # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs                389.442765                       # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data   276.872320                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.540766                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total        0.540766                       # Average percentage of cache occupancy
-system.cpu3.dcache.ReadReq_hits::cpu3.data       124111                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        56201                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
-system.cpu3.dcache.demand_hits::cpu3.data       180312                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data       180312                       # number of overall hits
-system.cpu3.dcache.overall_hits::total         180312                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          324                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          139                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          463                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          463                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu3.dcache.ReadReq_accesses::cpu3.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data       180775                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data       180775                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.002561                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.002561                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu3.dcache.writebacks::total               29                       # number of writebacks
-system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                             0                       # number of replacements
-system.l2c.tags.tagsinuse                      1962.780232                       # Cycle average of tags in use
-system.l2c.tags.total_refs                             332                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                          2932                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                          0.113233                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks           17.466765                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst           267.152061                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data           219.176305                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst           267.152061                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data           219.176305                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst           267.152061                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data           219.176305                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst           267.152061                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data           219.176305                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks           0.000267                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst            0.004076                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data            0.003344                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst            0.004076                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data            0.003344                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst            0.004076                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data            0.003344                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst            0.004076                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data            0.003344                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total                0.029950                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                    276                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks             116                       # number of Writeback hits
-system.l2c.Writeback_hits::total                  116                       # number of Writeback hits
-system.l2c.demand_hits::cpu0.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                     276                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu0.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu1.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
-system.l2c.overall_hits::total                    276                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 2872                       # number of ReadReq misses
-system.l2c.ReadExReq_misses::cpu0.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total                556                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                  3428                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu0.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu1.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu2.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu3.data              454                       # number of overall misses
-system.l2c.overall_misses::total                 3428                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total               3148                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks          116                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total              116                       # number of Writeback accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total              556                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                3704                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               3704                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.912325                       # miss rate for ReadReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.925486                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.925486                       # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,10 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,18 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  8 2013 10:00:13
-gem5 started Jun  8 2013 10:00:28
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
->>>>Exiting @ tick 729024000 because a thread reached the max instruction count
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/fast/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
+Skipping test: Test requires the 'EioProcess' SimObject.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,1405 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000729                       # Number of seconds simulated
-sim_ticks                                   729024000                       # Number of ticks simulated
-final_tick                                  729024000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1420709                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1420692                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              517863701                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236964                       # Number of bytes of host memory used
-host_seconds                                     1.41                       # Real time elapsed on the host
-sim_insts                                     1999959                       # Number of instructions simulated
-sim_ops                                       1999959                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst            25792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data            29056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            25792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data            29056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst            25792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data            29056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst            25792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data            29056                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               219392                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst        25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst        25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst        25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          103168                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst               403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data               454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst               403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data               454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst               403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data               454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst               403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data               454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  3428                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst            35378808                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            39856027                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            35378808                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data            39856027                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst            35378808                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data            39856027                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst            35378808                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data            39856027                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               300939338                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst       35378808                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       35378808                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst       35378808                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst       35378808                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          141515231                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst           35378808                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           39856027                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           35378808                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data           39856027                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst           35378808                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data           39856027                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst           35378808                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data           39856027                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              300939338                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                    300939338                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                2872                       # Transaction distribution
-system.membus.trans_dist::ReadResp               2872                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               556                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              556                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side         6856                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count                          6856                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side       219392                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size                     219392                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                 219392                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             4229968                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           31051500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              4.3                       # Layer utilization (%)
-system.toL2Bus.throughput                   335352471                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq               3148                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp              3148                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback              116                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq              556                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp             556                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side          926                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side          955                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side          926                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side          955                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side          926                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side          955                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side          926                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side          955                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count                         7524                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side        29632                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side        31488                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side        29632                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side        31488                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side        29632                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side        31488                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side        29632                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side        31488                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size                    244480                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus                244480                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus               0                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy            2374000                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy           2083500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy           2083500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy           2083500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy           2083500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy           2083500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy           2083500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy           2083500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy           2083500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization             0.3                       # Layer utilization (%)
-system.cpu0.dtb.fetch_hits                          0                       # ITB hits
-system.cpu0.dtb.fetch_misses                        0                       # ITB misses
-system.cpu0.dtb.fetch_acv                           0                       # ITB acv
-system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                      124435                       # DTB read hits
-system.cpu0.dtb.read_misses                         8                       # DTB read misses
-system.cpu0.dtb.read_acv                            0                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu0.dtb.write_hits                      56340                       # DTB write hits
-system.cpu0.dtb.write_misses                       10                       # DTB write misses
-system.cpu0.dtb.write_acv                           0                       # DTB write access violations
-system.cpu0.dtb.write_accesses                  56350                       # DTB write accesses
-system.cpu0.dtb.data_hits                      180775                       # DTB hits
-system.cpu0.dtb.data_misses                        18                       # DTB misses
-system.cpu0.dtb.data_acv                            0                       # DTB access violations
-system.cpu0.dtb.data_accesses                  180793                       # DTB accesses
-system.cpu0.itb.fetch_hits                     500020                       # ITB hits
-system.cpu0.itb.fetch_misses                       13                       # ITB misses
-system.cpu0.itb.fetch_acv                           0                       # ITB acv
-system.cpu0.itb.fetch_accesses                 500033                       # ITB accesses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.read_acv                            0                       # DTB read access violations
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.write_acv                           0                       # DTB write access violations
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.data_hits                           0                       # DTB hits
-system.cpu0.itb.data_misses                         0                       # DTB misses
-system.cpu0.itb.data_acv                            0                       # DTB access violations
-system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.workload.num_syscalls                  18                       # Number of system calls
-system.cpu0.numCycles                         1458048                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                     500001                       # Number of instructions committed
-system.cpu0.committedOps                       500001                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu0.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                      474689                       # number of integer instructions
-system.cpu0.num_fp_insts                           32                       # number of float instructions
-system.cpu0.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                       180793                       # number of memory refs
-system.cpu0.num_load_insts                     124443                       # Number of load instructions
-system.cpu0.num_store_insts                     56350                       # Number of store instructions
-system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu0.num_busy_cycles                   1458048                       # Number of busy cycles
-system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu0.icache.tags.replacements                   152                       # number of replacements
-system.cpu0.icache.tags.tagsinuse               216.376897                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs                  499557                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs               1078.956803                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   216.376897                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.422611                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total        0.422611                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst       499557                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total         499557                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst       499557                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total          499557                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst       499557                       # number of overall hits
-system.cpu0.icache.overall_hits::total         499557                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          463                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          463                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          463                       # number of overall misses
-system.cpu0.icache.overall_misses::total          463                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     23096000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     23096000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     23096000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     23096000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     23096000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     23096000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst       500020                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total       500020                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst       500020                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total       500020                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst       500020                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total       500020                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.000926                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.000926                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 49883.369330                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 49883.369330                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 49883.369330                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 49883.369330                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 49883.369330                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 49883.369330                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          463                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst          463                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst          463                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     22170000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     22170000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     22170000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     22170000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     22170000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     22170000                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.000926                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.000926                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.000926                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.000926                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47883.369330                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47883.369330                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47883.369330                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 47883.369330                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47883.369330                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 47883.369330                       # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements                    61                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse               273.500146                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs                  180312                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs                389.442765                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   273.500146                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.534180                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total        0.534180                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data       124111                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        56201                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
-system.cpu0.dcache.demand_hits::cpu0.data       180312                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data       180312                       # number of overall hits
-system.cpu0.dcache.overall_hits::total         180312                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          324                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data          139                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu0.dcache.demand_misses::cpu0.data          463                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data          463                       # number of overall misses
-system.cpu0.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     17474500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total     17474500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      7669500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total      7669500                       # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     25144000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     25144000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     25144000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     25144000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data       180775                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data       180775                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.002561                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.002561                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53933.641975                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 53933.641975                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 55176.258993                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 55176.258993                       # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 54306.695464                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 54306.695464                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 54306.695464                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 54306.695464                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu0.dcache.writebacks::total               29                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          324                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          139                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data          463                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data          463                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data     16826500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total     16826500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      7391500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      7391500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     24218000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     24218000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     24218000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     24218000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002561                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.002561                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002561                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.002561                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 51933.641975                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 53176.258993                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993                       # average WriteReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52306.695464                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 52306.695464                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52306.695464                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 52306.695464                       # average overall mshr miss latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dtb.fetch_hits                          0                       # ITB hits
-system.cpu1.dtb.fetch_misses                        0                       # ITB misses
-system.cpu1.dtb.fetch_acv                           0                       # ITB acv
-system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                      124435                       # DTB read hits
-system.cpu1.dtb.read_misses                         8                       # DTB read misses
-system.cpu1.dtb.read_acv                            0                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu1.dtb.write_hits                      56339                       # DTB write hits
-system.cpu1.dtb.write_misses                       10                       # DTB write misses
-system.cpu1.dtb.write_acv                           0                       # DTB write access violations
-system.cpu1.dtb.write_accesses                  56349                       # DTB write accesses
-system.cpu1.dtb.data_hits                      180774                       # DTB hits
-system.cpu1.dtb.data_misses                        18                       # DTB misses
-system.cpu1.dtb.data_acv                            0                       # DTB access violations
-system.cpu1.dtb.data_accesses                  180792                       # DTB accesses
-system.cpu1.itb.fetch_hits                     500012                       # ITB hits
-system.cpu1.itb.fetch_misses                       13                       # ITB misses
-system.cpu1.itb.fetch_acv                           0                       # ITB acv
-system.cpu1.itb.fetch_accesses                 500025                       # ITB accesses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.read_acv                            0                       # DTB read access violations
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.write_acv                           0                       # DTB write access violations
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.data_hits                           0                       # DTB hits
-system.cpu1.itb.data_misses                         0                       # DTB misses
-system.cpu1.itb.data_acv                            0                       # DTB access violations
-system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.workload.num_syscalls                  18                       # Number of system calls
-system.cpu1.numCycles                         1458048                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                     499993                       # Number of instructions committed
-system.cpu1.committedOps                       499993                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses               474681                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu1.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts        38179                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                      474681                       # number of integer instructions
-system.cpu1.num_fp_insts                           32                       # number of float instructions
-system.cpu1.num_int_register_reads             654273                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes            371536                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                       180792                       # number of memory refs
-system.cpu1.num_load_insts                     124443                       # Number of load instructions
-system.cpu1.num_store_insts                     56349                       # Number of store instructions
-system.cpu1.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu1.num_busy_cycles                   1458048                       # Number of busy cycles
-system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu1.icache.tags.replacements                   152                       # number of replacements
-system.cpu1.icache.tags.tagsinuse               216.373058                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs                  499549                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs               1078.939525                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   216.373058                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.422604                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total        0.422604                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst       499549                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total         499549                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst       499549                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total          499549                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst       499549                       # number of overall hits
-system.cpu1.icache.overall_hits::total         499549                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          463                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          463                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          463                       # number of overall misses
-system.cpu1.icache.overall_misses::total          463                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     23105000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total     23105000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst     23105000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total     23105000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst     23105000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total     23105000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst       500012                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total       500012                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst       500012                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total       500012                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst       500012                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total       500012                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.000926                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.000926                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 49902.807775                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 49902.807775                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 49902.807775                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 49902.807775                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 49902.807775                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 49902.807775                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          463                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst          463                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst          463                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     22179000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total     22179000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     22179000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total     22179000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     22179000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total     22179000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.000926                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.000926                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.000926                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.000926                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 47902.807775                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 47902.807775                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 47902.807775                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 47902.807775                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47902.807775                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 47902.807775                       # average overall mshr miss latency
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements                    61                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse               273.495183                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs                  180311                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs                389.440605                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   273.495183                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.534170                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total        0.534170                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data       124111                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        56200                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         56200                       # number of WriteReq hits
-system.cpu1.dcache.demand_hits::cpu1.data       180311                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total          180311                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data       180311                       # number of overall hits
-system.cpu1.dcache.overall_hits::total         180311                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          324                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          139                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          463                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          463                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data     17474500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total     17474500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      7669500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      7669500                       # number of WriteReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data     25144000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total     25144000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data     25144000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total     25144000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        56339                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        56339                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data       180774                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total       180774                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data       180774                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total       180774                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.002561                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.002561                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 53933.641975                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 53933.641975                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 55176.258993                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 55176.258993                       # average WriteReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 54306.695464                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 54306.695464                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 54306.695464                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 54306.695464                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu1.dcache.writebacks::total               29                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          324                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          139                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data          463                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data          463                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data     16826500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total     16826500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      7391500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      7391500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data     24218000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total     24218000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data     24218000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total     24218000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.002561                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.002561                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.002561                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.002561                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 51933.641975                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 53176.258993                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993                       # average WriteReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 52306.695464                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 52306.695464                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 52306.695464                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 52306.695464                       # average overall mshr miss latency
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dtb.fetch_hits                          0                       # ITB hits
-system.cpu2.dtb.fetch_misses                        0                       # ITB misses
-system.cpu2.dtb.fetch_acv                           0                       # ITB acv
-system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu2.dtb.read_hits                      124433                       # DTB read hits
-system.cpu2.dtb.read_misses                         8                       # DTB read misses
-system.cpu2.dtb.read_acv                            0                       # DTB read access violations
-system.cpu2.dtb.read_accesses                  124441                       # DTB read accesses
-system.cpu2.dtb.write_hits                      56339                       # DTB write hits
-system.cpu2.dtb.write_misses                       10                       # DTB write misses
-system.cpu2.dtb.write_acv                           0                       # DTB write access violations
-system.cpu2.dtb.write_accesses                  56349                       # DTB write accesses
-system.cpu2.dtb.data_hits                      180772                       # DTB hits
-system.cpu2.dtb.data_misses                        18                       # DTB misses
-system.cpu2.dtb.data_acv                            0                       # DTB access violations
-system.cpu2.dtb.data_accesses                  180790                       # DTB accesses
-system.cpu2.itb.fetch_hits                     500005                       # ITB hits
-system.cpu2.itb.fetch_misses                       13                       # ITB misses
-system.cpu2.itb.fetch_acv                           0                       # ITB acv
-system.cpu2.itb.fetch_accesses                 500018                       # ITB accesses
-system.cpu2.itb.read_hits                           0                       # DTB read hits
-system.cpu2.itb.read_misses                         0                       # DTB read misses
-system.cpu2.itb.read_acv                            0                       # DTB read access violations
-system.cpu2.itb.read_accesses                       0                       # DTB read accesses
-system.cpu2.itb.write_hits                          0                       # DTB write hits
-system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.write_acv                           0                       # DTB write access violations
-system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.data_hits                           0                       # DTB hits
-system.cpu2.itb.data_misses                         0                       # DTB misses
-system.cpu2.itb.data_acv                            0                       # DTB access violations
-system.cpu2.itb.data_accesses                       0                       # DTB accesses
-system.cpu2.workload.num_syscalls                  18                       # Number of system calls
-system.cpu2.numCycles                         1458048                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                     499986                       # Number of instructions committed
-system.cpu2.committedOps                       499986                       # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses               474674                       # Number of integer alu accesses
-system.cpu2.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu2.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts        38179                       # number of instructions that are conditional controls
-system.cpu2.num_int_insts                      474674                       # number of integer instructions
-system.cpu2.num_fp_insts                           32                       # number of float instructions
-system.cpu2.num_int_register_reads             654263                       # number of times the integer registers were read
-system.cpu2.num_int_register_writes            371529                       # number of times the integer registers were written
-system.cpu2.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu2.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu2.num_mem_refs                       180790                       # number of memory refs
-system.cpu2.num_load_insts                     124441                       # Number of load instructions
-system.cpu2.num_store_insts                     56349                       # Number of store instructions
-system.cpu2.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu2.num_busy_cycles                   1458048                       # Number of busy cycles
-system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu2.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu2.icache.tags.replacements                   152                       # number of replacements
-system.cpu2.icache.tags.tagsinuse               216.369218                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs                  499542                       # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs               1078.924406                       # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst   216.369218                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.422596                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total        0.422596                       # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits::cpu2.inst       499542                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total         499542                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst       499542                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total          499542                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst       499542                       # number of overall hits
-system.cpu2.icache.overall_hits::total         499542                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          463                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          463                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          463                       # number of overall misses
-system.cpu2.icache.overall_misses::total          463                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     23114000                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total     23114000                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst     23114000                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total     23114000                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst     23114000                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total     23114000                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst       500005                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total       500005                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst       500005                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total       500005                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst       500005                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total       500005                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.000926                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.000926                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 49922.246220                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 49922.246220                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 49922.246220                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 49922.246220                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 49922.246220                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 49922.246220                       # average overall miss latency
-system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          463                       # number of ReadReq MSHR misses
-system.cpu2.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses::cpu2.inst          463                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses::cpu2.inst          463                       # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst     22188000                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total     22188000                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst     22188000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total     22188000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst     22188000                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total     22188000                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.000926                       # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total     0.000926                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.000926                       # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total     0.000926                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 47922.246220                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 47922.246220                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 47922.246220                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 47922.246220                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 47922.246220                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 47922.246220                       # average overall mshr miss latency
-system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dcache.tags.replacements                    61                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse               273.490220                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs                  180309                       # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs                389.436285                       # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data   273.490220                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.534161                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total        0.534161                       # Average percentage of cache occupancy
-system.cpu2.dcache.ReadReq_hits::cpu2.data       124109                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total         124109                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        56200                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         56200                       # number of WriteReq hits
-system.cpu2.dcache.demand_hits::cpu2.data       180309                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total          180309                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data       180309                       # number of overall hits
-system.cpu2.dcache.overall_hits::total         180309                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          324                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          139                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          463                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          463                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data     17474500                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total     17474500                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      7669500                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      7669500                       # number of WriteReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data     25144000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total     25144000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data     25144000                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total     25144000                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data       124433                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total       124433                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        56339                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        56339                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data       180772                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total       180772                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data       180772                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total       180772                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.002561                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.002561                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 53933.641975                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 53933.641975                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 55176.258993                       # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 55176.258993                       # average WriteReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 54306.695464                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 54306.695464                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 54306.695464                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 54306.695464                       # average overall miss latency
-system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu2.dcache.writebacks::total               29                       # number of writebacks
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          324                       # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          139                       # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data          463                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data          463                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data     16826500                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total     16826500                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      7391500                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      7391500                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data     24218000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total     24218000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data     24218000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total     24218000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.002561                       # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total     0.002561                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.002561                       # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total     0.002561                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 51933.641975                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53176.258993                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993                       # average WriteReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 52306.695464                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 52306.695464                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52306.695464                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 52306.695464                       # average overall mshr miss latency
-system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dtb.fetch_hits                          0                       # ITB hits
-system.cpu3.dtb.fetch_misses                        0                       # ITB misses
-system.cpu3.dtb.fetch_acv                           0                       # ITB acv
-system.cpu3.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu3.dtb.read_hits                      124431                       # DTB read hits
-system.cpu3.dtb.read_misses                         8                       # DTB read misses
-system.cpu3.dtb.read_acv                            0                       # DTB read access violations
-system.cpu3.dtb.read_accesses                  124439                       # DTB read accesses
-system.cpu3.dtb.write_hits                      56339                       # DTB write hits
-system.cpu3.dtb.write_misses                       10                       # DTB write misses
-system.cpu3.dtb.write_acv                           0                       # DTB write access violations
-system.cpu3.dtb.write_accesses                  56349                       # DTB write accesses
-system.cpu3.dtb.data_hits                      180770                       # DTB hits
-system.cpu3.dtb.data_misses                        18                       # DTB misses
-system.cpu3.dtb.data_acv                            0                       # DTB access violations
-system.cpu3.dtb.data_accesses                  180788                       # DTB accesses
-system.cpu3.itb.fetch_hits                     499998                       # ITB hits
-system.cpu3.itb.fetch_misses                       13                       # ITB misses
-system.cpu3.itb.fetch_acv                           0                       # ITB acv
-system.cpu3.itb.fetch_accesses                 500011                       # ITB accesses
-system.cpu3.itb.read_hits                           0                       # DTB read hits
-system.cpu3.itb.read_misses                         0                       # DTB read misses
-system.cpu3.itb.read_acv                            0                       # DTB read access violations
-system.cpu3.itb.read_accesses                       0                       # DTB read accesses
-system.cpu3.itb.write_hits                          0                       # DTB write hits
-system.cpu3.itb.write_misses                        0                       # DTB write misses
-system.cpu3.itb.write_acv                           0                       # DTB write access violations
-system.cpu3.itb.write_accesses                      0                       # DTB write accesses
-system.cpu3.itb.data_hits                           0                       # DTB hits
-system.cpu3.itb.data_misses                         0                       # DTB misses
-system.cpu3.itb.data_acv                            0                       # DTB access violations
-system.cpu3.itb.data_accesses                       0                       # DTB accesses
-system.cpu3.workload.num_syscalls                  18                       # Number of system calls
-system.cpu3.numCycles                         1458048                       # number of cpu cycles simulated
-system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.committedInsts                     499979                       # Number of instructions committed
-system.cpu3.committedOps                       499979                       # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses               474668                       # Number of integer alu accesses
-system.cpu3.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu3.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts        38178                       # number of instructions that are conditional controls
-system.cpu3.num_int_insts                      474668                       # number of integer instructions
-system.cpu3.num_fp_insts                           32                       # number of float instructions
-system.cpu3.num_int_register_reads             654256                       # number of times the integer registers were read
-system.cpu3.num_int_register_writes            371524                       # number of times the integer registers were written
-system.cpu3.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu3.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu3.num_mem_refs                       180788                       # number of memory refs
-system.cpu3.num_load_insts                     124439                       # Number of load instructions
-system.cpu3.num_store_insts                     56349                       # Number of store instructions
-system.cpu3.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu3.num_busy_cycles                   1458048                       # Number of busy cycles
-system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu3.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu3.icache.tags.replacements                   152                       # number of replacements
-system.cpu3.icache.tags.tagsinuse               216.365379                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs                  499535                       # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs               1078.909287                       # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst   216.365379                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.422589                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total        0.422589                       # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits::cpu3.inst       499535                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total         499535                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst       499535                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total          499535                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst       499535                       # number of overall hits
-system.cpu3.icache.overall_hits::total         499535                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          463                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          463                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          463                       # number of overall misses
-system.cpu3.icache.overall_misses::total          463                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst     23123000                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total     23123000                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst     23123000                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total     23123000                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst     23123000                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total     23123000                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst       499998                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total       499998                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst       499998                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total       499998                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst       499998                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total       499998                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.000926                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.000926                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 49941.684665                       # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 49941.684665                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 49941.684665                       # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 49941.684665                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 49941.684665                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 49941.684665                       # average overall miss latency
-system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          463                       # number of ReadReq MSHR misses
-system.cpu3.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
-system.cpu3.icache.demand_mshr_misses::cpu3.inst          463                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses::cpu3.inst          463                       # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst     22197000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total     22197000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst     22197000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total     22197000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst     22197000                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total     22197000                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.000926                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.000926                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.000926                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.000926                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 47941.684665                       # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 47941.684665                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 47941.684665                       # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 47941.684665                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 47941.684665                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 47941.684665                       # average overall mshr miss latency
-system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dcache.tags.replacements                    61                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse               273.485257                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs                  180307                       # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs                389.431965                       # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data   273.485257                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.534151                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total        0.534151                       # Average percentage of cache occupancy
-system.cpu3.dcache.ReadReq_hits::cpu3.data       124107                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total         124107                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        56200                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         56200                       # number of WriteReq hits
-system.cpu3.dcache.demand_hits::cpu3.data       180307                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total          180307                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data       180307                       # number of overall hits
-system.cpu3.dcache.overall_hits::total         180307                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          324                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          139                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          463                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          463                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data     17474500                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total     17474500                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      7669500                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      7669500                       # number of WriteReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data     25144000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total     25144000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data     25144000                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total     25144000                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data       124431                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total       124431                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        56339                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        56339                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data       180770                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total       180770                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data       180770                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total       180770                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.002561                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.002561                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 53933.641975                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 53933.641975                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 55176.258993                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 55176.258993                       # average WriteReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 54306.695464                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 54306.695464                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 54306.695464                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 54306.695464                       # average overall miss latency
-system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu3.dcache.writebacks::total               29                       # number of writebacks
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          324                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          139                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data          463                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data          463                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data     16826500                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total     16826500                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      7391500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      7391500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data     24218000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total     24218000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data     24218000                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total     24218000                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.002561                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.002561                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.002561                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.002561                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 51933.641975                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 53176.258993                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993                       # average WriteReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 52306.695464                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 52306.695464                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52306.695464                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 52306.695464                       # average overall mshr miss latency
-system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                             0                       # number of replacements
-system.l2c.tags.tagsinuse                      1943.172107                       # Cycle average of tags in use
-system.l2c.tags.total_refs                             332                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                          2932                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                          0.113233                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks           17.224555                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst           265.011494                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data           216.488870                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst           265.006320                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data           216.484940                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst           265.001344                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data           216.481052                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst           264.996369                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data           216.477163                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks           0.000263                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst            0.004044                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data            0.003303                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst            0.004044                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data            0.003303                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst            0.004044                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data            0.003303                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst            0.004044                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data            0.003303                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total                0.029650                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                    276                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks             116                       # number of Writeback hits
-system.l2c.Writeback_hits::total                  116                       # number of Writeback hits
-system.l2c.demand_hits::cpu0.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                     276                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu0.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu1.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
-system.l2c.overall_hits::total                    276                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 2872                       # number of ReadReq misses
-system.l2c.ReadExReq_misses::cpu0.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total                556                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                  3428                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu0.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu1.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu2.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu3.data              454                       # number of overall misses
-system.l2c.overall_misses::total                 3428                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst     21101500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data     16409500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst     21110000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data     16409500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst     21118500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data     16409500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.inst     21129500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.data     16412000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total      150100000                       # number of ReadReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data      7252500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data      7252500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data      7252500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data      7252500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total     29010000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst     21101500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data     23662000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst     21110000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data     23662000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst     21118500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data     23662000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst     21129500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data     23664500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total       179110000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst     21101500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data     23662000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst     21110000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data     23662000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst     21118500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data     23662000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst     21129500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data     23664500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total      179110000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total               3148                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks          116                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total              116                       # number of Writeback accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total              556                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                3704                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               3704                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.912325                       # miss rate for ReadReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.925486                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.925486                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52361.042184                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52093.650794                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52382.133995                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 52093.650794                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52403.225806                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 52093.650794                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.inst 52430.521092                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.data 52101.587302                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52263.231198                       # average ReadReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52176.258993                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52176.258993                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52176.258993                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52176.258993                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52176.258993                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52361.042184                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52118.942731                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 52382.133995                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 52118.942731                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 52403.225806                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 52118.942731                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 52430.521092                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 52124.449339                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52249.124854                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52361.042184                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52118.942731                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 52382.133995                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 52118.942731                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 52403.225806                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 52118.942731                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 52430.521092                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 52124.449339                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52249.124854                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.ReadReq_mshr_misses::cpu0.inst          403                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data          315                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst          403                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data          315                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst          403                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data          315                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.inst          403                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.data          315                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total            2872                       # number of ReadReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data          139                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data          139                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data          139                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3.data          139                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total           556                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst          403                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data          454                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst          403                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data          454                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst          403                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data          454                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst          403                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.data          454                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total             3428                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst          403                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data          454                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst          403                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data          454                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst          403                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data          454                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst          403                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.data          454                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total            3428                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     16120000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data     12600000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     16274000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data     12629500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst     16282500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data     12629500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.inst     16293500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.data     12632000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    115461000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      5560000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data      5584500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data      5584500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data      5584500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total     22313500                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst     16120000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data     18160000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     16274000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data     18214000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst     16282500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data     18214000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst     16293500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data     18216500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total    137774500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst     16120000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data     18160000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     16274000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data     18214000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst     16282500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data     18214000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst     16293500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data     18216500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total    137774500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.870410                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.972222                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.870410                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.972222                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.870410                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.972222                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.870410                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.972222                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.912325                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.870410                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.980562                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.870410                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.980562                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.870410                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.980562                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.870410                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.980562                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.925486                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.870410                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.980562                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.870410                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.980562                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.870410                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.980562                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.870410                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data     0.980562                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.925486                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40382.133995                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40093.650794                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40403.225806                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40093.650794                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40430.521092                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40101.587302                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40202.298050                       # average ReadReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data        40000                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40176.258993                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40176.258993                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40176.258993                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40132.194245                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40382.133995                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40118.942731                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40403.225806                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40118.942731                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40430.521092                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40124.449339                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40190.927655                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40382.133995                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40118.942731                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40403.225806                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40118.942731                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40430.521092                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40124.449339                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40190.927655                       # average overall mshr miss latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -27,7 +27,11 @@
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.slave[1]
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
 
 [system.cpu0]
 type=DerivO3CPU
@@ -43,7 +47,7 @@
 branchPred=system.cpu0.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +96,7 @@
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +126,9 @@
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +136,11 @@
 
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +151,21 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=SparcTLB
 size=64
@@ -422,10 +435,11 @@
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -436,12 +450,21 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=SparcInterrupts
 
@@ -488,7 +511,7 @@
 branchPred=system.cpu1.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -537,6 +560,7 @@
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -566,11 +590,9 @@
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -578,10 +600,11 @@
 
 [system.cpu1.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -592,12 +615,21 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
 
+[system.cpu1.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.dtb]
 type=SparcTLB
 size=64
@@ -867,10 +899,11 @@
 
 [system.cpu1.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -881,12 +914,21 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
 
+[system.cpu1.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.interrupts]
 type=SparcInterrupts
 
@@ -914,7 +956,7 @@
 branchPred=system.cpu2.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -963,6 +1005,7 @@
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -992,11 +1035,9 @@
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -1004,10 +1045,11 @@
 
 [system.cpu2.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -1018,12 +1060,21 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu2.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.dcache_port
 mem_side=system.toL2Bus.slave[5]
 
+[system.cpu2.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu2.dtb]
 type=SparcTLB
 size=64
@@ -1293,10 +1344,11 @@
 
 [system.cpu2.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -1307,12 +1359,21 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu2.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.icache_port
 mem_side=system.toL2Bus.slave[4]
 
+[system.cpu2.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu2.interrupts]
 type=SparcInterrupts
 
@@ -1340,7 +1401,7 @@
 branchPred=system.cpu3.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -1389,6 +1450,7 @@
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -1418,11 +1480,9 @@
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -1430,10 +1490,11 @@
 
 [system.cpu3.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -1444,12 +1505,21 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu3.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.dcache_port
 mem_side=system.toL2Bus.slave[7]
 
+[system.cpu3.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu3.dtb]
 type=SparcTLB
 size=64
@@ -1719,10 +1789,11 @@
 
 [system.cpu3.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -1733,12 +1804,21 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu3.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.icache_port
 mem_side=system.toL2Bus.slave[6]
 
+[system.cpu3.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu3.interrupts]
 type=SparcInterrupts
 
@@ -1752,12 +1832,17 @@
 [system.cpu3.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -1768,39 +1853,50 @@
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[0]
+mem_side=system.membus.slave[1]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
 
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 master=system.physmem.port
-slave=system.l2c.mem_side system.system_port
+slave=system.system_port system.l2c.mem_side
 
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
-lines_per_rowbuffer=32
+lines_per_rowbuffer=128
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -1811,13 +1907,12 @@
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
 [system.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,2 +1,4 @@
-warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
+fatal: Can't load object file tests/test-progs/m5threads/bin/sparc/linux/test_atomic
+ @ cycle 0
+[create:build/SPARC/sim/process.cc, line 613]
+Memory Usage: 253240 KBytes
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,84 +1,8 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:04:14
-gem5 started Mar 26 2013 15:04:37
-gem5 executing on ribera.cs.wisc.edu
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+gem5 compiled Jul 17 2013 12:19:08
+gem5 started Jul 17 2013 12:19:19
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-Init done
-[Iteration 1, Thread 1] Got lock
-[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 1, Thread 2] Got lock
-[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2
-[Iteration 1, Thread 3] Got lock
-[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
-Iteration 1 completed
-[Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3
-[Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
-Iteration 2 completed
-[Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3
-[Iteration 3, Thread 1] Got lock
-[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
-Iteration 3 completed
-[Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1
-[Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
-Iteration 4 completed
-[Iteration 5, Thread 3] Got lock
-[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
-Iteration 5 completed
-[Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 6, Thread 2] Got lock
-[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2
-[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
-Iteration 6 completed
-[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2
-[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
-Iteration 7 completed
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
-[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
-Iteration 8 completed
-[Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
-[Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
-Iteration 9 completed
-[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
-[Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
-Iteration 10 completed
-PASSED :-)
-Exiting @ tick 105945500 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,2594 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000111                       # Number of seconds simulated
-sim_ticks                                   110804500                       # Number of ticks simulated
-final_tick                                  110804500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 110530                       # Simulator instruction rate (inst/s)
-host_op_rate                                   110530                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               11745373                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 249508                       # Number of bytes of host memory used
-host_seconds                                     9.43                       # Real time elapsed on the host
-sim_insts                                     1042724                       # Number of instructions simulated
-sim_ops                                       1042724                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst            22784                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data            10752                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst              640                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data              832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst             4672                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data             1280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst              384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                42176                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst        22784                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst          640                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst         4672                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst          384                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           28480                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst               356                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data               168                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst                10                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data                13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst                73                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data                20                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst                 6                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   659                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst           205623418                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            97035770                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst             5775939                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             7508720                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst            42164353                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data            11551877                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst             3465563                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             7508720                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               380634361                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      205623418                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst        5775939                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst       42164353                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst        3465563                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          257029272                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          205623418                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           97035770                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst            5775939                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            7508720                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst           42164353                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data           11551877                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst            3465563                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            7508720                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              380634361                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           660                       # Total number of read requests seen
-system.physmem.writeReqs                            0                       # Total number of write requests seen
-system.physmem.cpureqs                            736                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                        42176                       # Total number of bytes read from memory
-system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd                  42176                       # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite                 76                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                   115                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                    39                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                    29                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                    60                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                    65                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                    27                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                    18                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                    24                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                     7                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                    28                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10                   23                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11                   12                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12                   60                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13                   38                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14                   17                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15                   98                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
-system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                       110776500                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                     660                       # Categorize read packet sizes
-system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::6                      0                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                       404                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       193                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        49                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        12                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          128                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      281.500000                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     172.723314                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     317.555625                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64                51     39.84%     39.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128               11      8.59%     48.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192               15     11.72%     60.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256                9      7.03%     67.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320               10      7.81%     75.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384                5      3.91%     78.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448                3      2.34%     81.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512                4      3.12%     84.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576                3      2.34%     86.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640                4      3.12%     89.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704                2      1.56%     91.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768                2      1.56%     92.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832                2      1.56%     94.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024               4      3.12%     97.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152               1      0.78%     98.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536               1      0.78%     99.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984               1      0.78%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            128                       # Bytes accessed per row activation
-system.physmem.totQLat                        3818750                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat                  18118750                       # Sum of mem lat for all requests
-system.physmem.totBusLat                      3300000                       # Total cycles spent in databus access
-system.physmem.totBankLat                    11000000                       # Total cycles spent in bank access
-system.physmem.avgQLat                        5785.98                       # Average queueing delay per request
-system.physmem.avgBankLat                    16666.67                       # Average bank access latency per request
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
-system.physmem.avgMemAccLat                  27452.65                       # Average memory access latency
-system.physmem.avgRdBW                         380.63                       # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                 380.63                       # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil                           2.97                       # Data bus utilization in percentage
-system.physmem.avgRdQLen                         0.16                       # Average read queue length over time
-system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
-system.physmem.readRowHits                        532                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.61                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                       167843.18                       # Average gap between requests
-system.membus.throughput                    380634361                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 529                       # Transaction distribution
-system.membus.trans_dist::ReadResp                528                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              287                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              76                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               163                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              131                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side         1714                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count                          1714                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side        42176                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size                      42176                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                  42176                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              929000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            6308925                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              5.7                       # Layer utilization (%)
-system.toL2Bus.throughput                  1691772446                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq               2536                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp              2535                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback                1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq             290                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp            290                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq              393                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp             393                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side         1175                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side          586                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side          856                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side          365                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side          850                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side          371                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side          860                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side          352                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count                         5415                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side        37568                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side        11136                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side        27392                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side         1536                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side        27200                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side         1600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side        27520                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side         1536                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size                    135488                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus                135488                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus           51968                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy            1623982                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              1.5                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy           2710248                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             2.4                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy           1462515                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             1.3                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy           1929494                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             1.7                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy           1189495                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             1.1                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy           1927246                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization             1.7                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy           1192987                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization             1.1                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy           1937245                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization             1.7                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy           1118007                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization             1.0                       # Layer utilization (%)
-system.cpu0.branchPred.lookups                  82992                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted            80791                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect             1218                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups               80321                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                  78273                       # Number of BTB hits
-system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            97.450231                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                    512                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect               132                       # Number of incorrect RAS predictions.
-system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          221610                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles             17247                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                        492529                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                      82992                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches             78785                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                       161677                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                   3808                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles                 13819                       # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles         1570                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.CacheLines                     5835                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes                  493                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples            196760                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             2.503197                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.215126                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                   35083     17.83%     17.83% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                   80084     40.70%     58.53% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                     578      0.29%     58.83% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                     973      0.49%     59.32% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                     477      0.24%     59.56% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                   76189     38.72%     98.28% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                     571      0.29%     98.57% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                     349      0.18%     98.75% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                    2456      1.25%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total              196760                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.374496                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       2.222503                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                   17898                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles                15432                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                   160701                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles                  287                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                  2442                       # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts                489694                       # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles                  2442                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                   18563                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                    848                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles         13994                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                   160355                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles                  558                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts                486837                       # Number of instructions processed by rename
-system.cpu0.rename.LSQFullEvents                  188                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands             332900                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups               970872                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups          970872                       # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps               319955                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                   12945                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts               867                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts           888                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                     3605                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads              155755                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores              78714                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads            75965                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores           75781                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                    407125                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded                911                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                   404423                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued              128                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined          10748                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined         9686                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved           352                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples       196760                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        2.055413                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.097364                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0              34065     17.31%     17.31% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1               4908      2.49%     19.81% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2              77935     39.61%     59.42% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3              77266     39.27%     98.69% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4               1571      0.80%     99.48% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                648      0.33%     99.81% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6                262      0.13%     99.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7                 89      0.05%     99.99% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8                 16      0.01%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total         196760                       # Number of insts issued each cycle
-system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                     57     25.91%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                    51     23.18%     49.09% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite                  112     50.91%    100.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu               170994     42.28%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead              155300     38.40%     80.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite              78129     19.32%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total                404423                       # Type of FU issued
-system.cpu0.iq.rate                          1.824931                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                        220                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.000544                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads           1005954                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes           418838                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses       402603                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses                404643                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads           75498                       # Number of loads that had data forwarded from stores
-system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads         2188                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation           54                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores         1424                       # Number of stores squashed
-system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked           19                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                  2442                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                    391                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles                   33                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts             484551                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts              313                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts               155755                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts               78714                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts               799                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                    38                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents            54                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect           343                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect         1106                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts                1449                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts               403352                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts               154964                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts             1071                       # Number of squashed instructions skipped in execute
-system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                        76515                       # number of nop insts executed
-system.cpu0.iew.exec_refs                      232993                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                   80132                       # Number of branches executed
-system.cpu0.iew.exec_stores                     78029                       # Number of stores executed
-system.cpu0.iew.exec_rate                    1.820098                       # Inst execution rate
-system.cpu0.iew.wb_sent                        402944                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                       402603                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                   238549                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                   241004                       # num instructions consuming a value
-system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      1.816719                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.989813                       # average fanout of values written-back
-system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts          12240                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts             1218                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples       194318                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     2.430470                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     2.136197                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0        34493     17.75%     17.75% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1        79895     41.12%     58.87% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2         2401      1.24%     60.10% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3          689      0.35%     60.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4          530      0.27%     60.73% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5        75316     38.76%     99.49% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6          445      0.23%     99.72% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7          242      0.12%     99.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8          307      0.16%    100.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total       194318                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts              472284                       # Number of instructions committed
-system.cpu0.commit.committedOps                472284                       # Number of ops (including micro ops) committed
-system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                        230857                       # Number of memory references committed
-system.cpu0.commit.loads                       153567                       # Number of loads committed
-system.cpu0.commit.membars                         84                       # Number of memory barriers committed
-system.cpu0.commit.branches                     79177                       # Number of branches committed
-system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                   318286                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
-system.cpu0.commit.bw_lim_events                  307                       # number cycles where commit BW limit reached
-system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                      677374                       # The number of ROB reads
-system.cpu0.rob.rob_writes                     971507                       # The number of ROB writes
-system.cpu0.timesIdled                            326                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                          24850                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts                     396291                       # Number of Instructions Simulated
-system.cpu0.committedOps                       396291                       # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total               396291                       # Number of Instructions Simulated
-system.cpu0.cpi                              0.559210                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        0.559210                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              1.788236                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        1.788236                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                  721592                       # number of integer regfile reads
-system.cpu0.int_regfile_writes                 325227                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
-system.cpu0.misc_regfile_reads                 234817                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
-system.cpu0.icache.tags.replacements                   297                       # number of replacements
-system.cpu0.icache.tags.tagsinuse               241.148232                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs                    5079                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs                   587                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs                  8.652470                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   241.148232                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.470993                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total        0.470993                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst         5079                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total           5079                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst         5079                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total            5079                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst         5079                       # number of overall hits
-system.cpu0.icache.overall_hits::total           5079                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          756                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          756                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          756                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           756                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          756                       # number of overall misses
-system.cpu0.icache.overall_misses::total          756                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     35147245                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     35147245                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     35147245                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     35147245                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     35147245                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     35147245                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst         5835                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total         5835                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst         5835                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total         5835                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst         5835                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total         5835                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.129563                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.129563                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.129563                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.129563                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.129563                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.129563                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46491.064815                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 46491.064815                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46491.064815                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 46491.064815                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46491.064815                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 46491.064815                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          168                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total          168                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst          168                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total          168                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst          168                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total          168                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          588                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total          588                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst          588                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total          588                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst          588                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total          588                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     27250252                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     27250252                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     27250252                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     27250252                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     27250252                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     27250252                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.100771                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.100771                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.100771                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.100771                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.100771                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.100771                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46343.965986                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46343.965986                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46343.965986                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 46343.965986                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46343.965986                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 46343.965986                       # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements                     2                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse               141.869283                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs                  155614                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs                   170                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs                915.376471                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   141.869283                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.277088                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total        0.277088                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data        78995                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          78995                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        76703                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         76703                       # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits::cpu0.data           21                       # number of SwapReq hits
-system.cpu0.dcache.SwapReq_hits::total             21                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data       155698                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total          155698                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data       155698                       # number of overall hits
-system.cpu0.dcache.overall_hits::total         155698                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          410                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          410                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data          545                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total          545                       # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses::cpu0.data           21                       # number of SwapReq misses
-system.cpu0.dcache.SwapReq_misses::total           21                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data          955                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total           955                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data          955                       # number of overall misses
-system.cpu0.dcache.overall_misses::total          955                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     13319205                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total     13319205                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     35150505                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total     35150505                       # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       418750                       # number of SwapReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::total       418750                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     48469710                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     48469710                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     48469710                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     48469710                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        79405                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        79405                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        77248                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        77248                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data       156653                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total       156653                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data       156653                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total       156653                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.005163                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.005163                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007055                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.007055                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.500000                       # miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::total     0.500000                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006096                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.006096                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006096                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.006096                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32485.865854                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 32485.865854                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64496.339450                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 64496.339450                       # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19940.476190                       # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::total 19940.476190                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50753.623037                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 50753.623037                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50753.623037                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 50753.623037                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs          503                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               21                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    23.952381                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
-system.cpu0.dcache.writebacks::total                1                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          223                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total          223                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          370                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total          370                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data          593                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total          593                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data          593                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total          593                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          187                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total          187                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          175                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total          175                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           21                       # number of SwapReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::total           21                       # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data          362                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total          362                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data          362                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total          362                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      6285007                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total      6285007                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      7788228                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      7788228                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       375250                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::total       375250                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     14073235                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     14073235                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     14073235                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     14073235                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002355                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002355                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002265                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002265                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.500000                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002311                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.002311                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002311                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.002311                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33609.663102                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33609.663102                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44504.160000                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44504.160000                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17869.047619                       # average SwapReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17869.047619                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38876.339779                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38876.339779                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38876.339779                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38876.339779                       # average overall mshr miss latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                  43495                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted            40766                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect             1279                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups               37360                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                  36580                       # Number of BTB hits
-system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            97.912206                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                    665                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
-system.cpu1.numCycles                          177681                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles             34028                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                        233746                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                      43495                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches             37245                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                        88254                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                   3762                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles                 42089                       # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.NoActiveThreadStallCycles         7739                       # Number of stall cycles due to no active thread to fetch from
-system.cpu1.fetch.PendingTrapStallCycles          785                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines                    25656                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                  258                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples            175306                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.333360                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.985884                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                   87052     49.66%     49.66% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                   46435     26.49%     76.15% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                    9084      5.18%     81.33% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                    3194      1.82%     83.15% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                     686      0.39%     83.54% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                   23635     13.48%     97.02% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                    1173      0.67%     97.69% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                     772      0.44%     98.13% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                    3275      1.87%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total              175306                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.244793                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       1.315537                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                   41969                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles                35783                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                    79597                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles                 7812                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                  2406                       # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts                230200                       # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles                  2406                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                   42677                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                  23059                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles         11946                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                    72053                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles                15426                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts                227940                       # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents                     4                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents                   19                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands             156532                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups               420697                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups          420697                       # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps               143693                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                   12839                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts              1114                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts          1240                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                    18203                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads               60713                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores              26873                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads            30033                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores           21821                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                    184781                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded               9329                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                   189617                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued              108                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined          10957                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined        10934                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved           690                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples       175306                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        1.081634                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.264768                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0              84668     48.30%     48.30% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1              30997     17.68%     65.98% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2              27119     15.47%     81.45% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3              27768     15.84%     97.29% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4               3226      1.84%     99.13% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               1160      0.66%     99.79% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6                259      0.15%     99.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7                 52      0.03%     99.97% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8                 57      0.03%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total         175306                       # Number of insts issued each cycle
-system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                     12      4.55%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                    42     15.91%     20.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite                  210     79.55%    100.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu                95616     50.43%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead               67820     35.77%     86.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite              26181     13.81%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total                189617                       # Type of FU issued
-system.cpu1.iq.rate                          1.067177                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                        264                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.001392                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads            554912                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes           205110                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses       187814                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses                189881                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           21562                       # Number of loads that had data forwarded from stores
-system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads         2474                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation           43                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores         1439                       # Number of stores squashed
-system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                  2406                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                    736                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles                   43                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts             225068                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts              373                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts                60713                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts               26873                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts              1076                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                    42                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents            43                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect           453                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect          939                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts                1392                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts               188449                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts                59619                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts             1168                       # Number of squashed instructions skipped in execute
-system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        30958                       # number of nop insts executed
-system.cpu1.iew.exec_refs                       85720                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                   40129                       # Number of branches executed
-system.cpu1.iew.exec_stores                     26101                       # Number of stores executed
-system.cpu1.iew.exec_rate                    1.060603                       # Inst execution rate
-system.cpu1.iew.wb_sent                        188127                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                       187814                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                   102456                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                   107134                       # num instructions consuming a value
-system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      1.057029                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.956335                       # average fanout of values written-back
-system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts          12618                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls           8639                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts             1279                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples       165161                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     1.286212                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.860966                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0        85256     51.62%     51.62% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1        38272     23.17%     74.79% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2         6084      3.68%     78.48% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3         9527      5.77%     84.24% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4         1571      0.95%     85.20% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5        22201     13.44%     98.64% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6          436      0.26%     98.90% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7         1006      0.61%     99.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8          808      0.49%    100.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total       165161                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts              212432                       # Number of instructions committed
-system.cpu1.commit.committedOps                212432                       # Number of ops (including micro ops) committed
-system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                         83673                       # Number of memory references committed
-system.cpu1.commit.loads                        58239                       # Number of loads committed
-system.cpu1.commit.membars                       7917                       # Number of memory barriers committed
-system.cpu1.commit.branches                     39308                       # Number of branches committed
-system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                   145097                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu1.commit.bw_lim_events                  808                       # number cycles where commit BW limit reached
-system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                      388816                       # The number of ROB reads
-system.cpu1.rob.rob_writes                     452512                       # The number of ROB writes
-system.cpu1.timesIdled                            218                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                           2375                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                       43927                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                     174425                       # Number of Instructions Simulated
-system.cpu1.committedOps                       174425                       # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total               174425                       # Number of Instructions Simulated
-system.cpu1.cpi                              1.018667                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.018667                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.981675                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.981675                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                  315718                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                 148477                       # number of integer regfile writes
-system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                  87269                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
-system.cpu1.icache.tags.replacements                   318                       # number of replacements
-system.cpu1.icache.tags.tagsinuse                79.958659                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs                   25178                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs                   428                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs                 58.827103                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst    79.958659                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.156169                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total        0.156169                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst        25178                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total          25178                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst        25178                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total           25178                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst        25178                       # number of overall hits
-system.cpu1.icache.overall_hits::total          25178                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          478                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          478                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          478                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           478                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          478                       # number of overall misses
-system.cpu1.icache.overall_misses::total          478                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      7224243                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total      7224243                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst      7224243                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total      7224243                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst      7224243                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total      7224243                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst        25656                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total        25656                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst        25656                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total        25656                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst        25656                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total        25656                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.018631                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.018631                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.018631                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.018631                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.018631                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.018631                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15113.479079                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 15113.479079                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15113.479079                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 15113.479079                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15113.479079                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 15113.479079                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs           26                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs           13                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           50                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total           50                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst           50                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total           50                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst           50                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total           50                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          428                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total          428                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst          428                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total          428                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst          428                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total          428                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      5769006                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total      5769006                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      5769006                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total      5769006                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      5769006                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total      5769006                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016682                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.016682                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.016682                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.016682                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.016682                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.016682                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13478.985981                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13478.985981                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13478.985981                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 13478.985981                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13478.985981                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 13478.985981                       # average overall mshr miss latency
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements                     0                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse                24.742100                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs                   31558                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs                    29                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs               1088.206897                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data    24.742100                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.048324                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total        0.048324                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data        37722                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          37722                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        25226                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         25226                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data           16                       # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data        62948                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total           62948                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data        62948                       # number of overall hits
-system.cpu1.dcache.overall_hits::total          62948                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          319                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          319                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          132                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          132                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data           60                       # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total           60                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          451                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           451                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          451                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          451                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      3919891                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total      3919891                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2617261                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      2617261                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       548504                       # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total       548504                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data      6537152                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total      6537152                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data      6537152                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total      6537152                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        38041                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        38041                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        25358                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        25358                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data           76                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total           76                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data        63399                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total        63399                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data        63399                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total        63399                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.008386                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.008386                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.005205                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.005205                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.789474                       # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total     0.789474                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.007114                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.007114                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.007114                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.007114                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12288.059561                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12288.059561                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19827.734848                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 19827.734848                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  9141.733333                       # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total  9141.733333                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14494.793792                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 14494.793792                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14494.793792                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14494.793792                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          154                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total          154                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           32                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total           32                       # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data          186                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total          186                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data          186                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total          186                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          165                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          165                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          100                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total          100                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           60                       # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total           60                       # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data          265                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total          265                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data          265                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total          265                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1138770                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1138770                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1290739                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1290739                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       428496                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total       428496                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      2429509                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total      2429509                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      2429509                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total      2429509                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.004337                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.004337                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.003944                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.003944                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.789474                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.789474                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.004180                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.004180                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.004180                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.004180                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  6901.636364                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  6901.636364                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12907.390000                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12907.390000                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  7141.600000                       # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  7141.600000                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data  9167.958491                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total  9167.958491                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data  9167.958491                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total  9167.958491                       # average overall mshr miss latency
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.branchPred.lookups                  51236                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted            48519                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect             1308                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups               45052                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                  44357                       # Number of BTB hits
-system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            98.457338                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                    684                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                          177316                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles             28846                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                        286216                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                      51236                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches             45041                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                       100902                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                   3805                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles                 31210                       # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.NoActiveThreadStallCycles         7739                       # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles          775                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.CacheLines                    19767                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                  276                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples            171898                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.665034                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.139289                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                   70996     41.30%     41.30% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                   51338     29.87%     71.17% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                    6125      3.56%     74.73% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                    3190      1.86%     76.59% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                     695      0.40%     76.99% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                   34353     19.98%     96.97% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                    1162      0.68%     97.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                     771      0.45%     98.10% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                    3268      1.90%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total              171898                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.288953                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.614158                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                   33770                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles                27924                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                    94988                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles                 5055                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                  2422                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts                282690                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                  2422                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                   34480                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                  14885                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles         12280                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                    90190                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles                 9902                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts                280450                       # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents                     4                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents                   24                       # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands             196553                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups               537620                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups          537620                       # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps               183508                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                   13045                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts              1112                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts          1237                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                    12513                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads               79191                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores              37564                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads            37796                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores           32512                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                    232563                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded               6341                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                   234561                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued               83                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined          11040                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined        10888                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved           602                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples       171898                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.364536                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.313534                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0              68441     39.81%     39.81% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1              22472     13.07%     52.89% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2              37788     21.98%     74.87% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3              38389     22.33%     97.20% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4               3254      1.89%     99.10% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5               1164      0.68%     99.77% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6                277      0.16%     99.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7                 56      0.03%     99.97% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8                 57      0.03%    100.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total         171898                       # Number of insts issued each cycle
-system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                     17      6.14%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                    50     18.05%     24.19% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                  210     75.81%    100.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu               114217     48.69%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead               83468     35.58%     84.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite              36876     15.72%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total                234561                       # Type of FU issued
-system.cpu2.iq.rate                          1.322842                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                        277                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.001181                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads            641380                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes           249989                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses       232740                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses                234838                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads           32248                       # Number of loads that had data forwarded from stores
-system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads         2484                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation           45                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores         1465                       # Number of stores squashed
-system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                  2422                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                    851                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles                   46                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts             277610                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts              365                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts                79191                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts               37564                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts              1068                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                    46                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents            45                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect           466                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect          970                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts                1436                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts               233403                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts                78158                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts             1158                       # Number of squashed instructions skipped in execute
-system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                        38706                       # number of nop insts executed
-system.cpu2.iew.exec_refs                      114950                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                   47927                       # Number of branches executed
-system.cpu2.iew.exec_stores                     36792                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.316311                       # Inst execution rate
-system.cpu2.iew.wb_sent                        233070                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                       232740                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                   131730                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                   136434                       # num instructions consuming a value
-system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.312572                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.965522                       # average fanout of values written-back
-system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts          12692                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls           5739                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts             1308                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples       161737                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.637943                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.020354                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0        66243     40.96%     40.96% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1        46082     28.49%     69.45% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2         6100      3.77%     73.22% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3         6659      4.12%     77.34% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4         1556      0.96%     78.30% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5        32794     20.28%     98.58% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6          480      0.30%     98.87% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7         1001      0.62%     99.49% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8          822      0.51%    100.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total       161737                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts              264916                       # Number of instructions committed
-system.cpu2.commit.committedOps                264916                       # Number of ops (including micro ops) committed
-system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                        112806                       # Number of memory references committed
-system.cpu2.commit.loads                        76707                       # Number of loads committed
-system.cpu2.commit.membars                       5024                       # Number of memory barriers committed
-system.cpu2.commit.branches                     47088                       # Number of branches committed
-system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                   182014                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu2.commit.bw_lim_events                  822                       # number cycles where commit BW limit reached
-system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                      437936                       # The number of ROB reads
-system.cpu2.rob.rob_writes                     557643                       # The number of ROB writes
-system.cpu2.timesIdled                            224                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                           5418                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                       44292                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                     222015                       # Number of Instructions Simulated
-system.cpu2.committedOps                       222015                       # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total               222015                       # Number of Instructions Simulated
-system.cpu2.cpi                              0.798667                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        0.798667                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              1.252087                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        1.252087                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                  403571                       # number of integer regfile reads
-system.cpu2.int_regfile_writes                 188531                       # number of integer regfile writes
-system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                 116514                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
-system.cpu2.icache.tags.replacements                   317                       # number of replacements
-system.cpu2.icache.tags.tagsinuse                82.351710                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs                   19274                       # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs                   425                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs                 45.350588                       # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst    82.351710                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.160843                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total        0.160843                       # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits::cpu2.inst        19274                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total          19274                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst        19274                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total           19274                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst        19274                       # number of overall hits
-system.cpu2.icache.overall_hits::total          19274                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          493                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          493                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          493                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           493                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          493                       # number of overall misses
-system.cpu2.icache.overall_misses::total          493                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     11521742                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total     11521742                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst     11521742                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total     11521742                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst     11521742                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total     11521742                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst        19767                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total        19767                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst        19767                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total        19767                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst        19767                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total        19767                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.024941                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.024941                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.024941                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.024941                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.024941                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.024941                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23370.673428                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 23370.673428                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23370.673428                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 23370.673428                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23370.673428                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 23370.673428                       # average overall miss latency
-system.cpu2.icache.blocked_cycles::no_mshrs           85                       # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs           85                       # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           68                       # number of ReadReq MSHR hits
-system.cpu2.icache.ReadReq_mshr_hits::total           68                       # number of ReadReq MSHR hits
-system.cpu2.icache.demand_mshr_hits::cpu2.inst           68                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_hits::total           68                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits::cpu2.inst           68                       # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_hits::total           68                       # number of overall MSHR hits
-system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          425                       # number of ReadReq MSHR misses
-system.cpu2.icache.ReadReq_mshr_misses::total          425                       # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses::cpu2.inst          425                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.demand_mshr_misses::total          425                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses::cpu2.inst          425                       # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_misses::total          425                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      9201754                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total      9201754                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      9201754                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total      9201754                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      9201754                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total      9201754                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.021500                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.021500                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.021500                       # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total     0.021500                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.021500                       # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total     0.021500                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21651.185882                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21651.185882                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21651.185882                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 21651.185882                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21651.185882                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 21651.185882                       # average overall mshr miss latency
-system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dcache.tags.replacements                     0                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse                26.191522                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs                   42135                       # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs                    28                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs               1504.821429                       # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data    26.191522                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.051155                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total        0.051155                       # Average percentage of cache occupancy
-system.cpu2.dcache.ReadReq_hits::cpu2.data        45549                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          45549                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        35887                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         35887                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data           12                       # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        81436                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           81436                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        81436                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          81436                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          344                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          344                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          143                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          143                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data           57                       # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          487                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           487                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          487                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          487                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      5599802                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total      5599802                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3105260                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      3105260                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       575007                       # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total       575007                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data      8705062                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total      8705062                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data      8705062                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total      8705062                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        45893                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        45893                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        36030                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        36030                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data           69                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        81923                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        81923                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        81923                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        81923                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.007496                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.007496                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.003969                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.003969                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.826087                       # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total     0.826087                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.005945                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.005945                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.005945                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.005945                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16278.494186                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 16278.494186                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21715.104895                       # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 21715.104895                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10087.842105                       # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total 10087.842105                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17874.870637                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 17874.870637                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17874.870637                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 17874.870637                       # average overall miss latency
-system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          182                       # number of ReadReq MSHR hits
-system.cpu2.dcache.ReadReq_mshr_hits::total          182                       # number of ReadReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           34                       # number of WriteReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::total           34                       # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits::cpu2.data          216                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_hits::total          216                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits::cpu2.data          216                       # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_hits::total          216                       # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          162                       # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total          162                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          109                       # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total          109                       # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           57                       # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total           57                       # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data          271                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total          271                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data          271                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total          271                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1526780                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1526780                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1514240                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1514240                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       460993                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total       460993                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3041020                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total      3041020                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3041020                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total      3041020                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003530                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003530                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.003025                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.003025                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.826087                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.826087                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003308                       # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total     0.003308                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003308                       # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total     0.003308                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  9424.567901                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  9424.567901                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13892.110092                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13892.110092                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  8087.596491                       # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  8087.596491                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11221.476015                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11221.476015                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11221.476015                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11221.476015                       # average overall mshr miss latency
-system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.branchPred.lookups                  56317                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted            53592                       # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect             1257                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups               50318                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits                  49441                       # Number of BTB hits
-system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct            98.257085                       # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS                    649                       # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
-system.cpu3.numCycles                          176970                       # number of cpu cycles simulated
-system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles             26467                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                        318235                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                      56317                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches             50090                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                       110248                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                   3629                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.BlockedCycles                 28039                       # Number of cycles fetch has spent blocked
-system.cpu3.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.NoActiveThreadStallCycles         7739                       # Number of stall cycles due to no active thread to fetch from
-system.cpu3.fetch.PendingTrapStallCycles          790                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines                    18199                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes                  258                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples            175582                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.812458                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.180606                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0                   65334     37.21%     37.21% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                   55610     31.67%     68.88% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                    5389      3.07%     71.95% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                    3177      1.81%     73.76% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                     669      0.38%     74.14% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                   40119     22.85%     96.99% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                    1237      0.70%     97.70% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                     753      0.43%     98.12% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                    3294      1.88%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total              175582                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.318229                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       1.798243                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles                   31057                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles                25106                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                   104911                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles                 4475                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles                  2294                       # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts                314540                       # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles                  2294                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles                   31713                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles                  12844                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles         11527                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                   100723                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles                 8742                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts                312369                       # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents                     1                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LSQFullEvents                   22                       # Number of times rename has blocked due to LSQ full
-system.cpu3.rename.RenamedOperands             219058                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups               604346                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups          604346                       # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps               206290                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                   12768                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts              1082                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts          1202                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                    11332                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads               90084                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores              43367                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads            42837                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores           38342                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                    260031                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded               5573                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                   261645                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued               62                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined          10424                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined        10297                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved           498                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples       175582                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        1.490158                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.307816                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0              62519     35.61%     35.61% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1              20435     11.64%     47.25% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2              43580     24.82%     72.07% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3              44218     25.18%     97.25% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4               3288      1.87%     99.12% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5               1176      0.67%     99.79% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6                257      0.15%     99.94% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7                 50      0.03%     99.97% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8                 59      0.03%    100.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total         175582                       # Number of insts issued each cycle
-system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                     17      6.25%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                     0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                      0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead                    45     16.54%     22.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite                  210     77.21%    100.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu               125105     47.81%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead               93850     35.87%     83.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite              42690     16.32%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total                261645                       # Type of FU issued
-system.cpu3.iq.rate                          1.478471                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                        272                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.001040                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads            699206                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes           276071                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses       259793                       # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses                261917                       # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads           38112                       # Number of loads that had data forwarded from stores
-system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads         2309                       # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation           43                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores         1414                       # Number of stores squashed
-system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles                  2294                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                    580                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles                   36                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts             309373                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts              369                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts                90084                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts               43367                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts              1034                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                    36                       # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents            43                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect           465                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect          904                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts                1369                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts               260458                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts                89199                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts             1187                       # Number of squashed instructions skipped in execute
-system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        43769                       # number of nop insts executed
-system.cpu3.iew.exec_refs                      131812                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                   53091                       # Number of branches executed
-system.cpu3.iew.exec_stores                     42613                       # Number of stores executed
-system.cpu3.iew.exec_rate                    1.471764                       # Inst execution rate
-system.cpu3.iew.wb_sent                        260118                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                       259793                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                   148532                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                   153197                       # num instructions consuming a value
-system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate                      1.468006                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.969549                       # average fanout of values written-back
-system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts          11915                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls           5075                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts             1257                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples       165549                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     1.796677                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     2.064793                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0        59727     36.08%     36.08% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1        51190     30.92%     67.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2         6085      3.68%     70.68% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3         6030      3.64%     74.32% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4         1572      0.95%     75.27% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5        38600     23.32%     98.58% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6          530      0.32%     98.90% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7         1000      0.60%     99.51% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8          815      0.49%    100.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total       165549                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts              297438                       # Number of instructions committed
-system.cpu3.commit.committedOps                297438                       # Number of ops (including micro ops) committed
-system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                        129728                       # Number of memory references committed
-system.cpu3.commit.loads                        87775                       # Number of loads committed
-system.cpu3.commit.membars                       4366                       # Number of memory barriers committed
-system.cpu3.commit.branches                     52284                       # Number of branches committed
-system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                   204138                       # Number of committed integer instructions.
-system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu3.commit.bw_lim_events                  815                       # number cycles where commit BW limit reached
-system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu3.rob.rob_reads                      473500                       # The number of ROB reads
-system.cpu3.rob.rob_writes                     621006                       # The number of ROB writes
-system.cpu3.timesIdled                            209                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                           1388                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                       44638                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                     249993                       # Number of Instructions Simulated
-system.cpu3.committedOps                       249993                       # Number of Ops (including micro ops) Simulated
-system.cpu3.committedInsts_total               249993                       # Number of Instructions Simulated
-system.cpu3.cpi                              0.707900                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        0.707900                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              1.412629                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        1.412629                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads                  453881                       # number of integer regfile reads
-system.cpu3.int_regfile_writes                 211087                       # number of integer regfile writes
-system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu3.misc_regfile_reads                 133368                       # number of misc regfile reads
-system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
-system.cpu3.icache.tags.replacements                   319                       # number of replacements
-system.cpu3.icache.tags.tagsinuse                77.348761                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs                   17724                       # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs                   430                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs                 41.218605                       # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst    77.348761                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.151072                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total        0.151072                       # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits::cpu3.inst        17724                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total          17724                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst        17724                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total           17724                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst        17724                       # number of overall hits
-system.cpu3.icache.overall_hits::total          17724                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          475                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          475                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          475                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           475                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          475                       # number of overall misses
-system.cpu3.icache.overall_misses::total          475                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      6467995                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total      6467995                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst      6467995                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total      6467995                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst      6467995                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total      6467995                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst        18199                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total        18199                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst        18199                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total        18199                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst        18199                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total        18199                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.026100                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.026100                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.026100                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.026100                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.026100                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.026100                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13616.831579                       # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 13616.831579                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13616.831579                       # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 13616.831579                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13616.831579                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 13616.831579                       # average overall miss latency
-system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           45                       # number of ReadReq MSHR hits
-system.cpu3.icache.ReadReq_mshr_hits::total           45                       # number of ReadReq MSHR hits
-system.cpu3.icache.demand_mshr_hits::cpu3.inst           45                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.demand_mshr_hits::total           45                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.overall_mshr_hits::cpu3.inst           45                       # number of overall MSHR hits
-system.cpu3.icache.overall_mshr_hits::total           45                       # number of overall MSHR hits
-system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          430                       # number of ReadReq MSHR misses
-system.cpu3.icache.ReadReq_mshr_misses::total          430                       # number of ReadReq MSHR misses
-system.cpu3.icache.demand_mshr_misses::cpu3.inst          430                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.demand_mshr_misses::total          430                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses::cpu3.inst          430                       # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_misses::total          430                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      5219755                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total      5219755                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5219755                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total      5219755                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5219755                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total      5219755                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.023628                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.023628                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.023628                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.023628                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.023628                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.023628                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12138.965116                       # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12138.965116                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12138.965116                       # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 12138.965116                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12138.965116                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 12138.965116                       # average overall mshr miss latency
-system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dcache.tags.replacements                     0                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse                23.659946                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs                   47957                       # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs                    28                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs               1712.750000                       # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data    23.659946                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.046211                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total        0.046211                       # Average percentage of cache occupancy
-system.cpu3.dcache.ReadReq_hits::cpu3.data        50723                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          50723                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        41752                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         41752                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data           12                       # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        92475                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           92475                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        92475                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          92475                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          346                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          346                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          138                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          138                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data           51                       # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total           51                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          484                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           484                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          484                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          484                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      4449419                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total      4449419                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2879011                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      2879011                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       478509                       # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total       478509                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data      7328430                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total      7328430                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data      7328430                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total      7328430                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        51069                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        51069                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        41890                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        41890                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data           63                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total           63                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        92959                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        92959                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        92959                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        92959                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.006775                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.006775                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.003294                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.003294                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.809524                       # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total     0.809524                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.005207                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.005207                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.005207                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.005207                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12859.592486                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 12859.592486                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20862.398551                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 20862.398551                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  9382.529412                       # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total  9382.529412                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15141.384298                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 15141.384298                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15141.384298                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 15141.384298                       # average overall miss latency
-system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          195                       # number of ReadReq MSHR hits
-system.cpu3.dcache.ReadReq_mshr_hits::total          195                       # number of ReadReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           32                       # number of WriteReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::total           32                       # number of WriteReq MSHR hits
-system.cpu3.dcache.demand_mshr_hits::cpu3.data          227                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.demand_mshr_hits::total          227                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.overall_mshr_hits::cpu3.data          227                       # number of overall MSHR hits
-system.cpu3.dcache.overall_mshr_hits::total          227                       # number of overall MSHR hits
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          151                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          151                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          106                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           51                       # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total           51                       # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data          257                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total          257                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data          257                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total          257                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1003763                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1003763                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1322239                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1322239                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       376491                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total       376491                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2326002                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total      2326002                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2326002                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total      2326002                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.002957                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.002957                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002530                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002530                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.809524                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.809524                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.002765                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.002765                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.002765                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.002765                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  6647.437086                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  6647.437086                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12473.952830                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12473.952830                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  7382.176471                       # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  7382.176471                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data  9050.591440                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total  9050.591440                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data  9050.591440                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total  9050.591440                       # average overall mshr miss latency
-system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                             0                       # number of replacements
-system.l2c.tags.tagsinuse                       416.979851                       # Cycle average of tags in use
-system.l2c.tags.total_refs                            1443                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                           526                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                          2.743346                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks            0.800256                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst           284.888559                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data            58.382327                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst             7.813679                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data             0.733163                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst            55.504569                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data             5.417548                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst             2.743977                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data             0.695773                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks           0.000012                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst            0.004347                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data            0.000891                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst            0.000119                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data            0.000011                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst            0.000847                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data            0.000083                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst            0.000042                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data            0.000011                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total                0.006363                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst                229                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst                412                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data                 11                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst                349                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data                  5                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst                421                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.data                 11                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                   1443                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
-system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
-system.l2c.demand_hits::cpu0.inst                 229                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                 412                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                  11                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                 349                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst                 421                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                    1443                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                229                       # number of overall hits
-system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                412                       # number of overall hits
-system.l2c.overall_hits::cpu1.data                 11                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                349                       # number of overall hits
-system.l2c.overall_hits::cpu2.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst                421                       # number of overall hits
-system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
-system.l2c.overall_hits::total                   1443                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst              359                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data               74                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst               16                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data                1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst               76                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data                7                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst                9                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                  543                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data            22                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data            16                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            18                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data            20                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                76                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data             12                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data             13                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst               359                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data               168                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst                16                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data                13                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst                76                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data                20                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst                 9                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                   674                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              359                       # number of overall misses
-system.l2c.overall_misses::cpu0.data              168                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst               16                       # number of overall misses
-system.l2c.overall_misses::cpu1.data               13                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst               76                       # number of overall misses
-system.l2c.overall_misses::cpu2.data               20                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst                9                       # number of overall misses
-system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
-system.l2c.overall_misses::total                  674                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst     24362500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data      5673000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst      1205500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data        88750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst      5263750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data       523750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.inst       570250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.data        88750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total       37776250                       # number of ReadReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data      7324500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data       823750                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data      1067249                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data       882250                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total     10097749                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst     24362500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data     12997500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst      1205500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data       912500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst      5263750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data      1590999                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst       570250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data       971000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total        47873999                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst     24362500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data     12997500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst      1205500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data       912500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst      5263750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data      1590999                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst       570250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data       971000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total       47873999                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst            588                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data             79                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst            428                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data             12                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst            425                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data             12                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst            430                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.data             12                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total               1986                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data           25                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data           16                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           18                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data           20                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              79                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data           12                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data           13                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             588                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data             173                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst             428                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data              24                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst             425                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data              25                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst             430                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data              24                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                2117                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst            588                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data            173                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst            428                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data             24                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst            425                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data             25                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst            430                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data             24                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               2117                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.610544                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.936709                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.037383                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.083333                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.178824                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.583333                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst      0.020930                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.data      0.083333                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.273414                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.880000                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.962025                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.610544                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.971098                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.037383                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.541667                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.178824                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.800000                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.020930                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.541667                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.318375                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.610544                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.971098                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.037383                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.541667                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.178824                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.800000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.020930                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.541667                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.318375                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67862.116992                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 76662.162162                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75343.750000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data        88750                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 69259.868421                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 74821.428571                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.inst 63361.111111                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.data        88750                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 69569.521179                       # average ReadReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77920.212766                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68645.833333                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82096.076923                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 73520.833333                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 77082.053435                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 67862.116992                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 77366.071429                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 75343.750000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 70192.307692                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 69259.868421                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 79549.950000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 63361.111111                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 74692.307692                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 71029.672107                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 67862.116992                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 77366.071429                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 75343.750000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 70192.307692                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 69259.868421                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 79549.950000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 63361.111111                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 74692.307692                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 71029.672107                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.ReadReq_mshr_hits::cpu0.inst             2                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst             6                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2.inst             3                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3.inst             3                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                14                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              6                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst              3                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.inst              3                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 14                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             6                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst             3                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.inst             3                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                14                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst          357                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data           74                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst           10                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst           73                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data            7                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.inst            6                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total             529                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data           22                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data           16                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data           18                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data           20                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total           76                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data           12                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data           13                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst          357                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data          168                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst           10                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data           13                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst           73                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data           20                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst            6                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.data           13                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total              660                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst          357                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data          168                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst           10                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data           13                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst           73                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data           20                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst            6                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total             660                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     19789750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data      4760500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst       695750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data        76250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst      4180000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data       436250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.inst       327500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.data        76250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total     30342250                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       220022                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       177515                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       180018                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       200020                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total       777575                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      6148500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       672250                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       907249                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       731250                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total      8459249                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst     19789750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data     10909000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst       695750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data       748500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst      4180000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data      1343499                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst       327500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data       807500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total     38801499                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst     19789750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data     10909000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst       695750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data       748500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst      4180000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data      1343499                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst       327500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data       807500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total     38801499                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.607143                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.936709                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.023364                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.083333                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.171765                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.583333                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.013953                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.083333                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.266365                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.880000                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.962025                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.607143                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.023364                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.541667                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.171765                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.800000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.013953                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.311762                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.607143                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.023364                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.541667                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.171765                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.800000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.013953                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.311762                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55433.473389                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64331.081081                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst        69575                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        76250                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57260.273973                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 54583.333333                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        76250                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 57357.750473                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 11094.687500                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65409.574468                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56020.833333                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69788.384615                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 60937.500000                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 64574.419847                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55433.473389                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64934.523810                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst        69575                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57576.923077                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57260.273973                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67174.950000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 54583.333333                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 62115.384615                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 58790.150000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55433.473389                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64934.523810                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst        69575                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57576.923077                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57260.273973                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67174.950000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 54583.333333                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 58790.150000                       # average overall mshr miss latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -27,14 +27,18 @@
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.slave[1]
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
 
 [system.cpu0]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer workload
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +57,10 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -65,10 +73,11 @@
 
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,22 +88,32 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -105,12 +124,21 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=SparcInterrupts
 
@@ -148,7 +176,7 @@
 children=dcache dtb icache interrupts isa itb tracer
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=1
 do_checkpoint_insts=true
 do_quiesce=true
@@ -167,6 +195,10 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -179,10 +211,11 @@
 
 [system.cpu1.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -193,22 +226,32 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
 
+[system.cpu1.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu1.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -219,12 +262,21 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
 
+[system.cpu1.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.interrupts]
 type=SparcInterrupts
 
@@ -243,7 +295,7 @@
 children=dcache dtb icache interrupts isa itb tracer
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=2
 do_checkpoint_insts=true
 do_quiesce=true
@@ -262,6 +314,10 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -274,10 +330,11 @@
 
 [system.cpu2.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -288,22 +345,32 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu2.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.dcache_port
 mem_side=system.toL2Bus.slave[5]
 
+[system.cpu2.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu2.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu2.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -314,12 +381,21 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu2.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.icache_port
 mem_side=system.toL2Bus.slave[4]
 
+[system.cpu2.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu2.interrupts]
 type=SparcInterrupts
 
@@ -338,7 +414,7 @@
 children=dcache dtb icache interrupts isa itb tracer
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=3
 do_checkpoint_insts=true
 do_quiesce=true
@@ -357,6 +433,10 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -369,10 +449,11 @@
 
 [system.cpu3.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -383,22 +464,32 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu3.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.dcache_port
 mem_side=system.toL2Bus.slave[7]
 
+[system.cpu3.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu3.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu3.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -409,12 +500,21 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu3.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.icache_port
 mem_side=system.toL2Bus.slave[6]
 
+[system.cpu3.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu3.interrupts]
 type=SparcInterrupts
 
@@ -428,12 +528,17 @@
 [system.cpu3.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -444,40 +549,50 @@
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[0]
+mem_side=system.membus.slave[1]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
 
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
-slave=system.l2c.mem_side system.system_port
+slave=system.system_port system.l2c.mem_side
 
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
-range=0:1073741823
-zero=false
+range=0:134217727
 port=system.membus.master[0]
 
 [system.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.l2c.cpu_side
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,2 +1,4 @@
-warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
+fatal: Can't load object file tests/test-progs/m5threads/bin/sparc/linux/test_atomic
+ @ cycle 0
+[create:build/SPARC/sim/process.cc, line 613]
+Memory Usage: 251848 KBytes
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,84 +1,8 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 16:09:53
-gem5 executing on ribera.cs.wisc.edu
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
+gem5 compiled Jul 17 2013 12:19:08
+gem5 started Jul 17 2013 12:19:20
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
 Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-Init done
-[Iteration 1, Thread 1] Got lock
-[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 1, Thread 2] Got lock
-[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2
-[Iteration 1, Thread 3] Got lock
-[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
-Iteration 1 completed
-[Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
-Iteration 2 completed
-[Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 3, Thread 1] Got lock
-[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1
-Iteration 3 completed
-[Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
-[Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2
-Iteration 4 completed
-[Iteration 5, Thread 3] Got lock
-[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
-Iteration 5 completed
-[Iteration 6, Thread 2] Got lock
-[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
-[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
-Iteration 6 completed
-[Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
-[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
-Iteration 7 completed
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
-[Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
-Iteration 8 completed
-[Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
-Iteration 9 completed
-[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
-[Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
-Iteration 10 completed
-PASSED :-)
-Exiting @ tick 87707000 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,736 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000088                       # Number of seconds simulated
-sim_ticks                                    87707000                       # Number of ticks simulated
-final_tick                                   87707000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1256528                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1256465                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              162691956                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1160656                       # Number of bytes of host memory used
-host_seconds                                     0.54                       # Real time elapsed on the host
-sim_insts                                      677327                       # Number of instructions simulated
-sim_ops                                        677327                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst            18048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data            10560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst             3968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data             1280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst              128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data              832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst              128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                35776                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst        18048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst         3968                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst          128                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst          128                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           22272                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst               282                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data               165                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst                62                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data                20                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst                 2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data                13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst                 2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   559                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst           205776050                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data           120400880                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            45241543                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data            14594046                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst             1459405                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             9486130                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst             1459405                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             9486130                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               407903588                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      205776050                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       45241543                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst        1459405                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst        1459405                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          253936402                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          205776050                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data          120400880                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           45241543                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data           14594046                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst            1459405                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            9486130                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst            1459405                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            9486130                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              407903588                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                    407903588                       # Throughput (bytes/s)
-system.membus.data_through_bus                  35776                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.toL2Bus.throughput                  1893577480                       # Throughput (bytes/s)
-system.toL2Bus.data_through_bus                166080                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus               0                       # Total snoop data (bytes)
-system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          175415                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                     175326                       # Number of instructions committed
-system.cpu0.committedOps                       175326                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses               120376                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                        390                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts        28824                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                      120376                       # number of integer instructions
-system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads             349286                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            121983                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                        82397                       # number of memory refs
-system.cpu0.num_load_insts                      54591                       # Number of load instructions
-system.cpu0.num_store_insts                     27806                       # Number of store instructions
-system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu0.num_busy_cycles                    175415                       # Number of busy cycles
-system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu0.icache.tags.replacements                   215                       # number of replacements
-system.cpu0.icache.tags.tagsinuse               222.772698                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs                  174921                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs                   467                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs                374.563169                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   222.772698                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.435103                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total        0.435103                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst       174921                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total         174921                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst       174921                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total          174921                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst       174921                       # number of overall hits
-system.cpu0.icache.overall_hits::total         174921                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           467                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          467                       # number of overall misses
-system.cpu0.icache.overall_misses::total          467                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst       175388                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total       175388                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst       175388                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total       175388                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst       175388                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total       175388                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002663                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.002663                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002663                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.002663                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002663                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.002663                       # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements                     2                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse               150.745494                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs                   81883                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs                   167                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs                490.317365                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   150.745494                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.294425                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total        0.294425                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data        54430                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          54430                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        27578                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         27578                       # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits::cpu0.data           15                       # number of SwapReq hits
-system.cpu0.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data        82008                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total           82008                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data        82008                       # number of overall hits
-system.cpu0.dcache.overall_hits::total          82008                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          151                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          151                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data          177                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total          177                       # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses::cpu0.data           27                       # number of SwapReq misses
-system.cpu0.dcache.SwapReq_misses::total           27                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data          328                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total           328                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data          328                       # number of overall misses
-system.cpu0.dcache.overall_misses::total          328                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        54581                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        54581                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        27755                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        27755                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data        82336                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total        82336                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data        82336                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total        82336                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.002767                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.002767                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006377                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.006377                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.642857                       # miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::total     0.642857                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.003984                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.003984                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.003984                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.003984                       # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
-system.cpu0.dcache.writebacks::total                1                       # number of writebacks
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                          173295                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                     167398                       # Number of instructions committed
-system.cpu1.committedOps                       167398                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses               109926                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                        633                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts        32743                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                      109926                       # number of integer instructions
-system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads             270038                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes            100721                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                        53394                       # number of memory refs
-system.cpu1.num_load_insts                      40652                       # Number of load instructions
-system.cpu1.num_store_insts                     12742                       # Number of store instructions
-system.cpu1.num_idle_cycles               7873.724337                       # Number of idle cycles
-system.cpu1.num_busy_cycles              165421.275663                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.954565                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.045435                       # Percentage of idle cycles
-system.cpu1.icache.tags.replacements                   278                       # number of replacements
-system.cpu1.icache.tags.tagsinuse                76.751702                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs                  167072                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs                   358                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs                466.681564                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst    76.751702                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.149906                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total        0.149906                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst       167072                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total         167072                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst       167072                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total          167072                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst       167072                       # number of overall hits
-system.cpu1.icache.overall_hits::total         167072                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          358                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          358                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          358                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           358                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          358                       # number of overall misses
-system.cpu1.icache.overall_misses::total          358                       # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst       167430                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total       167430                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst       167430                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total       167430                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst       167430                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total       167430                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002138                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.002138                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002138                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.002138                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002138                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.002138                       # miss rate for overall accesses
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements                     0                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse                30.316999                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs                   26731                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs                    26                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs               1028.115385                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data    30.316999                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.059213                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total        0.059213                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data        40470                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          40470                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        12563                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         12563                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data           14                       # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data        53033                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total           53033                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data        53033                       # number of overall hits
-system.cpu1.dcache.overall_hits::total          53033                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          174                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          174                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          106                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          106                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data           57                       # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          280                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           280                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          280                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          280                       # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        40644                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        40644                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        12669                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        12669                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data           71                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data        53313                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total        53313                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data        53313                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total        53313                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.004281                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.004281                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.008367                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.008367                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.802817                       # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total     0.802817                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.005252                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.005252                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.005252                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.005252                       # miss rate for overall accesses
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.numCycles                          173295                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                     167334                       # Number of instructions committed
-system.cpu2.committedOps                       167334                       # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses               113333                       # Number of integer alu accesses
-system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu2.num_func_calls                        633                       # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts        31007                       # number of instructions that are conditional controls
-system.cpu2.num_int_insts                      113333                       # number of integer instructions
-system.cpu2.num_fp_insts                            0                       # number of float instructions
-system.cpu2.num_int_register_reads             290613                       # number of times the integer registers were read
-system.cpu2.num_int_register_writes            109308                       # number of times the integer registers were written
-system.cpu2.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu2.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu2.num_mem_refs                        58537                       # number of memory refs
-system.cpu2.num_load_insts                      42362                       # Number of load instructions
-system.cpu2.num_store_insts                     16175                       # Number of store instructions
-system.cpu2.num_idle_cycles               7936.951217                       # Number of idle cycles
-system.cpu2.num_busy_cycles              165358.048783                       # Number of busy cycles
-system.cpu2.not_idle_fraction                0.954200                       # Percentage of non-idle cycles
-system.cpu2.idle_fraction                    0.045800                       # Percentage of idle cycles
-system.cpu2.icache.tags.replacements                   278                       # number of replacements
-system.cpu2.icache.tags.tagsinuse                74.781015                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs                  167008                       # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs                   358                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs                466.502793                       # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst    74.781015                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.146057                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total        0.146057                       # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits::cpu2.inst       167008                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total         167008                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst       167008                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total          167008                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst       167008                       # number of overall hits
-system.cpu2.icache.overall_hits::total         167008                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          358                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          358                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          358                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           358                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          358                       # number of overall misses
-system.cpu2.icache.overall_misses::total          358                       # number of overall misses
-system.cpu2.icache.ReadReq_accesses::cpu2.inst       167366                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total       167366                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst       167366                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total       167366                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst       167366                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total       167366                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002139                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.002139                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002139                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.002139                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002139                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.002139                       # miss rate for overall accesses
-system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dcache.tags.replacements                     0                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse                29.605505                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs                   33613                       # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs                    26                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs               1292.807692                       # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data    29.605505                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.057823                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total        0.057823                       # Average percentage of cache occupancy
-system.cpu2.dcache.ReadReq_hits::cpu2.data        42194                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          42194                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        15998                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         15998                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data           11                       # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total             11                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        58192                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           58192                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        58192                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          58192                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          160                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          160                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          109                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          109                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data           55                       # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          269                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           269                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          269                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          269                       # number of overall misses
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        42354                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        42354                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        16107                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        16107                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data           66                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total           66                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        58461                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        58461                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        58461                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        58461                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.003778                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.003778                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.006767                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.006767                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.833333                       # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total     0.833333                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.004601                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.004601                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.004601                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.004601                       # miss rate for overall accesses
-system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.numCycles                          173294                       # number of cpu cycles simulated
-system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.committedInsts                     167269                       # Number of instructions committed
-system.cpu3.committedOps                       167269                       # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses               111554                       # Number of integer alu accesses
-system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu3.num_func_calls                        633                       # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts        31865                       # number of instructions that are conditional controls
-system.cpu3.num_int_insts                      111554                       # number of integer instructions
-system.cpu3.num_fp_insts                            0                       # number of float instructions
-system.cpu3.num_int_register_reads             280060                       # number of times the integer registers were read
-system.cpu3.num_int_register_writes            104916                       # number of times the integer registers were written
-system.cpu3.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu3.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu3.num_mem_refs                        55900                       # number of memory refs
-system.cpu3.num_load_insts                      41466                       # Number of load instructions
-system.cpu3.num_store_insts                     14434                       # Number of store instructions
-system.cpu3.num_idle_cycles               8001.119846                       # Number of idle cycles
-system.cpu3.num_busy_cycles              165292.880154                       # Number of busy cycles
-system.cpu3.not_idle_fraction                0.953829                       # Percentage of non-idle cycles
-system.cpu3.idle_fraction                    0.046171                       # Percentage of idle cycles
-system.cpu3.icache.tags.replacements                   279                       # number of replacements
-system.cpu3.icache.tags.tagsinuse                72.874497                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs                  166942                       # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs                   359                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs                465.019499                       # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst    72.874497                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.142333                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total        0.142333                       # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits::cpu3.inst       166942                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total         166942                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst       166942                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total          166942                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst       166942                       # number of overall hits
-system.cpu3.icache.overall_hits::total         166942                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          359                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          359                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          359                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           359                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          359                       # number of overall misses
-system.cpu3.icache.overall_misses::total          359                       # number of overall misses
-system.cpu3.icache.ReadReq_accesses::cpu3.inst       167301                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total       167301                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst       167301                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total       167301                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst       167301                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total       167301                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002146                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.002146                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002146                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.002146                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002146                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.002146                       # miss rate for overall accesses
-system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dcache.tags.replacements                     0                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse                28.795404                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs                   30236                       # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs                    27                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs               1119.851852                       # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data    28.795404                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.056241                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total        0.056241                       # Average percentage of cache occupancy
-system.cpu3.dcache.ReadReq_hits::cpu3.data        41301                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          41301                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        14260                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         14260                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data           15                       # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        55561                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           55561                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        55561                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          55561                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          157                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          157                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          102                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          102                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data           55                       # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          259                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           259                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          259                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          259                       # number of overall misses
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        41458                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        41458                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        14362                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        14362                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data           70                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        55820                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        55820                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        55820                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        55820                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.003787                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.003787                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.007102                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.007102                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.785714                       # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total     0.785714                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.004640                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.004640                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.004640                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.004640                       # miss rate for overall accesses
-system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                             0                       # number of replacements
-system.l2c.tags.tagsinuse                       366.582542                       # Cycle average of tags in use
-system.l2c.tags.total_refs                            1220                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                           421                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                          2.897862                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks            0.966439                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst           239.426226                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data            55.207595                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst            59.511852                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data             6.721145                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst             1.930661                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data             0.935410                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst             0.977573                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data             0.905640                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks           0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst            0.003653                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data            0.000842                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst            0.000908                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data            0.000103                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst            0.000029                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data            0.000014                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst            0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data            0.000014                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total                0.005594                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst                185                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst                296                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data                  3                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst                356                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst                357                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                   1220                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
-system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data               2                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                   2                       # number of UpgradeReq hits
-system.l2c.demand_hits::cpu0.inst                 185                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                 296                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                   3                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                 356                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst                 357                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                    1220                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                185                       # number of overall hits
-system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                296                       # number of overall hits
-system.l2c.overall_hits::cpu1.data                  3                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                356                       # number of overall hits
-system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst                357                       # number of overall hits
-system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
-system.l2c.overall_hits::total                   1220                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst              282                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data               66                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst               62                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data                7                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst                2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data                1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst                2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                  423                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data            29                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data            18                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            19                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data            18                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                84                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total                136                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst               282                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data               165                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst                62                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data                20                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst                 2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data                13                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst                 2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                   559                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              282                       # number of overall misses
-system.l2c.overall_misses::cpu0.data              165                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst               62                       # number of overall misses
-system.l2c.overall_misses::cpu1.data               20                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst                2                       # number of overall misses
-system.l2c.overall_misses::cpu2.data               13                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst                2                       # number of overall misses
-system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
-system.l2c.overall_misses::total                  559                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.inst            467                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data             71                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst            358                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data             10                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst            358                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data             10                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst            359                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.data             10                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total               1643                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data           31                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data           18                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           19                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data           18                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              86                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total              136                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             467                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data             170                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst             358                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data              23                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst             358                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data              22                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst             359                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data              22                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                1779                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst            467                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data            170                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst            358                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data             23                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst            358                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data             22                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst            359                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data             22                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               1779                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.603854                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.929577                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.173184                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.700000                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.005587                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.100000                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst      0.005571                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.data      0.100000                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.257456                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.935484                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.976744                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.603854                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.970588                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.173184                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.869565                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.005587                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.590909                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.005571                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.590909                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.314221                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.603854                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.970588                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.173184                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.869565                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.005587                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.590909                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.005571                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.590909                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.314221                       # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -27,14 +27,18 @@
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.slave[1]
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
 
 [system.cpu0]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer workload
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +56,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu0.tracer
@@ -61,10 +66,11 @@
 
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,32 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +117,21 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=SparcInterrupts
 
@@ -144,7 +169,7 @@
 children=dcache dtb icache interrupts isa itb tracer
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=1
 do_checkpoint_insts=true
 do_quiesce=true
@@ -162,6 +187,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu1.tracer
@@ -171,10 +197,11 @@
 
 [system.cpu1.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -185,22 +212,32 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
 
+[system.cpu1.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu1.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -211,12 +248,21 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
 
+[system.cpu1.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.interrupts]
 type=SparcInterrupts
 
@@ -235,7 +281,7 @@
 children=dcache dtb icache interrupts isa itb tracer
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=2
 do_checkpoint_insts=true
 do_quiesce=true
@@ -253,6 +299,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu2.tracer
@@ -262,10 +309,11 @@
 
 [system.cpu2.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -276,22 +324,32 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu2.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.dcache_port
 mem_side=system.toL2Bus.slave[5]
 
+[system.cpu2.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu2.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu2.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -302,12 +360,21 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu2.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.icache_port
 mem_side=system.toL2Bus.slave[4]
 
+[system.cpu2.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu2.interrupts]
 type=SparcInterrupts
 
@@ -326,7 +393,7 @@
 children=dcache dtb icache interrupts isa itb tracer
 branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=3
 do_checkpoint_insts=true
 do_quiesce=true
@@ -344,6 +411,7 @@
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu3.tracer
@@ -353,10 +421,11 @@
 
 [system.cpu3.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -367,22 +436,32 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu3.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.dcache_port
 mem_side=system.toL2Bus.slave[7]
 
+[system.cpu3.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu3.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu3.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -393,12 +472,21 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu3.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.icache_port
 mem_side=system.toL2Bus.slave[6]
 
+[system.cpu3.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu3.interrupts]
 type=SparcInterrupts
 
@@ -412,12 +500,17 @@
 [system.cpu3.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -428,40 +521,48 @@
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[0]
+mem_side=system.membus.slave[1]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
 
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 master=system.physmem.port
-slave=system.l2c.mem_side system.system_port
+slave=system.system_port system.l2c.mem_side
 
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
 [system.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,2 +1,4 @@
-warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
+fatal: Can't load object file tests/test-progs/m5threads/bin/sparc/linux/test_atomic
+ @ cycle 0
+[create:build/SPARC/sim/process.cc, line 613]
+Memory Usage: 251848 KBytes
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,84 +1,8 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:04:14
-gem5 started Mar 26 2013 15:04:37
-gem5 executing on ribera.cs.wisc.edu
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
+gem5 compiled Jul 17 2013 12:19:08
+gem5 started Jul 17 2013 12:19:20
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
 Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-Init done
-[Iteration 1, Thread 1] Got lock
-[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 1, Thread 3] Got lock
-[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
-[Iteration 1, Thread 2] Got lock
-[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2
-Iteration 1 completed
-[Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
-Iteration 2 completed
-[Iteration 3, Thread 1] Got lock
-[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3
-[Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
-Iteration 3 completed
-[Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
-[Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
-Iteration 4 completed
-[Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 5, Thread 3] Got lock
-[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
-Iteration 5 completed
-[Iteration 6, Thread 2] Got lock
-[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
-[Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1
-Iteration 6 completed
-[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
-[Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
-Iteration 7 completed
-[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
-Iteration 8 completed
-[Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3
-[Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
-Iteration 9 completed
-[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
-[Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
-Iteration 10 completed
-PASSED :-)
-Exiting @ tick 262970500 because target called exit()
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,1407 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000263                       # Number of seconds simulated
-sim_ticks                                   262794500                       # Number of ticks simulated
-final_tick                                  262794500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 146225                       # Simulator instruction rate (inst/s)
-host_op_rate                                   146224                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               57909206                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 244388                       # Number of bytes of host memory used
-host_seconds                                     4.54                       # Real time elapsed on the host
-sim_insts                                      663567                       # Number of instructions simulated
-sim_ops                                        663567                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst            18240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data            10560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst             3776                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data             1408                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst              128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data              960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst              512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data             1024                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                36608                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst        18240                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst         3776                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst          128                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst          512                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           22656                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst               285                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data               165                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst                59                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data                22                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst                 2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data                15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst                 8                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data                16                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   572                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst            69407845                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            40183489                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            14368642                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             5357799                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              487073                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             3653044                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst             1948290                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             3896581                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               139302763                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst       69407845                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       14368642                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         487073                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst        1948290                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           86211850                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst           69407845                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           40183489                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           14368642                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            5357799                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             487073                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            3653044                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst            1948290                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            3896581                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              139302763                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                    139302763                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 430                       # Transaction distribution
-system.membus.trans_dist::ReadResp                430                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              272                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              77                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               208                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              142                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side         1559                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count                          1559                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side        36608                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size                      36608                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                  36608                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              852296                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            5420500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              2.1                       # Layer utilization (%)
-system.toL2Bus.throughput                   646588875                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq               2225                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp              2225                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback                1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq             274                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp            274                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq              429                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp             429                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side          934                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side          580                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side          732                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side          355                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side          732                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side          352                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side          734                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side          401                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count                         4820                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side        29888                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side        10944                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side        23424                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side         1664                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side        23424                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side         1600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side        23488                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side         1600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size                    116032                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus                116032                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus           53888                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy            1473490                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.6                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy           2101500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.8                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy           1430481                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.5                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy           1650488                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.6                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy           1157483                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy           1651988                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization             0.6                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy           1147981                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization             0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy           1651999                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization             0.6                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy           1327473                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization             0.5                       # Layer utilization (%)
-system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          525589                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                     158574                       # Number of instructions committed
-system.cpu0.committedOps                       158574                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses               109208                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                        390                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts        26032                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                      109208                       # number of integer instructions
-system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads             315782                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            110814                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                        74021                       # number of memory refs
-system.cpu0.num_load_insts                      49007                       # Number of load instructions
-system.cpu0.num_store_insts                     25014                       # Number of store instructions
-system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu0.num_busy_cycles                    525589                       # Number of busy cycles
-system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu0.icache.tags.replacements                   215                       # number of replacements
-system.cpu0.icache.tags.tagsinuse               212.401822                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs                  158170                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs                   467                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs                338.693790                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   212.401822                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.414847                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total        0.414847                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst       158170                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total         158170                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst       158170                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total          158170                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst       158170                       # number of overall hits
-system.cpu0.icache.overall_hits::total         158170                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           467                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          467                       # number of overall misses
-system.cpu0.icache.overall_misses::total          467                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     18148000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     18148000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     18148000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     18148000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     18148000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     18148000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst       158637                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total       158637                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst       158637                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total       158637                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst       158637                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total       158637                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002944                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.002944                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002944                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.002944                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002944                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.002944                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38860.813704                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 38860.813704                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38860.813704                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 38860.813704                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38860.813704                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 38860.813704                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          467                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total          467                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst          467                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total          467                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst          467                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total          467                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     17214000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     17214000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     17214000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     17214000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     17214000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     17214000                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.002944                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.002944                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.002944                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.002944                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.002944                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.002944                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36860.813704                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36860.813704                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36860.813704                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 36860.813704                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704                       # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements                     2                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse               145.571924                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs                   73489                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs                   167                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs                440.053892                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   145.571924                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.284320                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total        0.284320                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data        48827                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          48827                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        24780                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         24780                       # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits::cpu0.data           16                       # number of SwapReq hits
-system.cpu0.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data        73607                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total           73607                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data        73607                       # number of overall hits
-system.cpu0.dcache.overall_hits::total          73607                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          170                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          170                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data          183                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total          183                       # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses::cpu0.data           26                       # number of SwapReq misses
-system.cpu0.dcache.SwapReq_misses::total           26                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data          353                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total           353                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data          353                       # number of overall misses
-system.cpu0.dcache.overall_misses::total          353                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data      4586981                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total      4586981                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      6974000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total      6974000                       # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       360500                       # number of SwapReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::total       360500                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     11560981                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     11560981                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     11560981                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     11560981                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        48997                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        48997                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        24963                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        24963                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data        73960                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total        73960                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data        73960                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total        73960                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.003470                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.003470                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007331                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.007331                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.619048                       # miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::total     0.619048                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.004773                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.004773                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.004773                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.004773                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26982.241176                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 26982.241176                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38109.289617                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 38109.289617                       # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615                       # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32750.654391                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 32750.654391                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32750.654391                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 32750.654391                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
-system.cpu0.dcache.writebacks::total                1                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          170                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total          170                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          183                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total          183                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           26                       # number of SwapReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::total           26                       # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data          353                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total          353                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data          353                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total          353                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4237019                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4237019                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6608000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6608000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       308500                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::total       308500                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     10845019                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     10845019                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     10845019                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     10845019                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.003470                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.003470                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.007331                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007331                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.619048                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.619048                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.004773                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.004773                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.004773                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.004773                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24923.641176                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24923.641176                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36109.289617                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36109.289617                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615                       # average SwapReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30722.433428                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30722.433428                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30722.433428                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30722.433428                       # average overall mshr miss latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                          525588                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                     163471                       # Number of instructions committed
-system.cpu1.committedOps                       163471                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses               111731                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                        637                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts        29880                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                      111731                       # number of integer instructions
-system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads             289610                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes            111151                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                        58020                       # number of memory refs
-system.cpu1.num_load_insts                      41540                       # Number of load instructions
-system.cpu1.num_store_insts                     16480                       # Number of store instructions
-system.cpu1.num_idle_cycles              69347.869793                       # Number of idle cycles
-system.cpu1.num_busy_cycles              456240.130207                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.868057                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.131943                       # Percentage of idle cycles
-system.cpu1.icache.tags.replacements                   280                       # number of replacements
-system.cpu1.icache.tags.tagsinuse                70.017506                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs                  163138                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs                   366                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs                445.732240                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst    70.017506                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.136753                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total        0.136753                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst       163138                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total         163138                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst       163138                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total          163138                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst       163138                       # number of overall hits
-system.cpu1.icache.overall_hits::total         163138                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          366                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          366                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          366                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           366                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          366                       # number of overall misses
-system.cpu1.icache.overall_misses::total          366                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      7546988                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total      7546988                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst      7546988                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total      7546988                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst      7546988                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total      7546988                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst       163504                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total       163504                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst       163504                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total       163504                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst       163504                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total       163504                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002238                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.002238                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002238                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.002238                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002238                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.002238                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20620.185792                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 20620.185792                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20620.185792                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 20620.185792                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20620.185792                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 20620.185792                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          366                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst          366                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst          366                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      6808012                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total      6808012                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      6808012                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total      6808012                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      6808012                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total      6808012                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.002238                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.002238                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.002238                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.002238                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.002238                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.002238                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18601.125683                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18601.125683                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18601.125683                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 18601.125683                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18601.125683                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 18601.125683                       # average overall mshr miss latency
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements                     0                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse                27.720196                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs                   35348                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs                    30                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs               1178.266667                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data    27.720196                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.054141                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total        0.054141                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data        41378                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          41378                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        16307                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         16307                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data           11                       # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total             11                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data        57685                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total           57685                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data        57685                       # number of overall hits
-system.cpu1.dcache.overall_hits::total          57685                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          154                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          154                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          109                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          109                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data           51                       # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total           51                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          263                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           263                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          263                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          263                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      2495483                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total      2495483                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      1980000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      1980000                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       209500                       # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total       209500                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data      4475483                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total      4475483                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data      4475483                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total      4475483                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        41532                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        41532                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        16416                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        16416                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data           62                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total           62                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data        57948                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total        57948                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data        57948                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total        57948                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.003708                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.003708                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.006640                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.006640                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.822581                       # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total     0.822581                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.004539                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.004539                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.004539                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.004539                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16204.435065                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16204.435065                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18165.137615                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 18165.137615                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  4107.843137                       # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total  4107.843137                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17017.045627                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 17017.045627                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17017.045627                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 17017.045627                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          154                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          154                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          109                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total          109                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           51                       # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total           51                       # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data          263                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total          263                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data          263                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total          263                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2170517                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2170517                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1762000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1762000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       107500                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total       107500                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3932517                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total      3932517                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3932517                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total      3932517                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003708                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003708                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.006640                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.006640                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.822581                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.822581                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.004539                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.004539                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.004539                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.004539                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14094.266234                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14094.266234                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16165.137615                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16165.137615                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  2107.843137                       # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  2107.843137                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14952.536122                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14952.536122                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14952.536122                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14952.536122                       # average overall mshr miss latency
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.numCycles                          525588                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                     164866                       # Number of instructions committed
-system.cpu2.committedOps                       164866                       # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses               112988                       # Number of integer alu accesses
-system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu2.num_func_calls                        637                       # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts        29949                       # number of instructions that are conditional controls
-system.cpu2.num_int_insts                      112988                       # number of integer instructions
-system.cpu2.num_fp_insts                            0                       # number of float instructions
-system.cpu2.num_int_register_reads             294363                       # number of times the integer registers were read
-system.cpu2.num_int_register_writes            112900                       # number of times the integer registers were written
-system.cpu2.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu2.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu2.num_mem_refs                        59208                       # number of memory refs
-system.cpu2.num_load_insts                      42171                       # Number of load instructions
-system.cpu2.num_store_insts                     17037                       # Number of store instructions
-system.cpu2.num_idle_cycles              69604.869303                       # Number of idle cycles
-system.cpu2.num_busy_cycles              455983.130697                       # Number of busy cycles
-system.cpu2.not_idle_fraction                0.867568                       # Percentage of non-idle cycles
-system.cpu2.idle_fraction                    0.132432                       # Percentage of idle cycles
-system.cpu2.icache.tags.replacements                   280                       # number of replacements
-system.cpu2.icache.tags.tagsinuse                67.624969                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs                  164533                       # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs                   366                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs                449.543716                       # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst    67.624969                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.132080                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total        0.132080                       # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits::cpu2.inst       164533                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total         164533                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst       164533                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total          164533                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst       164533                       # number of overall hits
-system.cpu2.icache.overall_hits::total         164533                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          366                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          366                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          366                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           366                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          366                       # number of overall misses
-system.cpu2.icache.overall_misses::total          366                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      5255488                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total      5255488                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst      5255488                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total      5255488                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst      5255488                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total      5255488                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst       164899                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total       164899                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst       164899                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total       164899                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst       164899                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total       164899                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002220                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.002220                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002220                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.002220                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002220                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.002220                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14359.256831                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 14359.256831                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14359.256831                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 14359.256831                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14359.256831                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 14359.256831                       # average overall miss latency
-system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          366                       # number of ReadReq MSHR misses
-system.cpu2.icache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses::cpu2.inst          366                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses::cpu2.inst          366                       # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      4513512                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total      4513512                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      4513512                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total      4513512                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      4513512                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total      4513512                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.002220                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.002220                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.002220                       # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total     0.002220                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.002220                       # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total     0.002220                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst        12332                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total        12332                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst        12332                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total        12332                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst        12332                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total        12332                       # average overall mshr miss latency
-system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dcache.tags.replacements                     0                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse                26.763892                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs                   36347                       # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs                    29                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs               1253.344828                       # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data    26.763892                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.052273                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total        0.052273                       # Average percentage of cache occupancy
-system.cpu2.dcache.ReadReq_hits::cpu2.data        42011                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          42011                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        16865                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         16865                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data           10                       # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total             10                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        58876                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           58876                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        58876                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          58876                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          152                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          152                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          110                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          110                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data           50                       # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total           50                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          262                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           262                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          262                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          262                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      2129481                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total      2129481                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      1930500                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      1930500                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       204500                       # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total       204500                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data      4059981                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total      4059981                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data      4059981                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total      4059981                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        42163                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        42163                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        16975                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        16975                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data           60                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total           60                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        59138                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        59138                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        59138                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        59138                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.003605                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.003605                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.006480                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.006480                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.833333                       # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total     0.833333                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.004430                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.004430                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.004430                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.004430                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14009.743421                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 14009.743421                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data        17550                       # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total        17550                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data         4090                       # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total         4090                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15496.110687                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 15496.110687                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15496.110687                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 15496.110687                       # average overall miss latency
-system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          152                       # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total          152                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          110                       # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total          110                       # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           50                       # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total           50                       # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data          262                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total          262                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data          262                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total          262                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1809519                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1809519                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1710500                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1710500                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       104500                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total       104500                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3520019                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total      3520019                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3520019                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total      3520019                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003605                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003605                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.006480                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.006480                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.833333                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.833333                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.004430                       # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total     0.004430                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.004430                       # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total     0.004430                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11904.730263                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11904.730263                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data        15550                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total        15550                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data         2090                       # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total         2090                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13435.187023                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13435.187023                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13435.187023                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13435.187023                       # average overall mshr miss latency
-system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.numCycles                          525588                       # number of cpu cycles simulated
-system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.committedInsts                     176656                       # Number of instructions committed
-system.cpu3.committedOps                       176656                       # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses               108218                       # Number of integer alu accesses
-system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu3.num_func_calls                        637                       # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts        38223                       # number of instructions that are conditional controls
-system.cpu3.num_int_insts                      108218                       # number of integer instructions
-system.cpu3.num_fp_insts                            0                       # number of float instructions
-system.cpu3.num_int_register_reads             242179                       # number of times the integer registers were read
-system.cpu3.num_int_register_writes             89182                       # number of times the integer registers were written
-system.cpu3.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu3.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu3.num_mem_refs                        46164                       # number of memory refs
-system.cpu3.num_load_insts                      39753                       # Number of load instructions
-system.cpu3.num_store_insts                      6411                       # Number of store instructions
-system.cpu3.num_idle_cycles              69869.868798                       # Number of idle cycles
-system.cpu3.num_busy_cycles              455718.131202                       # Number of busy cycles
-system.cpu3.not_idle_fraction                0.867063                       # Percentage of non-idle cycles
-system.cpu3.idle_fraction                    0.132937                       # Percentage of idle cycles
-system.cpu3.icache.tags.replacements                   281                       # number of replacements
-system.cpu3.icache.tags.tagsinuse                65.598437                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs                  176322                       # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs                   367                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs                480.441417                       # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst    65.598437                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.128122                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total        0.128122                       # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits::cpu3.inst       176322                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total         176322                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst       176322                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total          176322                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst       176322                       # number of overall hits
-system.cpu3.icache.overall_hits::total         176322                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          367                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          367                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          367                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           367                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          367                       # number of overall misses
-system.cpu3.icache.overall_misses::total          367                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      5147499                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total      5147499                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst      5147499                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total      5147499                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst      5147499                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total      5147499                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst       176689                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total       176689                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst       176689                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total       176689                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst       176689                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total       176689                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002077                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.002077                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002077                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.002077                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002077                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.002077                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14025.882834                       # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 14025.882834                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14025.882834                       # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 14025.882834                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14025.882834                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 14025.882834                       # average overall miss latency
-system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          367                       # number of ReadReq MSHR misses
-system.cpu3.icache.ReadReq_mshr_misses::total          367                       # number of ReadReq MSHR misses
-system.cpu3.icache.demand_mshr_misses::cpu3.inst          367                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.demand_mshr_misses::total          367                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses::cpu3.inst          367                       # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_misses::total          367                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      4412501                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total      4412501                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      4412501                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total      4412501                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      4412501                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total      4412501                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.002077                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.002077                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.002077                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.002077                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.002077                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.002077                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12023.163488                       # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12023.163488                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12023.163488                       # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 12023.163488                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488                       # average overall mshr miss latency
-system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dcache.tags.replacements                     0                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse                25.915086                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs                   15020                       # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs                    29                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs                517.931034                       # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data    25.915086                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.050615                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total        0.050615                       # Average percentage of cache occupancy
-system.cpu3.dcache.ReadReq_hits::cpu3.data        39563                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          39563                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data         6216                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total          6216                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data           19                       # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total             19                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        45779                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           45779                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        45779                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          45779                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          183                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          183                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          105                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          105                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data           69                       # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total           69                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          288                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           288                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          288                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          288                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      3156473                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total      3156473                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2098500                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      2098500                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       280000                       # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total       280000                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data      5254973                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total      5254973                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data      5254973                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total      5254973                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        39746                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        39746                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data         6321                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total         6321                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data           88                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total           88                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        46067                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        46067                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        46067                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        46067                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.004604                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.004604                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.016611                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.016611                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.784091                       # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total     0.784091                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.006252                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.006252                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.006252                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.006252                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17248.486339                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 17248.486339                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19985.714286                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 19985.714286                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  4057.971014                       # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total  4057.971014                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18246.434028                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 18246.434028                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18246.434028                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 18246.434028                       # average overall miss latency
-system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          183                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          183                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          105                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           69                       # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total           69                       # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data          288                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total          288                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data          288                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total          288                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      2772527                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total      2772527                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1888500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1888500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       142000                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total       142000                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      4661027                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total      4661027                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      4661027                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total      4661027                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.004604                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.004604                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.016611                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.016611                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.784091                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.784091                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.006252                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.006252                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.006252                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.006252                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15150.420765                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15150.420765                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17985.714286                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17985.714286                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  2057.971014                       # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  2057.971014                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16184.121528                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16184.121528                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16184.121528                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16184.121528                       # average overall mshr miss latency
-system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                             0                       # number of replacements
-system.l2c.tags.tagsinuse                       349.046072                       # Cycle average of tags in use
-system.l2c.tags.total_refs                            1220                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                           429                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                          2.843823                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks            0.889005                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst           231.790437                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data            54.207948                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst            51.556673                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data             6.123914                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst             1.773020                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data             0.843760                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst             1.030292                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data             0.831024                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks           0.000014                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst            0.003537                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data            0.000827                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst            0.000787                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data            0.000093                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst            0.000027                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data            0.000013                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst            0.000016                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data            0.000013                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total                0.005326                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst                182                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst                300                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data                  3                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst                354                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst                358                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                   1220                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
-system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data               2                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                   2                       # number of UpgradeReq hits
-system.l2c.demand_hits::cpu0.inst                 182                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                 300                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                   3                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                 354                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst                 358                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                    1220                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                182                       # number of overall hits
-system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                300                       # number of overall hits
-system.l2c.overall_hits::cpu1.data                  3                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                354                       # number of overall hits
-system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst                358                       # number of overall hits
-system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
-system.l2c.overall_hits::total                   1220                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst              285                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data               66                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst               66                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data                8                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst               12                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data                2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst                9                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.data                2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                  450                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data            28                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data            15                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            15                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data            19                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                77                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data             15                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data             14                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data             14                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total                142                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst               285                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data               165                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst                66                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data                23                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst                12                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data                16                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst                 9                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data                16                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                   592                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              285                       # number of overall misses
-system.l2c.overall_misses::cpu0.data              165                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst               66                       # number of overall misses
-system.l2c.overall_misses::cpu1.data               23                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst               12                       # number of overall misses
-system.l2c.overall_misses::cpu2.data               16                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst                9                       # number of overall misses
-system.l2c.overall_misses::cpu3.data               16                       # number of overall misses
-system.l2c.overall_misses::total                  592                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst     14927000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data      3451500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst      3436500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data       418500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst       597500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data       103500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.inst       465000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.data       104500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total       23504000                       # number of ReadReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data      5174000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data       801000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data       747000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data       730000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total      7452000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst     14927000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data      8625500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst      3436500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data      1219500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst       597500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data       850500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst       465000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data       834500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total        30956000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst     14927000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data      8625500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst      3436500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data      1219500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst       597500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data       850500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst       465000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data       834500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total       30956000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst            467                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data             71                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst            366                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data             11                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst            366                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data             11                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst            367                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.data             11                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total               1670                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data           30                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data           15                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           15                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data           19                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              79                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data           15                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data           14                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data           14                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total              142                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             467                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data             170                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst             366                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data              26                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst             366                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data              25                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst             367                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data              25                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                1812                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst            467                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data            170                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst            366                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data             26                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst            366                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data             25                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst            367                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data             25                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               1812                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.610278                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.929577                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.180328                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.727273                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.032787                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.181818                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst      0.024523                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.data      0.181818                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.269461                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.933333                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.974684                       # miss rate for UpgradeReq accesses
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-system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.610278                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.970588                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.180328                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.884615                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.032787                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.640000                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.024523                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.640000                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.326711                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.610278                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.970588                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.180328                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.884615                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.032787                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.640000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.024523                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.640000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.326711                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545                       # average ReadReq miss latency
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-system.l2c.ReadReq_avg_miss_latency::cpu1.data 52312.500000                       # average ReadReq miss latency
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-system.l2c.ReadReq_avg_miss_latency::cpu2.data        51750                       # average ReadReq miss latency
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-system.l2c.ReadReq_avg_miss_latency::cpu3.data        52250                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52231.111111                       # average ReadReq miss latency
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-system.l2c.ReadExReq_avg_miss_latency::cpu1.data        53400                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53357.142857                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.857143                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52478.873239                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 52068.181818                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 53021.739130                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 49791.666667                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 53156.250000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 52156.250000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52290.540541                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.data 53021.739130                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu2.data 53156.250000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 52156.250000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52290.540541                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
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-system.l2c.ReadReq_mshr_hits::total                20                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
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-system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
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-system.l2c.overall_mshr_hits::total                20                       # number of overall MSHR hits
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-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.929577                       # mshr miss rate for ReadReq accesses
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-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.636364                       # mshr miss rate for ReadReq accesses
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-system.l2c.ReadReq_mshr_miss_rate::total     0.257485                       # mshr miss rate for ReadReq accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::total     0.974684                       # mshr miss rate for UpgradeReq accesses
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-system.l2c.demand_mshr_miss_rate::cpu1.data     0.846154                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu2.data     0.600000                       # mshr miss rate for demand accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.data     0.846154                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu2.data     0.600000                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::total     0.315673                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40050.877193                       # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        40000                       # average ReadReq mshr miss latency
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-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        40000                       # average UpgradeReq mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545                       # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu3.data        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40108.391608                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40108.391608                       # average overall mshr miss latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,15 +8,15 @@
 
 [system]
 type=System
-children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcbus funcmem physmem ruby sys_port_proxy
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcbus funcmem physmem ruby sys_port_proxy
 boot_osflags=a
-clock=1
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
 mem_mode=timing
 mem_ranges=
-memories=system.funcmem system.physmem
+memories=system.physmem system.funcmem
 num_work_ids=16
 readfile=
 symbolfile=
@@ -29,10 +29,14 @@
 work_item_id=-1
 system_port=system.sys_port_proxy.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1
+
 [system.cpu0]
 type=MemTest
 atomic=false
-clock=1
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -51,7 +55,7 @@
 [system.cpu1]
 type=MemTest
 atomic=false
-clock=1
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -70,7 +74,7 @@
 [system.cpu2]
 type=MemTest
 atomic=false
-clock=1
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -89,7 +93,7 @@
 [system.cpu3]
 type=MemTest
 atomic=false
-clock=1
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -108,7 +112,7 @@
 [system.cpu4]
 type=MemTest
 atomic=false
-clock=1
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -127,7 +131,7 @@
 [system.cpu5]
 type=MemTest
 atomic=false
-clock=1
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -146,7 +150,7 @@
 [system.cpu6]
 type=MemTest
 atomic=false
-clock=1
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -165,7 +169,7 @@
 [system.cpu7]
 type=MemTest
 atomic=false
-clock=1
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -181,10 +185,14 @@
 functional=system.funcbus.slave[7]
 test=system.ruby.l1_cntrl7.sequencer.slave[0]
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=1
+
 [system.funcbus]
 type=NoncoherentBus
 block_size=64
-clock=1
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=false
 width=8
@@ -194,44 +202,46 @@
 [system.funcmem]
 type=SimpleMemory
 bandwidth=0.000000
-clock=1
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=false
 latency=30
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.funcbus.master[0]
 
 [system.physmem]
 type=SimpleMemory
 bandwidth=0.000000
-clock=1
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30
 latency_var=0
 null=true
 range=0:134217727
-zero=false
 
 [system.ruby]
 type=RubySystem
-children=dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 memctrl_clk_domain network profiler
 block_size_bytes=64
-clock=1
+clk_domain=system.ruby.clk_domain
 mem_size=268435456
 no_mem_vec=false
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
 
+[system.ruby.clk_domain]
+type=SrcClockDomain
+clock=1
+
 [system.ruby.dir_cntrl0]
 type=Directory_Controller
 children=directory memBuffer
 buffer_size=0
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=8
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
@@ -258,7 +268,7 @@
 bank_queue_size=12
 banks_per_rank=8
 basic_bus_busy_time=2
-clock=3
+clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
 mem_ctl_latency=12
@@ -279,7 +289,7 @@
 buffer_size=0
 cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=0
 issue_latency=2
 number_of_TBEs=256
@@ -308,7 +318,7 @@
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
 access_phys_mem=false
-clock=1
+clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=1000000
 icache=system.ruby.l1_cntrl0.cacheMemory
@@ -328,7 +338,7 @@
 buffer_size=0
 cacheMemory=system.ruby.l1_cntrl1.cacheMemory
 cache_response_latency=12
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=1
 issue_latency=2
 number_of_TBEs=256
@@ -357,7 +367,7 @@
 [system.ruby.l1_cntrl1.sequencer]
 type=RubySequencer
 access_phys_mem=false
-clock=1
+clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl1.cacheMemory
 deadlock_threshold=1000000
 icache=system.ruby.l1_cntrl1.cacheMemory
@@ -377,7 +387,7 @@
 buffer_size=0
 cacheMemory=system.ruby.l1_cntrl2.cacheMemory
 cache_response_latency=12
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=2
 issue_latency=2
 number_of_TBEs=256
@@ -406,7 +416,7 @@
 [system.ruby.l1_cntrl2.sequencer]
 type=RubySequencer
 access_phys_mem=false
-clock=1
+clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl2.cacheMemory
 deadlock_threshold=1000000
 icache=system.ruby.l1_cntrl2.cacheMemory
@@ -426,7 +436,7 @@
 buffer_size=0
 cacheMemory=system.ruby.l1_cntrl3.cacheMemory
 cache_response_latency=12
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=3
 issue_latency=2
 number_of_TBEs=256
@@ -455,7 +465,7 @@
 [system.ruby.l1_cntrl3.sequencer]
 type=RubySequencer
 access_phys_mem=false
-clock=1
+clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl3.cacheMemory
 deadlock_threshold=1000000
 icache=system.ruby.l1_cntrl3.cacheMemory
@@ -475,7 +485,7 @@
 buffer_size=0
 cacheMemory=system.ruby.l1_cntrl4.cacheMemory
 cache_response_latency=12
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=4
 issue_latency=2
 number_of_TBEs=256
@@ -504,7 +514,7 @@
 [system.ruby.l1_cntrl4.sequencer]
 type=RubySequencer
 access_phys_mem=false
-clock=1
+clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl4.cacheMemory
 deadlock_threshold=1000000
 icache=system.ruby.l1_cntrl4.cacheMemory
@@ -524,7 +534,7 @@
 buffer_size=0
 cacheMemory=system.ruby.l1_cntrl5.cacheMemory
 cache_response_latency=12
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=5
 issue_latency=2
 number_of_TBEs=256
@@ -553,7 +563,7 @@
 [system.ruby.l1_cntrl5.sequencer]
 type=RubySequencer
 access_phys_mem=false
-clock=1
+clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl5.cacheMemory
 deadlock_threshold=1000000
 icache=system.ruby.l1_cntrl5.cacheMemory
@@ -573,7 +583,7 @@
 buffer_size=0
 cacheMemory=system.ruby.l1_cntrl6.cacheMemory
 cache_response_latency=12
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=6
 issue_latency=2
 number_of_TBEs=256
@@ -602,7 +612,7 @@
 [system.ruby.l1_cntrl6.sequencer]
 type=RubySequencer
 access_phys_mem=false
-clock=1
+clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl6.cacheMemory
 deadlock_threshold=1000000
 icache=system.ruby.l1_cntrl6.cacheMemory
@@ -622,7 +632,7 @@
 buffer_size=0
 cacheMemory=system.ruby.l1_cntrl7.cacheMemory
 cache_response_latency=12
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=7
 issue_latency=2
 number_of_TBEs=256
@@ -651,7 +661,7 @@
 [system.ruby.l1_cntrl7.sequencer]
 type=RubySequencer
 access_phys_mem=false
-clock=1
+clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl7.cacheMemory
 deadlock_threshold=1000000
 icache=system.ruby.l1_cntrl7.cacheMemory
@@ -665,12 +675,17 @@
 version=7
 slave=system.cpu7.test
 
+[system.ruby.memctrl_clk_domain]
+type=DerivedClockDomain
+clk_divider=3
+clk_domain=system.ruby.clk_domain
+
 [system.ruby.network]
 type=SimpleNetwork
 children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8
 adaptive_routing=false
 buffer_size=0
-clock=1
+clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6 system.ruby.network.ext_links7 system.ruby.network.ext_links8
@@ -692,7 +707,7 @@
 
 [system.ruby.network.ext_links0.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=0
 virt_nets=10
 
@@ -708,7 +723,7 @@
 
 [system.ruby.network.ext_links1.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=1
 virt_nets=10
 
@@ -724,7 +739,7 @@
 
 [system.ruby.network.ext_links2.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=2
 virt_nets=10
 
@@ -740,7 +755,7 @@
 
 [system.ruby.network.ext_links3.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=3
 virt_nets=10
 
@@ -756,7 +771,7 @@
 
 [system.ruby.network.ext_links4.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=4
 virt_nets=10
 
@@ -772,7 +787,7 @@
 
 [system.ruby.network.ext_links5.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=5
 virt_nets=10
 
@@ -788,7 +803,7 @@
 
 [system.ruby.network.ext_links6.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=6
 virt_nets=10
 
@@ -804,7 +819,7 @@
 
 [system.ruby.network.ext_links7.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=7
 virt_nets=10
 
@@ -820,7 +835,7 @@
 
 [system.ruby.network.ext_links8.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=8
 virt_nets=10
 
@@ -836,7 +851,7 @@
 
 [system.ruby.network.int_links0.node_b]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=9
 virt_nets=10
 
@@ -922,7 +937,7 @@
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-clock=1
+clk_domain=system.clk_domain
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats	Wed Aug 07 15:24:58 2013 -0500
@@ -1,24 +1,24 @@
-Real time: Jun/24/2013 23:54:57
+Real time: Jul/17/2013 12:18:22
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 46
-Elapsed_time_in_minutes: 0.766667
-Elapsed_time_in_hours: 0.0127778
-Elapsed_time_in_days: 0.000532407
+Elapsed_time_in_seconds: 35
+Elapsed_time_in_minutes: 0.583333
+Elapsed_time_in_hours: 0.00972222
+Elapsed_time_in_days: 0.000405093
 
-Virtual_time_in_seconds: 46.63
-Virtual_time_in_minutes: 0.777167
-Virtual_time_in_hours:   0.0129528
-Virtual_time_in_days:    0.000539699
+Virtual_time_in_seconds: 36.04
+Virtual_time_in_minutes: 0.600667
+Virtual_time_in_hours:   0.0100111
+Virtual_time_in_days:    0.00041713
 
 Ruby_current_time: 8664886
 Ruby_start_time: 0
 Ruby_cycles: 8664886
 
-mbytes_resident: 71.4453
-mbytes_total: 292.027
-resident_ratio: 0.24468
+mbytes_resident: 66.5352
+mbytes_total: 269.961
+resident_ratio: 0.24652
 
 Busy Controller Counts:
 L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:0  L1Cache-7:0  
@@ -78,13 +78,13 @@
 Resource Usage
 --------------
 page_size: 4096
-user_time: 46
+user_time: 35
 system_time: 0
-page_reclaims: 16444
-page_faults: 5
+page_reclaims: 9528
+page_faults: 0
 swaps: 0
-block_inputs: 80
-block_outputs: 240
+block_inputs: 0
+block_outputs: 192
 
 Network Stats
 -------------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr  9 2013 01:51:40
-gem5 started Apr  9 2013 01:54:58
-gem5 executing on vein
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 8664886 because maximum number of loads reached
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,11 +4,9 @@
 sim_ticks                                     8664886                       # Number of ticks simulated
 final_tick                                    8664886                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 229644                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 290312                       # Number of bytes of host memory used
-host_seconds                                    37.73                       # Real time elapsed on the host
-system.funcbus.throughput                           0                       # Throughput (bytes/s)
-system.funcbus.data_through_bus                     0                       # Total data (bytes)
+host_tick_rate                                 243257                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 276444                       # Number of bytes of host memory used
+host_seconds                                    35.62                       # Real time elapsed on the host
 system.ruby.l1_cntrl4.cacheMemory.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl4.cacheMemory.demand_misses        77331                       # Number of cache demand misses
 system.ruby.l1_cntrl4.cacheMemory.demand_accesses        77331                       # Number of cache demand accesses
@@ -51,6 +49,8 @@
 system.ruby.dir_cntrl0.memBuffer.memBankCount |       38404      3.15%      3.15% |       37646      3.09%      6.24% |       38381      3.15%      9.39% |       38273      3.14%     12.53% |       38109      3.13%     15.66% |       38021      3.12%     18.78% |       38580      3.17%     21.94% |       38357      3.15%     25.09% |       38057      3.12%     28.21% |       38004      3.12%     31.33% |       38123      3.13%     34.46% |       37658      3.09%     37.55% |       37751      3.10%     40.65% |       38546      3.16%     43.81% |       37560      3.08%     46.89% |       38514      3.16%     50.05% |       38232      3.14%     53.19% |       38045      3.12%     56.31% |       38749      3.18%     59.49% |       38589      3.17%     62.66% |       38066      3.12%     65.78% |       37687      3.09%     68.87% |       38032      3.12%     71.99% |       38060      3.12%     75.12% |       37804      3.10%     78.22% |       38206      3.14%     81.35% |       37726      3.10%     84.45% |       38148      3.13%     87.58% |       37682      3.09%     90.67% |       38049      3.12%     93.79% |       37701      3.09%     96.89% |       37918      3.11%    100.00% # Number of accesses per bank
 system.ruby.dir_cntrl0.memBuffer.memBankCount::total      1218678                       # Number of accesses per bank
 
+system.funcbus.throughput                           0                       # Throughput (bytes/s)
+system.funcbus.data_through_bus                     0                       # Total data (bytes)
 system.cpu0.num_reads                           99885                       # number of read accesses completed
 system.cpu0.num_writes                          54375                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,15 +8,15 @@
 
 [system]
 type=System
-children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcbus funcmem l2c membus physmem toL2Bus
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcbus funcmem l2c membus physmem toL2Bus
 boot_osflags=a
-clock=1000
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
 mem_mode=timing
 mem_ranges=
-memories=system.funcmem system.physmem
+memories=system.physmem system.funcmem
 num_work_ids=16
 readfile=
 symbolfile=
@@ -29,11 +29,15 @@
 work_item_id=-1
 system_port=system.membus.slave[1]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+
 [system.cpu0]
 type=MemTest
 children=l1c
 atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -51,10 +55,11 @@
 
 [system.cpu0.l1c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -65,17 +70,26 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.test
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1]
 type=MemTest
 children=l1c
 atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -93,10 +107,11 @@
 
 [system.cpu1.l1c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -107,17 +122,26 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.test
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu1.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu2]
 type=MemTest
 children=l1c
 atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -135,10 +159,11 @@
 
 [system.cpu2.l1c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -149,17 +174,26 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu2.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.test
 mem_side=system.toL2Bus.slave[2]
 
+[system.cpu2.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu3]
 type=MemTest
 children=l1c
 atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -177,10 +211,11 @@
 
 [system.cpu3.l1c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -191,17 +226,26 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu3.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.test
 mem_side=system.toL2Bus.slave[3]
 
+[system.cpu3.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu4]
 type=MemTest
 children=l1c
 atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -219,10 +263,11 @@
 
 [system.cpu4.l1c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -233,17 +278,26 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu4.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu4.test
 mem_side=system.toL2Bus.slave[4]
 
+[system.cpu4.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu5]
 type=MemTest
 children=l1c
 atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -261,10 +315,11 @@
 
 [system.cpu5.l1c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -275,17 +330,26 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu5.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu5.test
 mem_side=system.toL2Bus.slave[5]
 
+[system.cpu5.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu6]
 type=MemTest
 children=l1c
 atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -303,10 +367,11 @@
 
 [system.cpu6.l1c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -317,17 +382,26 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu6.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu6.test
 mem_side=system.toL2Bus.slave[6]
 
+[system.cpu6.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu7]
 type=MemTest
 children=l1c
 atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -345,10 +419,11 @@
 
 [system.cpu7.l1c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -359,16 +434,29 @@
 response_latency=2
 size=32768
 system=system
+tags=system.cpu7.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu7.test
 mem_side=system.toL2Bus.slave[7]
 
+[system.cpu7.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+
 [system.funcbus]
 type=NoncoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=false
 width=8
@@ -378,22 +466,22 @@
 [system.funcmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=false
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.funcbus.master[0]
 
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -404,16 +492,25 @@
 response_latency=20
 size=65536
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[0]
 
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=65536
+
 [system.membus]
 type=CoherentBus
 block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -424,20 +521,19 @@
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
 [system.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,74 +1,74 @@
-system.cpu6: completed 10000 read, 5435 write accesses @79021500
-system.cpu0: completed 10000 read, 5363 write accesses @79194500
-system.cpu7: completed 10000 read, 5392 write accesses @79770500
-system.cpu2: completed 10000 read, 5375 write accesses @80689500
-system.cpu1: completed 10000 read, 5373 write accesses @81623500
-system.cpu4: completed 10000 read, 5458 write accesses @81916000
-system.cpu5: completed 10000 read, 5507 write accesses @81975000
-system.cpu3: completed 10000 read, 5421 write accesses @82381000
-system.cpu2: completed 20000 read, 10678 write accesses @153864500
-system.cpu0: completed 20000 read, 10854 write accesses @154789000
-system.cpu7: completed 20000 read, 10817 write accesses @154953500
-system.cpu1: completed 20000 read, 10781 write accesses @155855500
-system.cpu3: completed 20000 read, 10799 write accesses @157033000
-system.cpu4: completed 20000 read, 10854 write accesses @157158000
-system.cpu6: completed 20000 read, 10878 write accesses @157795000
-system.cpu5: completed 20000 read, 10963 write accesses @159866500
-system.cpu0: completed 30000 read, 16180 write accesses @228385000
-system.cpu2: completed 30000 read, 15995 write accesses @229109500
-system.cpu7: completed 30000 read, 16232 write accesses @231170000
-system.cpu1: completed 30000 read, 16165 write accesses @231658500
-system.cpu4: completed 30000 read, 16252 write accesses @232783000
-system.cpu6: completed 30000 read, 16228 write accesses @233712000
-system.cpu3: completed 30000 read, 16226 write accesses @236523000
-system.cpu5: completed 30000 read, 16456 write accesses @239602000
-system.cpu0: completed 40000 read, 21598 write accesses @305262000
-system.cpu2: completed 40000 read, 21332 write accesses @306571000
-system.cpu1: completed 40000 read, 21599 write accesses @307778500
-system.cpu4: completed 40000 read, 21599 write accesses @307971000
-system.cpu7: completed 40000 read, 21551 write accesses @308441000
-system.cpu6: completed 40000 read, 21597 write accesses @310397000
-system.cpu3: completed 40000 read, 21704 write accesses @312891000
-system.cpu5: completed 40000 read, 21914 write accesses @315565000
-system.cpu4: completed 50000 read, 26891 write accesses @381925000
-system.cpu0: completed 50000 read, 26990 write accesses @382095500
-system.cpu2: completed 50000 read, 26686 write accesses @382917500
-system.cpu1: completed 50000 read, 26983 write accesses @384289000
-system.cpu6: completed 50000 read, 27066 write accesses @384539000
-system.cpu7: completed 50000 read, 26943 write accesses @385136500
-system.cpu3: completed 50000 read, 27037 write accesses @389922000
-system.cpu5: completed 50000 read, 27423 write accesses @393691500
-system.cpu6: completed 60000 read, 32353 write accesses @457634500
-system.cpu4: completed 60000 read, 32228 write accesses @457992000
-system.cpu1: completed 60000 read, 32457 write accesses @460714000
-system.cpu2: completed 60000 read, 32178 write accesses @461196500
-system.cpu0: completed 60000 read, 32542 write accesses @461690000
-system.cpu7: completed 60000 read, 32302 write accesses @462388500
-system.cpu3: completed 60000 read, 32488 write accesses @466103000
-system.cpu5: completed 60000 read, 32744 write accesses @469778000
-system.cpu6: completed 70000 read, 37747 write accesses @533745000
-system.cpu2: completed 70000 read, 37532 write accesses @535320500
-system.cpu4: completed 70000 read, 37773 write accesses @535591500
-system.cpu7: completed 70000 read, 37639 write accesses @538124500
-system.cpu0: completed 70000 read, 37909 write accesses @538334500
-system.cpu1: completed 70000 read, 37921 write accesses @541231500
-system.cpu3: completed 70000 read, 37871 write accesses @542226500
-system.cpu5: completed 70000 read, 38229 write accesses @548322500
-system.cpu4: completed 80000 read, 42983 write accesses @610769500
-system.cpu6: completed 80000 read, 43020 write accesses @610776000
-system.cpu2: completed 80000 read, 42982 write accesses @611661000
-system.cpu0: completed 80000 read, 43374 write accesses @615085500
-system.cpu1: completed 80000 read, 43250 write accesses @615627500
-system.cpu7: completed 80000 read, 43033 write accesses @615746000
-system.cpu3: completed 80000 read, 43154 write accesses @619760000
-system.cpu5: completed 80000 read, 43738 write accesses @625688001
-system.cpu6: completed 90000 read, 48339 write accesses @685422000
-system.cpu2: completed 90000 read, 48272 write accesses @687608500
-system.cpu4: completed 90000 read, 48507 write accesses @688615500
-system.cpu7: completed 90000 read, 48310 write accesses @688789000
-system.cpu0: completed 90000 read, 48650 write accesses @689991000
-system.cpu1: completed 90000 read, 48621 write accesses @693117500
-system.cpu3: completed 90000 read, 48493 write accesses @697608000
-system.cpu5: completed 90000 read, 49008 write accesses @701381500
-system.cpu6: completed 100000 read, 53851 write accesses @761435500
+system.cpu6: completed 10000 read, 5217 write accesses @68085999
+system.cpu4: completed 10000 read, 5435 write accesses @69661000
+system.cpu2: completed 10000 read, 5368 write accesses @70121500
+system.cpu3: completed 10000 read, 5457 write accesses @70317500
+system.cpu1: completed 10000 read, 5387 write accesses @70875500
+system.cpu7: completed 10000 read, 5470 write accesses @70949000
+system.cpu0: completed 10000 read, 5435 write accesses @71227500
+system.cpu5: completed 10000 read, 5514 write accesses @71894000
+system.cpu6: completed 20000 read, 10518 write accesses @132327500
+system.cpu4: completed 20000 read, 10839 write accesses @133525000
+system.cpu1: completed 20000 read, 10784 write accesses @134714500
+system.cpu7: completed 20000 read, 10701 write accesses @135318500
+system.cpu0: completed 20000 read, 10821 write accesses @135563500
+system.cpu2: completed 20000 read, 10843 write accesses @135684500
+system.cpu3: completed 20000 read, 10685 write accesses @135938500
+system.cpu5: completed 20000 read, 11031 write accesses @136425000
+system.cpu6: completed 30000 read, 16001 write accesses @197849500
+system.cpu4: completed 30000 read, 16254 write accesses @198725500
+system.cpu0: completed 30000 read, 16109 write accesses @199579499
+system.cpu1: completed 30000 read, 16209 write accesses @200016500
+system.cpu5: completed 30000 read, 16414 write accesses @200525000
+system.cpu3: completed 30000 read, 15978 write accesses @200724000
+system.cpu7: completed 30000 read, 16153 write accesses @201563500
+system.cpu2: completed 30000 read, 16316 write accesses @202401999
+system.cpu4: completed 40000 read, 21506 write accesses @263053500
+system.cpu6: completed 40000 read, 21338 write accesses @263431500
+system.cpu5: completed 40000 read, 21670 write accesses @263987000
+system.cpu3: completed 40000 read, 21219 write accesses @264608000
+system.cpu1: completed 40000 read, 21536 write accesses @265348500
+system.cpu0: completed 40000 read, 21604 write accesses @265426500
+system.cpu7: completed 40000 read, 21465 write accesses @265674000
+system.cpu2: completed 40000 read, 21690 write accesses @268754000
+system.cpu6: completed 50000 read, 26563 write accesses @327819000
+system.cpu4: completed 50000 read, 27066 write accesses @328101000
+system.cpu5: completed 50000 read, 26900 write accesses @328372000
+system.cpu3: completed 50000 read, 26596 write accesses @328811500
+system.cpu1: completed 50000 read, 26845 write accesses @328908500
+system.cpu7: completed 50000 read, 26873 write accesses @331316999
+system.cpu0: completed 50000 read, 26988 write accesses @331358000
+system.cpu2: completed 50000 read, 27102 write accesses @333876000
+system.cpu1: completed 60000 read, 32156 write accesses @392077000
+system.cpu6: completed 60000 read, 31998 write accesses @392784000
+system.cpu5: completed 60000 read, 32223 write accesses @393227500
+system.cpu4: completed 60000 read, 32446 write accesses @394175000
+system.cpu3: completed 60000 read, 32090 write accesses @394842000
+system.cpu0: completed 60000 read, 32282 write accesses @395716500
+system.cpu7: completed 60000 read, 32292 write accesses @397180000
+system.cpu2: completed 60000 read, 32266 write accesses @397288500
+system.cpu6: completed 70000 read, 37440 write accesses @457780500
+system.cpu1: completed 70000 read, 37577 write accesses @458242500
+system.cpu5: completed 70000 read, 37616 write accesses @458643500
+system.cpu4: completed 70000 read, 37952 write accesses @459569500
+system.cpu3: completed 70000 read, 37486 write accesses @460007500
+system.cpu0: completed 70000 read, 37804 write accesses @461418499
+system.cpu2: completed 70000 read, 37588 write accesses @461790000
+system.cpu7: completed 70000 read, 37743 write accesses @462130500
+system.cpu1: completed 80000 read, 42976 write accesses @523192500
+system.cpu5: completed 80000 read, 43028 write accesses @523895500
+system.cpu6: completed 80000 read, 42870 write accesses @524155000
+system.cpu4: completed 80000 read, 43341 write accesses @524226000
+system.cpu3: completed 80000 read, 42885 write accesses @524383000
+system.cpu2: completed 80000 read, 43005 write accesses @527239000
+system.cpu7: completed 80000 read, 43156 write accesses @528371000
+system.cpu0: completed 80000 read, 43239 write accesses @528519000
+system.cpu3: completed 90000 read, 48037 write accesses @586595000
+system.cpu1: completed 90000 read, 48299 write accesses @588010000
+system.cpu4: completed 90000 read, 48806 write accesses @589147500
+system.cpu6: completed 90000 read, 48454 write accesses @589844000
+system.cpu5: completed 90000 read, 48341 write accesses @590185000
+system.cpu2: completed 90000 read, 48395 write accesses @591584000
+system.cpu7: completed 90000 read, 48496 write accesses @592485000
+system.cpu0: completed 90000 read, 48680 write accesses @594831500
+system.cpu3: completed 100000 read, 53536 write accesses @652606500
 hack: be nice to actually delete the event here
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 14:39:12
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 761435500 because maximum number of loads reached
+Exiting @ tick 652606500 because maximum number of loads reached
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,9 +4,9 @@
 sim_ticks                                   652606500                       # Number of ticks simulated
 final_tick                                  652606500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                              176079756                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 355636                       # Number of bytes of host memory used
-host_seconds                                     3.71                       # Real time elapsed on the host
+host_tick_rate                              133358853                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 380288                       # Number of bytes of host memory used
+host_seconds                                     4.89                       # Real time elapsed on the host
 system.physmem.bytes_read::cpu0                 80014                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1                 82049                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu2                 81047                       # Number of bytes read from this memory
@@ -94,31 +94,31 @@
 system.membus.reqLayer0.utilization              43.9                       # Layer utilization (%)
 system.membus.respLayer0.occupancy          311361500                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization             47.7                       # Layer utilization (%)
-system.l2c.tags.replacements                         13254                       # number of replacements
-system.l2c.tags.tagsinuse                       783.820018                       # Cycle average of tags in use
-system.l2c.tags.total_refs                          149317                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                         14065                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                         10.616210                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks          726.472153                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0                  7.679894                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1                  7.566050                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2                  7.311161                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3                  6.856177                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4                  7.195523                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5                  6.988954                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6                  6.739476                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7                  7.010629                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks           0.709445                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0                 0.007500                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1                 0.007389                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2                 0.007140                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3                 0.006695                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu4                 0.007027                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu5                 0.006825                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu6                 0.006582                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu7                 0.006846                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total                0.765449                       # Average percentage of cache occupancy
+system.l2c.tags.replacements                    13254                       # number of replacements
+system.l2c.tags.tagsinuse                  783.820018                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     149317                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                    14065                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    10.616210                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks     726.472153                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0             7.679894                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1             7.566050                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2             7.311161                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3             6.856177                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu4             7.195523                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu5             6.988954                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu6             6.739476                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu7             7.010629                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.709445                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0            0.007500                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1            0.007389                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2            0.007140                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3            0.006695                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu4            0.007027                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu5            0.006825                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu6            0.006582                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu7            0.006846                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.765449                       # Average percentage of cache occupancy
 system.l2c.ReadReq_hits::cpu0                   10635                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1                   10552                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu2                   10744                       # number of ReadReq hits
@@ -731,15 +731,15 @@
 system.cpu0.num_reads                           98977                       # number of read accesses completed
 system.cpu0.num_writes                          53590                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
-system.cpu0.l1c.tags.replacements                    21970                       # number of replacements
-system.cpu0.l1c.tags.tagsinuse                  393.709596                       # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs                      13350                       # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs                    22370                       # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs                     0.596781                       # Average number of references to valid blocks.
-system.cpu0.l1c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0           393.709596                       # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0            0.768964                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total           0.768964                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.replacements               21970                       # number of replacements
+system.cpu0.l1c.tags.tagsinuse             393.709596                       # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs                 13350                       # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs               22370                       # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs                0.596781                       # Average number of references to valid blocks.
+system.cpu0.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
+system.cpu0.l1c.tags.occ_blocks::cpu0      393.709596                       # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0       0.768964                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total      0.768964                       # Average percentage of cache occupancy
 system.cpu0.l1c.ReadReq_hits::cpu0               8685                       # number of ReadReq hits
 system.cpu0.l1c.ReadReq_hits::total              8685                       # number of ReadReq hits
 system.cpu0.l1c.WriteReq_hits::cpu0              1118                       # number of WriteReq hits
@@ -846,15 +846,15 @@
 system.cpu1.num_reads                           99824                       # number of read accesses completed
 system.cpu1.num_writes                          53636                       # number of write accesses completed
 system.cpu1.num_copies                              0                       # number of copy accesses completed
-system.cpu1.l1c.tags.replacements                    22223                       # number of replacements
-system.cpu1.l1c.tags.tagsinuse                  395.298418                       # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs                      13436                       # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs                    22630                       # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs                     0.593725                       # Average number of references to valid blocks.
-system.cpu1.l1c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1           395.298418                       # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1            0.772067                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total           0.772067                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.replacements               22223                       # number of replacements
+system.cpu1.l1c.tags.tagsinuse             395.298418                       # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs                 13436                       # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs               22630                       # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs                0.593725                       # Average number of references to valid blocks.
+system.cpu1.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
+system.cpu1.l1c.tags.occ_blocks::cpu1      395.298418                       # Average occupied blocks per requestor
+system.cpu1.l1c.tags.occ_percent::cpu1       0.772067                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_percent::total      0.772067                       # Average percentage of cache occupancy
 system.cpu1.l1c.ReadReq_hits::cpu1               8757                       # number of ReadReq hits
 system.cpu1.l1c.ReadReq_hits::total              8757                       # number of ReadReq hits
 system.cpu1.l1c.WriteReq_hits::cpu1              1135                       # number of WriteReq hits
@@ -961,15 +961,15 @@
 system.cpu2.num_reads                           99336                       # number of read accesses completed
 system.cpu2.num_writes                          53403                       # number of write accesses completed
 system.cpu2.num_copies                              0                       # number of copy accesses completed
-system.cpu2.l1c.tags.replacements                    22214                       # number of replacements
-system.cpu2.l1c.tags.tagsinuse                  394.859577                       # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs                      13307                       # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs                    22614                       # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs                     0.588441                       # Average number of references to valid blocks.
-system.cpu2.l1c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2           394.859577                       # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2            0.771210                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total           0.771210                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.replacements               22214                       # number of replacements
+system.cpu2.l1c.tags.tagsinuse             394.859577                       # Cycle average of tags in use
+system.cpu2.l1c.tags.total_refs                 13307                       # Total number of references to valid blocks.
+system.cpu2.l1c.tags.sampled_refs               22614                       # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs                0.588441                       # Average number of references to valid blocks.
+system.cpu2.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
+system.cpu2.l1c.tags.occ_blocks::cpu2      394.859577                       # Average occupied blocks per requestor
+system.cpu2.l1c.tags.occ_percent::cpu2       0.771210                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_percent::total      0.771210                       # Average percentage of cache occupancy
 system.cpu2.l1c.ReadReq_hits::cpu2               8708                       # number of ReadReq hits
 system.cpu2.l1c.ReadReq_hits::total              8708                       # number of ReadReq hits
 system.cpu2.l1c.WriteReq_hits::cpu2              1070                       # number of WriteReq hits
@@ -1076,15 +1076,15 @@
 system.cpu3.num_reads                          100000                       # number of read accesses completed
 system.cpu3.num_writes                          53536                       # number of write accesses completed
 system.cpu3.num_copies                              0                       # number of copy accesses completed
-system.cpu3.l1c.tags.replacements                    22464                       # number of replacements
-system.cpu3.l1c.tags.tagsinuse                  397.838914                       # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs                      13424                       # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs                    22862                       # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs                     0.587175                       # Average number of references to valid blocks.
-system.cpu3.l1c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3           397.838914                       # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3            0.777029                       # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total           0.777029                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.replacements               22464                       # number of replacements
+system.cpu3.l1c.tags.tagsinuse             397.838914                       # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs                 13424                       # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs               22862                       # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs                0.587175                       # Average number of references to valid blocks.
+system.cpu3.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
+system.cpu3.l1c.tags.occ_blocks::cpu3      397.838914                       # Average occupied blocks per requestor
+system.cpu3.l1c.tags.occ_percent::cpu3       0.777029                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_percent::total      0.777029                       # Average percentage of cache occupancy
 system.cpu3.l1c.ReadReq_hits::cpu3               8781                       # number of ReadReq hits
 system.cpu3.l1c.ReadReq_hits::total              8781                       # number of ReadReq hits
 system.cpu3.l1c.WriteReq_hits::cpu3              1109                       # number of WriteReq hits
@@ -1191,15 +1191,15 @@
 system.cpu4.num_reads                           99830                       # number of read accesses completed
 system.cpu4.num_writes                          54064                       # number of write accesses completed
 system.cpu4.num_copies                              0                       # number of copy accesses completed
-system.cpu4.l1c.tags.replacements                    22082                       # number of replacements
-system.cpu4.l1c.tags.tagsinuse                  393.544066                       # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs                      13201                       # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs                    22486                       # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs                     0.587076                       # Average number of references to valid blocks.
-system.cpu4.l1c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4           393.544066                       # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4            0.768641                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total           0.768641                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.replacements               22082                       # number of replacements
+system.cpu4.l1c.tags.tagsinuse             393.544066                       # Cycle average of tags in use
+system.cpu4.l1c.tags.total_refs                 13201                       # Total number of references to valid blocks.
+system.cpu4.l1c.tags.sampled_refs               22486                       # Sample count of references to valid blocks.
+system.cpu4.l1c.tags.avg_refs                0.587076                       # Average number of references to valid blocks.
+system.cpu4.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
+system.cpu4.l1c.tags.occ_blocks::cpu4      393.544066                       # Average occupied blocks per requestor
+system.cpu4.l1c.tags.occ_percent::cpu4       0.768641                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_percent::total      0.768641                       # Average percentage of cache occupancy
 system.cpu4.l1c.ReadReq_hits::cpu4               8712                       # number of ReadReq hits
 system.cpu4.l1c.ReadReq_hits::total              8712                       # number of ReadReq hits
 system.cpu4.l1c.WriteReq_hits::cpu4              1102                       # number of WriteReq hits
@@ -1306,15 +1306,15 @@
 system.cpu5.num_reads                           99630                       # number of read accesses completed
 system.cpu5.num_writes                          53500                       # number of write accesses completed
 system.cpu5.num_copies                              0                       # number of copy accesses completed
-system.cpu5.l1c.tags.replacements                    22051                       # number of replacements
-system.cpu5.l1c.tags.tagsinuse                  395.592742                       # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs                      13484                       # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs                    22450                       # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs                     0.600624                       # Average number of references to valid blocks.
-system.cpu5.l1c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5           395.592742                       # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5            0.772642                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total           0.772642                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.replacements               22051                       # number of replacements
+system.cpu5.l1c.tags.tagsinuse             395.592742                       # Cycle average of tags in use
+system.cpu5.l1c.tags.total_refs                 13484                       # Total number of references to valid blocks.
+system.cpu5.l1c.tags.sampled_refs               22450                       # Sample count of references to valid blocks.
+system.cpu5.l1c.tags.avg_refs                0.600624                       # Average number of references to valid blocks.
+system.cpu5.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
+system.cpu5.l1c.tags.occ_blocks::cpu5      395.592742                       # Average occupied blocks per requestor
+system.cpu5.l1c.tags.occ_percent::cpu5       0.772642                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_percent::total      0.772642                       # Average percentage of cache occupancy
 system.cpu5.l1c.ReadReq_hits::cpu5               8824                       # number of ReadReq hits
 system.cpu5.l1c.ReadReq_hits::total              8824                       # number of ReadReq hits
 system.cpu5.l1c.WriteReq_hits::cpu5              1160                       # number of WriteReq hits
@@ -1421,15 +1421,15 @@
 system.cpu6.num_reads                           99897                       # number of read accesses completed
 system.cpu6.num_writes                          53584                       # number of write accesses completed
 system.cpu6.num_copies                              0                       # number of copy accesses completed
-system.cpu6.l1c.tags.replacements                    22385                       # number of replacements
-system.cpu6.l1c.tags.tagsinuse                  395.582005                       # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs                      13337                       # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs                    22793                       # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs                     0.585136                       # Average number of references to valid blocks.
-system.cpu6.l1c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6           395.582005                       # Average occupied blocks per requestor
-system.cpu6.l1c.tags.occ_percent::cpu6            0.772621                       # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_percent::total           0.772621                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.replacements               22385                       # number of replacements
+system.cpu6.l1c.tags.tagsinuse             395.582005                       # Cycle average of tags in use
+system.cpu6.l1c.tags.total_refs                 13337                       # Total number of references to valid blocks.
+system.cpu6.l1c.tags.sampled_refs               22793                       # Sample count of references to valid blocks.
+system.cpu6.l1c.tags.avg_refs                0.585136                       # Average number of references to valid blocks.
+system.cpu6.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
+system.cpu6.l1c.tags.occ_blocks::cpu6      395.582005                       # Average occupied blocks per requestor
+system.cpu6.l1c.tags.occ_percent::cpu6       0.772621                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_percent::total      0.772621                       # Average percentage of cache occupancy
 system.cpu6.l1c.ReadReq_hits::cpu6               8715                       # number of ReadReq hits
 system.cpu6.l1c.ReadReq_hits::total              8715                       # number of ReadReq hits
 system.cpu6.l1c.WriteReq_hits::cpu6              1094                       # number of WriteReq hits
@@ -1536,15 +1536,15 @@
 system.cpu7.num_reads                           99207                       # number of read accesses completed
 system.cpu7.num_writes                          53401                       # number of write accesses completed
 system.cpu7.num_copies                              0                       # number of copy accesses completed
-system.cpu7.l1c.tags.replacements                    22143                       # number of replacements
-system.cpu7.l1c.tags.tagsinuse                  394.587693                       # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs                      13403                       # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs                    22544                       # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs                     0.594526                       # Average number of references to valid blocks.
-system.cpu7.l1c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7           394.587693                       # Average occupied blocks per requestor
-system.cpu7.l1c.tags.occ_percent::cpu7            0.770679                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_percent::total           0.770679                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.replacements               22143                       # number of replacements
+system.cpu7.l1c.tags.tagsinuse             394.587693                       # Cycle average of tags in use
+system.cpu7.l1c.tags.total_refs                 13403                       # Total number of references to valid blocks.
+system.cpu7.l1c.tags.sampled_refs               22544                       # Sample count of references to valid blocks.
+system.cpu7.l1c.tags.avg_refs                0.594526                       # Average number of references to valid blocks.
+system.cpu7.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
+system.cpu7.l1c.tags.occ_blocks::cpu7      394.587693                       # Average occupied blocks per requestor
+system.cpu7.l1c.tags.occ_percent::cpu7       0.770679                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_percent::total      0.770679                       # Average percentage of cache occupancy
 system.cpu7.l1c.ReadReq_hits::cpu7               8635                       # number of ReadReq hits
 system.cpu7.l1c.ReadReq_hits::total              8635                       # number of ReadReq hits
 system.cpu7.l1c.WriteReq_hits::cpu7              1078                       # number of WriteReq hits
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini	Wed Aug 07 15:24:58 2013 -0500
@@ -8,9 +8,9 @@
 
 [system]
 type=System
-children=physmem ruby sys_port_proxy tester
+children=clk_domain physmem ruby sys_port_proxy tester
 boot_osflags=a
-clock=1
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,34 +29,41 @@
 work_item_id=-1
 system_port=system.sys_port_proxy.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1
+
 [system.physmem]
 type=SimpleMemory
 bandwidth=0.000000
-clock=1
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30
 latency_var=0
 null=true
 range=0:134217727
-zero=false
 
 [system.ruby]
 type=RubySystem
-children=dir_cntrl0 l1_cntrl0 network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler
 block_size_bytes=64
-clock=1
+clk_domain=system.ruby.clk_domain
 mem_size=134217728
 no_mem_vec=false
 random_seed=1234
 randomization=true
 stats_filename=ruby.stats
 
+[system.ruby.clk_domain]
+type=SrcClockDomain
+clock=1
+
 [system.ruby.dir_cntrl0]
 type=Directory_Controller
 children=directory memBuffer
 buffer_size=0
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=1
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
@@ -83,7 +90,7 @@
 bank_queue_size=12
 banks_per_rank=8
 basic_bus_busy_time=2
-clock=3
+clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
 mem_ctl_latency=12
@@ -104,7 +111,7 @@
 buffer_size=0
 cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
-clock=1
+clk_domain=system.ruby.clk_domain
 cntrl_id=0
 issue_latency=2
 number_of_TBEs=256
@@ -133,7 +140,7 @@
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
 access_phys_mem=false
-clock=1
+clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
 icache=system.ruby.l1_cntrl0.cacheMemory
@@ -147,12 +154,17 @@
 version=0
 slave=system.tester.cpuDataPort[0] system.tester.cpuInstPort[0]
 
+[system.ruby.memctrl_clk_domain]
+type=DerivedClockDomain
+clk_divider=3
+clk_domain=system.ruby.clk_domain
+
 [system.ruby.network]
 type=SimpleNetwork
 children=ext_links0 ext_links1 int_links0 int_links1
 adaptive_routing=false
 buffer_size=0
-clock=1
+clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
@@ -174,7 +186,7 @@
 
 [system.ruby.network.ext_links0.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=0
 virt_nets=10
 
@@ -190,7 +202,7 @@
 
 [system.ruby.network.ext_links1.int_node]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=1
 virt_nets=10
 
@@ -206,7 +218,7 @@
 
 [system.ruby.network.int_links0.node_b]
 type=Switch
-clock=1
+clk_domain=system.ruby.clk_domain
 router_id=2
 virt_nets=10
 
@@ -229,7 +241,7 @@
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
-clock=1
+clk_domain=system.clk_domain
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -243,7 +255,7 @@
 type=RubyTester
 check_flush=false
 checks_to_complete=100
-clock=1
+clk_domain=system.clk_domain
 deadlock_threshold=50000
 num_cpus=1
 system=system
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats	Wed Aug 07 15:24:58 2013 -0500
@@ -1,24 +1,24 @@
-Real time: Jun/24/2013 23:54:11
+Real time: Jul/17/2013 12:17:47
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.51
-Virtual_time_in_minutes: 0.0085
-Virtual_time_in_hours:   0.000141667
-Virtual_time_in_days:    5.90278e-06
+Virtual_time_in_seconds: 0.42
+Virtual_time_in_minutes: 0.007
+Virtual_time_in_hours:   0.000116667
+Virtual_time_in_days:    4.86111e-06
 
 Ruby_current_time: 221941
 Ruby_start_time: 0
 Ruby_cycles: 221941
 
-mbytes_resident: 51.1953
-mbytes_total: 146.023
-resident_ratio: 0.35065
+mbytes_resident: 44.2617
+mbytes_total: 123.793
+resident_ratio: 0.357673
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -76,11 +76,11 @@
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 9501
+page_reclaims: 8939
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 88
+block_outputs: 72
 
 Network Stats
 -------------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,5 +1,5 @@
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
 hack: be nice to actually delete the event here
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:07:36
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby
+gem5 compiled Jul 17 2013 12:17:37
+gem5 started Jul 17 2013 12:17:46
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA/tests/fast/quick/se/60.rubytest/alpha/linux/rubytest-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 221941 because Ruby Tester completed
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -4,9 +4,9 @@
 sim_ticks                                      221941                       # Number of ticks simulated
 final_tick                                     221941                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                3023855                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 141832                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_tick_rate                                2808721                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 126900                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 system.ruby.l1_cntrl0.cacheMemory.demand_hits           38                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses          917                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses          955                       # Number of cache demand accesses
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simerr
--- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simerr	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simerr	Wed Aug 07 15:24:58 2013 -0500
@@ -1,1 +0,0 @@
-hack: be nice to actually delete the event here
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simout
--- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,10 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  6 2012 15:52:45
-gem5 started Aug  6 2012 15:56:03
-gem5 executing on 61f1f4j
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-dram -re tests/run.py build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-dram
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 300940000 because Done
+gem5 compiled Jul 17 2013 12:12:01
+gem5 started Jul 17 2013 12:12:10
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/70.tgen/arm/linux/tgen-simple-dram -re tests/run.py build/ARM/tests/fast/quick/se/70.tgen/arm/linux/tgen-simple-dram
+Skipping test: Test requires the 'TrafficGen' SimObject.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt
--- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,523 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.100000                       # Number of seconds simulated
-sim_ticks                                100000000000                       # Number of ticks simulated
-final_tick                               100000000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                            29067628326                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 231288                       # Number of bytes of host memory used
-host_seconds                                     3.44                       # Real time elapsed on the host
-system.physmem.bytes_read::cpu              213331136                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            213331136                       # Number of bytes read from this memory
-system.physmem.num_reads::cpu                 3333299                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               3333299                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu                2133311360                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2133311360                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu               2133311360                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2133311360                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       3333300                       # Total number of read requests seen
-system.physmem.writeReqs                            0                       # Total number of write requests seen
-system.physmem.cpureqs                        3333300                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                    213331136                       # Total number of bytes read from memory
-system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd              213331136                       # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                217600                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                217600                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                217600                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                217600                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                210100                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                204800                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                204800                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                204800                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                204800                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                204800                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10               204800                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11               204800                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12               204800                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13               204800                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14               204800                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15               204800                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
-system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                     99999960000                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                 3333300                       # Categorize read packet sizes
-system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::6                      0                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                   3301421                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     26232                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      1073                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       946                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       938                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       802                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       538                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       402                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       540                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       270                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      138                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        26100                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean     8168.810421                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean    8140.398372                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     356.874580                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65             16      0.06%      0.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3393           99      0.38%      0.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193        25985     99.56%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          26100                       # Bytes accessed per row activation
-system.physmem.totQLat                     1278758950                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat               63884930200                       # Sum of mem lat for all requests
-system.physmem.totBusLat                  16666500000                       # Total cycles spent in databus access
-system.physmem.totBankLat                 45939671250                       # Total cycles spent in bank access
-system.physmem.avgQLat                         383.63                       # Average queueing delay per request
-system.physmem.avgBankLat                    13782.04                       # Average bank access latency per request
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
-system.physmem.avgMemAccLat                  19165.67                       # Average memory access latency
-system.physmem.avgRdBW                        2133.31                       # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                2133.31                       # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil                          16.67                       # Data bus utilization in percentage
-system.physmem.avgRdQLen                         0.64                       # Average read queue length over time
-system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
-system.physmem.readRowHits                    3307200                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   99.22                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        30000.29                       # Average gap between requests
-system.membus.throughput                   2133311360                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq             3333300                       # Transaction distribution
-system.membus.trans_dist::ReadResp            3333299                       # Transaction distribution
-system.membus.pkt_count_system.monitor-master      6666599                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count                       6666599                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.monitor-master    213331136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size                  213331136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              213331136                       # Total data (bytes)
-system.membus.reqLayer0.occupancy          6333270000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               6.3                       # Layer utilization (%)
-system.membus.respLayer0.occupancy        17184426300                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization             17.2                       # Layer utilization (%)
-system.cpu.numPackets                         3333300                       # Number of packets generated
-system.cpu.numRetries                               0                       # Number of retries
-system.cpu.retryTicks                               0                       # Time spent waiting due to back-pressure (ticks)
-system.monitor.readBurstLengthHist::samples      3333300                       # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::mean           64                       # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::gmean    64.000000                       # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::stdev            0                       # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::0-3             0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::4-7             0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::8-11            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::12-15            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::16-19            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::20-23            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::24-27            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::28-31            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::32-35            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::36-39            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::40-43            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::44-47            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::48-51            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::52-55            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::56-59            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::60-63            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::64-67      3333300    100.00%    100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::68-71            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::72-75            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::76-79            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::total      3333300                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::samples            0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::mean          nan                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::gmean          nan                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::stdev          nan                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::0              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::1              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::2              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::3              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::4              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::5              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::6              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::7              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::8              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::9              0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::10             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::11             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::12             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::13             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::14             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::15             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::16             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::17             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::18             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::19             0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::total            0                       # Histogram of burst lengths of transmitted packets
-system.monitor.readBandwidthHist::samples          100                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::mean     2133311360                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::gmean  2133311359.990499                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::stdev   6399.944145                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::0-1.34218e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::4.02653e+08-5.36871e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::5.36871e+08-6.71089e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::6.71089e+08-8.05306e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::8.05306e+08-9.39524e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::9.39524e+08-1.07374e+09            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.07374e+09-1.20796e+09            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.20796e+09-1.34218e+09            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.34218e+09-1.4764e+09            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.4764e+09-1.61061e+09            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.61061e+09-1.74483e+09            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.74483e+09-1.87905e+09            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.87905e+09-2.01327e+09            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::2.01327e+09-2.14748e+09          100    100.00%    100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::2.14748e+09-2.2817e+09            0      0.00%    100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::2.2817e+09-2.41592e+09            0      0.00%    100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::2.41592e+09-2.55014e+09            0      0.00%    100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::2.55014e+09-2.68435e+09            0      0.00%    100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::total           100                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.averageReadBandwidth        2133311360      0.00%      0.00% # Average read bandwidth (bytes/s)
-system.monitor.totalReadBytes               213331136                       # Number of bytes read
-system.monitor.writeBandwidthHist::samples          100                       # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::mean             0                       # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::gmean            0                       # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::stdev            0                       # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::0              100    100.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1                0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::2                0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::3                0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::4                0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::5                0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::6                0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::7                0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::8                0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::9                0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::10               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::11               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::12               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::13               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::14               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::15               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::16               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::17               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::18               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::19               0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::total          100                       # Histogram of write bandwidth (bytes/s)
-system.monitor.averageWriteBandwidth                0                       # Average write bandwidth (bytes/s)
-system.monitor.totalWrittenBytes                    0                       # Number of bytes written
-system.monitor.readLatencyHist::samples       3333299                       # Read request-response latency
-system.monitor.readLatencyHist::mean     39172.137513                       # Read request-response latency
-system.monitor.readLatencyHist::gmean    38967.643311                       # Read request-response latency
-system.monitor.readLatencyHist::stdev     6823.352873                       # Read request-response latency
-system.monitor.readLatencyHist::0-32767         12686      0.38%      0.38% # Read request-response latency
-system.monitor.readLatencyHist::32768-65535      3289137     98.68%     99.06% # Read request-response latency
-system.monitor.readLatencyHist::65536-98303        26638      0.80%     99.85% # Read request-response latency
-system.monitor.readLatencyHist::98304-131071          937      0.03%     99.88% # Read request-response latency
-system.monitor.readLatencyHist::131072-163839         1073      0.03%     99.92% # Read request-response latency
-system.monitor.readLatencyHist::163840-196607          808      0.02%     99.94% # Read request-response latency
-system.monitor.readLatencyHist::196608-229375          670      0.02%     99.96% # Read request-response latency
-system.monitor.readLatencyHist::229376-262143          670      0.02%     99.98% # Read request-response latency
-system.monitor.readLatencyHist::262144-294911          272      0.01%     99.99% # Read request-response latency
-system.monitor.readLatencyHist::294912-327679          270      0.01%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::327680-360447          138      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::360448-393215            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::393216-425983            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::425984-458751            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::458752-491519            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::491520-524287            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::524288-557055            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::557056-589823            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::589824-622591            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::622592-655359            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::total         3333299                       # Read request-response latency
-system.monitor.writeLatencyHist::samples            0                       # Write request-response latency
-system.monitor.writeLatencyHist::mean             nan                       # Write request-response latency
-system.monitor.writeLatencyHist::gmean            nan                       # Write request-response latency
-system.monitor.writeLatencyHist::stdev            nan                       # Write request-response latency
-system.monitor.writeLatencyHist::0                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::1                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::2                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::3                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::4                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::5                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::6                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::7                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::8                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::9                  0                       # Write request-response latency
-system.monitor.writeLatencyHist::10                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::11                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::12                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::13                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::14                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::15                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::16                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::17                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::18                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::19                 0                       # Write request-response latency
-system.monitor.writeLatencyHist::total              0                       # Write request-response latency
-system.monitor.ittReadRead::samples           3333299                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::mean         30000.297003                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::stdev           54.497186                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::underflows              0      0.00%      0.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::1-5000                  0      0.00%      0.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::5001-10000              0      0.00%      0.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::10001-15000             0      0.00%      0.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::15001-20000             0      0.00%      0.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::20001-25000             0      0.00%      0.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::25001-30000       3333200    100.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::30001-35000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::35001-40000            99      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::40001-45000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::45001-50000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::50001-55000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::55001-60000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::60001-65000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::65001-70000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::70001-75000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::75001-80000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::80001-85000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::85001-90000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::90001-95000             0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::95001-100000            0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::overflows               0      0.00%    100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::min_value           30000                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::max_value           40000                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::total             3333299                       # Read-to-read inter transaction time
-system.monitor.ittWriteWrite::samples               0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::mean                nan                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::stdev               nan                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::underflows            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::1-5000                0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::5001-10000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::10001-15000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::15001-20000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::20001-25000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::25001-30000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::30001-35000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::35001-40000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::40001-45000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::45001-50000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::50001-55000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::55001-60000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::60001-65000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::65001-70000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::70001-75000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::75001-80000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::80001-85000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::85001-90000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::90001-95000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::95001-100000            0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::overflows             0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::min_value             0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::max_value             0                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::total                 0                       # Write-to-write inter transaction time
-system.monitor.ittReqReq::samples             3333299                       # Request-to-request inter transaction time
-system.monitor.ittReqReq::mean           30000.297003                       # Request-to-request inter transaction time
-system.monitor.ittReqReq::stdev             54.497186                       # Request-to-request inter transaction time
-system.monitor.ittReqReq::underflows                0      0.00%      0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::1-5000                    0      0.00%      0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::5001-10000                0      0.00%      0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::10001-15000               0      0.00%      0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::15001-20000               0      0.00%      0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::20001-25000               0      0.00%      0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::25001-30000         3333200    100.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::30001-35000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::35001-40000              99      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::40001-45000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::45001-50000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::50001-55000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::55001-60000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::60001-65000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::65001-70000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::70001-75000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::75001-80000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::80001-85000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::85001-90000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::90001-95000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::95001-100000              0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::overflows                 0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::min_value             30000                       # Request-to-request inter transaction time
-system.monitor.ittReqReq::max_value             40000                       # Request-to-request inter transaction time
-system.monitor.ittReqReq::total               3333299                       # Request-to-request inter transaction time
-system.monitor.outstandingReadsHist::samples          100                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::mean            1                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::gmean            1                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::stdev            0                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::0              0      0.00%      0.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::1            100    100.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::2              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::3              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::4              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::5              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::6              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::7              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::8              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::9              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::10             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::11             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::12             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::13             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::14             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::15             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::16             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::17             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::18             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::19             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::total          100                       # Outstanding read transactions
-system.monitor.outstandingWritesHist::samples          100                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::mean            0                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::gmean            0                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::stdev            0                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::0           100    100.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::1             0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::2             0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::3             0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::4             0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::5             0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::6             0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::7             0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::8             0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::9             0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::10            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::11            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::12            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::13            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::14            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::15            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::16            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::17            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::18            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::19            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::total          100                       # Outstanding write transactions
-system.monitor.readTransHist::samples             100                       # Histogram of read transactions per sample period
-system.monitor.readTransHist::mean              33333                       # Histogram of read transactions per sample period
-system.monitor.readTransHist::gmean      33333.000000                       # Histogram of read transactions per sample period
-system.monitor.readTransHist::stdev                 0                       # Histogram of read transactions per sample period
-system.monitor.readTransHist::0-2047                0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::2048-4095             0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::4096-6143             0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::6144-8191             0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::8192-10239            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::10240-12287            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::12288-14335            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::14336-16383            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::16384-18431            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::18432-20479            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::20480-22527            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::22528-24575            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::24576-26623            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::26624-28671            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::28672-30719            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::30720-32767            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::32768-34815          100    100.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::34816-36863            0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::36864-38911            0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::38912-40959            0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::total               100                       # Histogram of read transactions per sample period
-system.monitor.writeTransHist::samples            100                       # Histogram of read transactions per sample period
-system.monitor.writeTransHist::mean                 0                       # Histogram of read transactions per sample period
-system.monitor.writeTransHist::gmean                0                       # Histogram of read transactions per sample period
-system.monitor.writeTransHist::stdev                0                       # Histogram of read transactions per sample period
-system.monitor.writeTransHist::0                  100    100.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::1                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::2                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::3                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::4                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::5                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::6                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::7                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::8                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::9                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::10                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::11                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::12                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::13                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::14                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::15                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::16                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::17                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::18                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::19                   0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::total              100                       # Histogram of read transactions per sample period
-
----------- End Simulation Statistics   ----------
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simout
--- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simout	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simout	Wed Aug 07 15:24:58 2013 -0500
@@ -1,10 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 25 2012 13:56:00
-gem5 started Aug 25 2012 13:58:17
-gem5 executing on Andreas-MacBook-Pro.local
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-mem -re tests/run.py build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-mem
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 100000000000 because simulate() limit reached
+gem5 compiled Jul 17 2013 12:12:01
+gem5 started Jul 17 2013 12:12:10
+gem5 executing on ale-02.cs.wisc.edu
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/70.tgen/arm/linux/tgen-simple-mem -re tests/run.py build/ARM/tests/fast/quick/se/70.tgen/arm/linux/tgen-simple-mem
+Skipping test: Test requires the 'TrafficGen' SimObject.
diff -r e895db06e69f -r 07db1338d0b2 tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt
--- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt	Mon Jul 15 18:08:57 2013 -0400
+++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt	Wed Aug 07 15:24:58 2013 -0500
@@ -1,380 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.100000                       # Number of seconds simulated
-sim_ticks                                100000000000                       # Number of ticks simulated
-final_tick                               100000000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                            14083896029                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 231304                       # Number of bytes of host memory used
-host_seconds                                     7.10                       # Real time elapsed on the host
-system.physmem.bytes_read::cpu                     64                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                   64                       # Number of bytes read from this memory
-system.physmem.bytes_written::cpu           213329152                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         213329152                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu                       1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                     1                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu                3333268                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              3333268                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu                       640                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                     640                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu               2133291520                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             2133291520                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu               2133292160                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2133292160                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                   2133292160                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                   1                       # Transaction distribution
-system.membus.trans_dist::ReadResp                  1                       # Transaction distribution
-system.membus.trans_dist::WriteReq            3333268                       # Transaction distribution
-system.membus.trans_dist::WriteResp           3333267                       # Transaction distribution
-system.membus.pkt_count_system.monitor-master      6666537                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count                       6666537                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.monitor-master    213329216                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size                  213329216                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              213329216                       # Total data (bytes)
-system.membus.reqLayer0.occupancy         16666342328                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization              16.7                       # Layer utilization (%)
-system.membus.respLayer0.occupancy         3333272000                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization              3.3                       # Layer utilization (%)
-system.cpu.numPackets                         3333269                       # Number of packets generated
-system.cpu.numRetries                               1                       # Number of retries
-system.cpu.retryTicks                            1672                       # Time spent waiting due to back-pressure (ticks)
-system.monitor.readBurstLengthHist::samples            1                       # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::mean           64                       # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::gmean    64.000000                       # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::stdev          nan                       # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::0-3             0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::4-7             0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::8-11            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::12-15            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::16-19            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::20-23            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::24-27            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::28-31            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::32-35            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::36-39            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::40-43            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::44-47            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::48-51            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::52-55            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::56-59            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::60-63            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::64-67            1    100.00%    100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::68-71            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::72-75            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::76-79            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::total            1                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::samples      3333268                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::mean           64                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::gmean    64.000000                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::stdev            0                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::0-3            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::4-7            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::8-11            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::12-15            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::16-19            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::20-23            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::24-27            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::28-31            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::32-35            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::36-39            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::40-43            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::44-47            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::48-51            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::52-55            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::56-59            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::60-63            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::64-67      3333268    100.00%    100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::68-71            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::72-75            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::76-79            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::total      3333268                       # Histogram of burst lengths of transmitted packets
-system.monitor.readBandwidthHist::samples          100                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::mean            640                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::gmean             0                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::stdev          6400                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::0-4095           99     99.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::4096-8191            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::8192-12287            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::12288-16383            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::16384-20479            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::20480-24575            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::24576-28671            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::28672-32767            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::32768-36863            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::36864-40959            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::40960-45055            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::45056-49151            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::49152-53247            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::53248-57343            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::57344-61439            0      0.00%     99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::61440-65535            1      1.00%    100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::65536-69631            0      0.00%    100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::69632-73727            0      0.00%    100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::73728-77823            0      0.00%    100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::77824-81919            0      0.00%    100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::total           100                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.averageReadBandwidth               640      0.00%      0.00% # Average read bandwidth (bytes/s)
-system.monitor.totalReadBytes                      64                       # Number of bytes read
-system.monitor.writeBandwidthHist::samples          100                       # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::mean    2133291520                       # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::gmean 2133291510.261604                       # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::stdev       204800                       # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::0-1.34218e+08            0      0.00%      0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1.34218e+08-2.68435e+08            0      0.00%      0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::2.68435e+08-4.02653e+08            0      0.00%      0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::4.02653e+08-5.36871e+08            0      0.00%      0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::5.36871e+08-6.71089e+08            0      0.00%      0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::6.71089e+08-8.05306e+08            0      0.00%      0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::8.05306e+08-9.39524e+08            0      0.00%      0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::9.39524e+08-1.07374e+09            0      0.00%      0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1.07374e+09-1.20796e+09            0      0.00%      0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1.20796e+09-1.34218e+09            0      0.00%      0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1.34218e+09-1.4764e+09            0      0.00%      0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1.4764e+09-1.61061e+09            0      0.00%      0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1.61061e+09-1.74483e+09            0      0.00%      0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1.74483e+09-1.87905e+09            0      0.00%      0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1.87905e+09-2.01327e+09            0      0.00%      0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::2.01327e+09-2.14748e+09          100    100.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::2.14748e+09-2.2817e+09            0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::2.2817e+09-2.41592e+09            0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::2.41592e+09-2.55014e+09            0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::2.55014e+09-2.68435e+09            0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::total          100                       # Histogram of write bandwidth (bytes/s)
-system.monitor.averageWriteBandwidth       2133291520      0.00%      0.00% # Average write bandwidth (bytes/s)
-system.monitor.totalWrittenBytes            213329152                       # Number of bytes written
-system.monitor.readLatencyHist::samples             1                       # Read request-response latency
-system.monitor.readLatencyHist::mean            30000                       # Read request-response latency
-system.monitor.readLatencyHist::gmean    30000.000000                       # Read request-response latency
-system.monitor.readLatencyHist::stdev             nan                       # Read request-response latency
-system.monitor.readLatencyHist::0-2047              0      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::2048-4095            0      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::4096-6143            0      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::6144-8191            0      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::8192-10239            0      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::10240-12287            0      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::12288-14335            0      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::14336-16383            0      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::16384-18431            0      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::18432-20479            0      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::20480-22527            0      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::22528-24575            0      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::24576-26623            0      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::26624-28671            0      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::28672-30719            1    100.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::30720-32767            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::32768-34815            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::34816-36863            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::36864-38911            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::38912-40959            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::total               1                       # Read request-response latency
-system.monitor.writeLatencyHist::samples      3333267                       # Write request-response latency
-system.monitor.writeLatencyHist::mean    30000.000098                       # Write request-response latency
-system.monitor.writeLatencyHist::gmean   30000.000081                       # Write request-response latency
-system.monitor.writeLatencyHist::stdev       0.179655                       # Write request-response latency
-system.monitor.writeLatencyHist::0-2047             0      0.00%      0.00% # Write request-response latency
-system.monitor.writeLatencyHist::2048-4095            0      0.00%      0.00% # Write request-response latency
-system.monitor.writeLatencyHist::4096-6143            0      0.00%      0.00% # Write request-response latency
-system.monitor.writeLatencyHist::6144-8191            0      0.00%      0.00% # Write request-response latency
-system.monitor.writeLatencyHist::8192-10239            0      0.00%      0.00% # Write request-response latency
-system.monitor.writeLatencyHist::10240-12287            0      0.00%      0.00% # Write request-response latency
-system.monitor.writeLatencyHist::12288-14335            0      0.00%      0.00% # Write request-response latency
-system.monitor.writeLatencyHist::14336-16383            0      0.00%      0.00% # Write request-response latency
-system.monitor.writeLatencyHist::16384-18431            0      0.00%      0.00% # Write request-response latency
-system.monitor.writeLatencyHist::18432-20479            0      0.00%      0.00% # Write request-response latency
-system.monitor.writeLatencyHist::20480-22527            0      0.00%      0.00% # Write request-response latency
-system.monitor.writeLatencyHist::22528-24575            0      0.00%      0.00% # Write request-response latency
-system.monitor.writeLatencyHist::24576-26623            0      0.00%      0.00% # Write request-response latency
-system.monitor.writeLatencyHist::26624-28671            0      0.00%      0.00% # Write request-response latency
-system.monitor.writeLatencyHist::28672-30719      3333267    100.00%    100.00% # Write request-response latency
-system.monitor.writeLatencyHist::30720-32767            0      0.00%    100.00% # Write request-response latency
-system.monitor.writeLatencyHist::32768-34815            0      0.00%    100.00% # Write request-response latency
-system.monitor.writeLatencyHist::34816-36863            0      0.00%    100.00% # Write request-response latency
-system.monitor.writeLatencyHist::36864-38911            0      0.00%    100.00% # Write request-response latency
-system.monitor.writeLatencyHist::38912-40959            0      0.00%    100.00% # Write request-response latency
-system.monitor.writeLatencyHist::total        3333267                       # Write request-response latency
-system.monitor.ittReadRead::samples                 0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::mean                  nan                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::stdev                 nan                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::underflows              0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::1-5000                  0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::5001-10000              0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::10001-15000             0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::15001-20000             0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::20001-25000             0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::25001-30000             0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::30001-35000             0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::35001-40000             0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::40001-45000             0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::45001-50000             0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::50001-55000             0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::55001-60000             0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::60001-65000             0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::65001-70000             0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::70001-75000             0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::75001-80000             0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::80001-85000             0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::85001-90000             0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::90001-95000             0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::95001-100000            0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::overflows               0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::min_value               0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::max_value               0                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::total                   0                       # Read-to-read inter transaction time
-system.monitor.ittWriteWrite::samples         3333267                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::mean       30000.595310                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::stdev        547.340980                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::underflows            0      0.00%      0.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::1-5000                0      0.00%      0.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::5001-10000            0      0.00%      0.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::10001-15000            0      0.00%      0.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::15001-20000            0      0.00%      0.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::20001-25000            0      0.00%      0.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::25001-30000      3333167    100.00%    100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::30001-35000            0      0.00%    100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::35001-40000           99      0.00%    100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::40001-45000            0      0.00%    100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::45001-50000            0      0.00%    100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::50001-55000            0      0.00%    100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::55001-60000            0      0.00%    100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::60001-65000            0      0.00%    100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::65001-70000            0      0.00%    100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::70001-75000            0      0.00%    100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::75001-80000            0      0.00%    100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::80001-85000            0      0.00%    100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::85001-90000            0      0.00%    100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::90001-95000            0      0.00%    100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::95001-100000            0      0.00%    100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::overflows             1      0.00%    100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::min_value         30000                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::max_value       1024328                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::total           3333267                       # Write-to-write inter transaction time
-system.monitor.ittReqReq::samples             3333268                       # Request-to-request inter transaction time
-system.monitor.ittReqReq::mean           30000.587712                       # Request-to-request inter transaction time
-system.monitor.ittReqReq::stdev            547.516688                       # Request-to-request inter transaction time
-system.monitor.ittReqReq::underflows                0      0.00%      0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::1-5000                    1      0.00%      0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::5001-10000                0      0.00%      0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::10001-15000               0      0.00%      0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::15001-20000               0      0.00%      0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::20001-25000               0      0.00%      0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::25001-30000         3333167    100.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::30001-35000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::35001-40000              99      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::40001-45000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::45001-50000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::50001-55000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::55001-60000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::60001-65000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::65001-70000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::70001-75000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::75001-80000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::80001-85000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::85001-90000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::90001-95000               0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::95001-100000              0      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::overflows                 1      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::min_value              4672                       # Request-to-request inter transaction time
-system.monitor.ittReqReq::max_value           1024328                       # Request-to-request inter transaction time
-system.monitor.ittReqReq::total               3333268                       # Request-to-request inter transaction time
-system.monitor.outstandingReadsHist::samples          100                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::mean            0                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::gmean            0                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::stdev            0                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::0            100    100.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::1              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::2              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::3              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::4              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::5              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::6              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::7              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::8              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::9              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::10             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::11             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::12             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::13             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::14             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::15             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::16             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::17             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::18             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::19             0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::total          100                       # Outstanding read transactions
-system.monitor.outstandingWritesHist::samples          100                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::mean            1                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::gmean            1                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::stdev            0                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::0             0      0.00%      0.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::1           100    100.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::2             0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::3             0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::4             0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::5             0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::6             0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::7             0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::8             0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::9             0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::10            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::11            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::12            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::13            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::14            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::15            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::16            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::17            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::18            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::19            0      0.00%    100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::total          100                       # Outstanding write transactions
-system.monitor.readTransHist::samples             100                       # Histogram of read transactions per sample period
-system.monitor.readTransHist::mean           0.010000                       # Histogram of read transactions per sample period
-system.monitor.readTransHist::gmean                 0                       # Histogram of read transactions per sample period
-system.monitor.readTransHist::stdev          0.100000                       # Histogram of read transactions per sample period
-system.monitor.readTransHist::0                    99     99.00%     99.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::1                     1      1.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::2                     0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::3                     0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::4                     0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::5                     0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::6                     0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::7                     0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::8                     0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::9                     0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::10                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::11                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::12                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::13                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::14                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::15                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::16                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::17                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::18                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::19                    0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::total               100                       # Histogram of read transactions per sample period
-system.monitor.writeTransHist::samples            100                       # Histogram of read transactions per sample period
-system.monitor.writeTransHist::mean      33332.680000                       # Histogram of read transactions per sample period
-system.monitor.writeTransHist::gmean     33332.679848                       # Histogram of read transactions per sample period
-system.monitor.writeTransHist::stdev         3.200000                       # Histogram of read transactions per sample period
-system.monitor.writeTransHist::0-2047               0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::2048-4095            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::4096-6143            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::6144-8191            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::8192-10239            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::10240-12287            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::12288-14335            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::14336-16383            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::16384-18431            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::18432-20479            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::20480-22527            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::22528-24575            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::24576-26623            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::26624-28671            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::28672-30719            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::30720-32767            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::32768-34815          100    100.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::34816-36863            0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::36864-38911            0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::38912-40959            0      0.00%    100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::total              100                       # Histogram of read transactions per sample period
-
----------- End Simulation Statistics   ----------