diff -r 2e689ba6f678 -r 5eeb3f6704eb src/mem/simple_dram.hh
--- a/src/mem/simple_dram.hh	Thu Jul 18 13:43:41 2013 +0100
+++ b/src/mem/simple_dram.hh	Thu Jul 18 13:43:44 2013 +0100
@@ -349,8 +349,8 @@
     /**
      * The controller's main read and write queues
      */
-    std::list<DRAMPacket*> readQueue;
-    std::list<DRAMPacket*> writeQueue;
+    std::deque<DRAMPacket*> readQueue;
+    std::deque<DRAMPacket*> writeQueue;
 
     /**
      * Response queue where read packets wait after we're done working
@@ -360,7 +360,7 @@
      * as sizing the read queue, this and the main read queue need to
      * be added together.
      */
-    std::list<DRAMPacket*> respQueue;
+    std::deque<DRAMPacket*> respQueue;
 
     /**
      * If we need to drain, keep the drain manager around until we're
diff -r 2e689ba6f678 -r 5eeb3f6704eb src/mem/simple_dram.cc
--- a/src/mem/simple_dram.cc	Thu Jul 18 13:43:41 2013 +0100
+++ b/src/mem/simple_dram.cc	Thu Jul 18 13:43:44 2013 +0100
@@ -287,11 +287,10 @@
 
     // First check write buffer to see if the data is already at
     // the controller
-    list<DRAMPacket*>::const_iterator i;
     Addr addr = pkt->getAddr();
 
     // @todo: add size check
-    for (i = writeQueue.begin(); i != writeQueue.end(); ++i) {
+    for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) {
         if ((*i)->addr == addr){
             servicedByWrQ++;
             DPRINTF(DRAM, "Read to %lld serviced by write queue\n", addr);
@@ -532,19 +531,16 @@
 
 void
 SimpleDRAM::printQs() const {
-
-    list<DRAMPacket*>::const_iterator i;
-
     DPRINTF(DRAM, "===READ QUEUE===\n\n");
-    for (i = readQueue.begin() ;  i != readQueue.end() ; ++i) {
+    for (auto i = readQueue.begin() ;  i != readQueue.end() ; ++i) {
         DPRINTF(DRAM, "Read %lu\n", (*i)->addr);
     }
     DPRINTF(DRAM, "\n===RESP QUEUE===\n\n");
-    for (i = respQueue.begin() ;  i != respQueue.end() ; ++i) {
+    for (auto i = respQueue.begin() ;  i != respQueue.end() ; ++i) {
         DPRINTF(DRAM, "Response %lu\n", (*i)->addr);
     }
     DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n");
-    for (i = writeQueue.begin() ;  i != writeQueue.end() ; ++i) {
+    for (auto i = writeQueue.begin() ;  i != writeQueue.end() ; ++i) {
         DPRINTF(DRAM, "Write %lu\n", (*i)->addr);
     }
 }
@@ -684,7 +680,7 @@
     if (memSchedPolicy == Enums::fcfs) {
         // Do nothing, since the correct request is already head
     } else if (memSchedPolicy == Enums::frfcfs) {
-        list<DRAMPacket*>::iterator i = writeQueue.begin();
+        auto i = writeQueue.begin();
         bool foundRowHit = false;
         while (!foundRowHit && i != writeQueue.end()) {
             DRAMPacket* dram_pkt = *i;
@@ -725,8 +721,7 @@
         // Do nothing, since the request to serve is already the first
         // one in the read queue
     } else if (memSchedPolicy == Enums::frfcfs) {
-        for (list<DRAMPacket*>::iterator i = readQueue.begin();
-             i != readQueue.end() ; ++i) {
+        for (auto i = readQueue.begin(); i != readQueue.end() ; ++i) {
             DRAMPacket* dram_pkt = *i;
             const Bank& bank = dram_pkt->bank_ref;
             // Check if it is a row hit
@@ -1004,7 +999,7 @@
         schedule(respondEvent, dram_pkt->readyTime);
     } else {
         bool done = false;
-        list<DRAMPacket*>::iterator i = respQueue.begin();
+        auto i = respQueue.begin();
         while (!done && i != respQueue.end()) {
             if ((*i)->readyTime > dram_pkt->readyTime) {
                 respQueue.insert(i, dram_pkt);