diff -r afa9f7f4ee46 -r bc3b52b32bad configs/ruby/MESI_CMP_directory.py --- a/configs/ruby/MESI_CMP_directory.py Wed Aug 14 10:51:47 2013 -0400 +++ b/configs/ruby/MESI_CMP_directory.py Sat Aug 17 12:24:40 2013 -0500 @@ -98,6 +98,7 @@ options.cpu_type == "detailed"), prefetcher = prefetcher, ruby_system = ruby_system, + transitions_per_cycle=options.ports, enable_prefetch = False) cpu_seq = RubySequencer(version = i, @@ -133,6 +134,7 @@ l2_cntrl = L2Cache_Controller(version = i, cntrl_id = cntrl_count, L2cache = l2_cache, + transitions_per_cycle=options.ports, ruby_system = ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) @@ -173,6 +175,7 @@ use_map = options.use_map), memBuffer = mem_cntrl, + transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) @@ -190,6 +193,7 @@ dma_cntrl = DMA_Controller(version = i, cntrl_id = cntrl_count, dma_sequencer = dma_seq, + transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) diff -r afa9f7f4ee46 -r bc3b52b32bad configs/ruby/MI_example.py --- a/configs/ruby/MI_example.py Wed Aug 14 10:51:47 2013 -0400 +++ b/configs/ruby/MI_example.py Sat Aug 17 12:24:40 2013 -0500 @@ -84,6 +84,7 @@ cacheMemory = cache, send_evictions = ( options.cpu_type == "detailed"), + transitions_per_cycle = options.ports, ruby_system = ruby_system) cpu_seq = RubySequencer(version = i, @@ -140,6 +141,7 @@ map_levels = \ options.map_levels), memBuffer = mem_cntrl, + transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) @@ -157,6 +159,7 @@ dma_cntrl = DMA_Controller(version = i, cntrl_id = cntrl_count, dma_sequencer = dma_seq, + transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) diff -r afa9f7f4ee46 -r bc3b52b32bad configs/ruby/MOESI_CMP_directory.py --- a/configs/ruby/MOESI_CMP_directory.py Wed Aug 14 10:51:47 2013 -0400 +++ b/configs/ruby/MOESI_CMP_directory.py Sat Aug 17 12:24:40 2013 -0500 @@ -94,6 +94,7 @@ l2_select_num_bits = l2_bits, send_evictions = ( options.cpu_type == "detailed"), + transitions_per_cycle = options.ports, ruby_system = ruby_system) cpu_seq = RubySequencer(version = i, @@ -128,6 +129,7 @@ l2_cntrl = L2Cache_Controller(version = i, cntrl_id = cntrl_count, L2cache = l2_cache, + transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) @@ -167,6 +169,7 @@ size = dir_size, use_map = options.use_map), memBuffer = mem_cntrl, + transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) @@ -184,6 +187,7 @@ dma_cntrl = DMA_Controller(version = i, cntrl_id = cntrl_count, dma_sequencer = dma_seq, + transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) diff -r afa9f7f4ee46 -r bc3b52b32bad configs/ruby/MOESI_CMP_token.py --- a/configs/ruby/MOESI_CMP_token.py Wed Aug 14 10:51:47 2013 -0400 +++ b/configs/ruby/MOESI_CMP_token.py Sat Aug 17 12:24:40 2013 -0500 @@ -114,6 +114,7 @@ options.allow_atomic_migration, send_evictions = ( options.cpu_type == "detailed"), + transitions_per_cycle = options.ports, ruby_system = ruby_system) cpu_seq = RubySequencer(version = i, @@ -149,6 +150,7 @@ cntrl_id = cntrl_count, L2cache = l2_cache, N_tokens = n_tokens, + transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) @@ -189,6 +191,7 @@ size = dir_size), memBuffer = mem_cntrl, l2_select_num_bits = l2_bits, + transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) @@ -206,6 +209,7 @@ dma_cntrl = DMA_Controller(version = i, cntrl_id = cntrl_count, dma_sequencer = dma_seq, + transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) diff -r afa9f7f4ee46 -r bc3b52b32bad configs/ruby/MOESI_hammer.py --- a/configs/ruby/MOESI_hammer.py Wed Aug 14 10:51:47 2013 -0400 +++ b/configs/ruby/MOESI_hammer.py Sat Aug 17 12:24:40 2013 -0500 @@ -107,6 +107,7 @@ options.allow_atomic_migration, send_evictions = ( options.cpu_type == "detailed"), + transitions_per_cycle = options.ports, ruby_system = ruby_system) cpu_seq = RubySequencer(version = i, @@ -197,6 +198,7 @@ memBuffer = mem_cntrl, probe_filter_enabled = options.pf_on, full_bit_dir_enabled = options.dir_on, + transitions_per_cycle = options.ports, ruby_system = ruby_system) if options.recycle_latency: @@ -217,6 +219,7 @@ dma_cntrl = DMA_Controller(version = i, cntrl_id = cntrl_count, dma_sequencer = dma_seq, + transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) diff -r afa9f7f4ee46 -r bc3b52b32bad configs/ruby/Ruby.py --- a/configs/ruby/Ruby.py Wed Aug 14 10:51:47 2013 -0400 +++ b/configs/ruby/Ruby.py Sat Aug 17 12:24:40 2013 -0500 @@ -52,6 +52,11 @@ default='2GHz', help="Clock for blocks running at Ruby system's speed") + # Options related to cache structure + parser.add_option("--ports", action="store", type="int", default=4, + help="used of transitions per cycle which is a proxy \ + for the number of ports.") + # ruby network options parser.add_option("--topology", type="string", default="Crossbar", help="check src/mem/ruby/network/topologies for complete set") diff -r afa9f7f4ee46 -r bc3b52b32bad tests/configs/memtest-ruby.py --- a/tests/configs/memtest-ruby.py Wed Aug 14 10:51:47 2013 -0400 +++ b/tests/configs/memtest-ruby.py Sat Aug 17 12:24:40 2013 -0500 @@ -64,6 +64,7 @@ options.l1i_assoc=2 options.l2_assoc=2 options.l3_assoc=2 +options.ports=32 #MAX CORES IS 8 with the fals sharing method nb_cores = 8 diff -r afa9f7f4ee46 -r bc3b52b32bad tests/configs/rubytest-ruby.py --- a/tests/configs/rubytest-ruby.py Wed Aug 14 10:51:47 2013 -0400 +++ b/tests/configs/rubytest-ruby.py Sat Aug 17 12:24:40 2013 -0500 @@ -65,6 +65,7 @@ options.l1i_assoc=2 options.l2_assoc=2 options.l3_assoc=2 +options.ports=32 # Turn on flush check for the hammer protocol check_flush = False