diff -r fdad76a1fba4 -r 73704b98a61d src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py	Mon Aug 19 10:33:57 2013 +0100
+++ b/src/cpu/BaseCPU.py	Mon Aug 19 10:34:04 2013 +0100
@@ -51,7 +51,6 @@
 from InstTracer import InstTracer
 from ExeTracer import ExeTracer
 from MemObject import MemObject
-from BranchPredictor import BranchPredictor
 from ClockDomain import *
 
 default_tracer = ExeTracer()
@@ -210,8 +209,6 @@
     dcache_port = MasterPort("Data Port")
     _cached_ports = ['icache_port', 'dcache_port']
 
-    branchPred = Param.BranchPredictor(NULL, "Branch Predictor")
-
     if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
         _cached_ports += ["itb.walker.port", "dtb.walker.port"]
 
diff -r fdad76a1fba4 -r 73704b98a61d src/cpu/inorder/InOrderCPU.py
--- a/src/cpu/inorder/InOrderCPU.py	Mon Aug 19 10:33:57 2013 +0100
+++ b/src/cpu/inorder/InOrderCPU.py	Mon Aug 19 10:34:04 2013 +0100
@@ -68,4 +68,6 @@
     div32Latency = Param.Cycles(1, "Latency for 32-bit Divide Operations")
     div32RepeatRate = Param.Cycles(1, "Repeat Rate for 32-bit Divide Operations")
 
-    branchPred = BranchPredictor(numThreads = Parent.numThreads)
+    branchPred = Param.BranchPredictor(BranchPredictor(numThreads =
+                                                       Parent.numThreads),
+                                       "Branch Predictor")
diff -r fdad76a1fba4 -r 73704b98a61d src/cpu/o3/O3CPU.py
--- a/src/cpu/o3/O3CPU.py	Mon Aug 19 10:33:57 2013 +0100
+++ b/src/cpu/o3/O3CPU.py	Mon Aug 19 10:34:04 2013 +0100
@@ -125,7 +125,9 @@
     smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
     smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
 
-    branchPred = BranchPredictor(numThreads = Parent.numThreads)
+    branchPred = Param.BranchPredictor(BranchPredictor(numThreads =
+                                                       Parent.numThreads),
+                                       "Branch Predictor")
     needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
                           "Enable TSO Memory model")