diff -r fa72e0042d89 -r c5aeb439b1c3 src/dev/Ethernet.py --- a/src/dev/Ethernet.py Mon Aug 19 10:34:12 2013 +0100 +++ b/src/dev/Ethernet.py Mon Aug 19 10:34:18 2013 +0100 @@ -26,51 +26,9 @@ # # Authors: Nathan Binkert -from m5.SimObject import SimObject from m5.params import * from m5.proxy import * -from Pci import PciDevice - -class EtherObject(SimObject): - type = 'EtherObject' - abstract = True - cxx_header = "dev/etherobject.hh" - -class EtherLink(EtherObject): - type = 'EtherLink' - cxx_header = "dev/etherlink.hh" - int0 = SlavePort("interface 0") - int1 = SlavePort("interface 1") - delay = Param.Latency('0us', "packet transmit delay") - delay_var = Param.Latency('0ns', "packet transmit delay variability") - speed = Param.NetworkBandwidth('1Gbps', "link speed") - dump = Param.EtherDump(NULL, "dump object") - -class EtherBus(EtherObject): - type = 'EtherBus' - cxx_header = "dev/etherbus.hh" - loopback = Param.Bool(True, "send packet back to the sending interface") - dump = Param.EtherDump(NULL, "dump object") - speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second") - -class EtherTap(EtherObject): - type = 'EtherTap' - cxx_header = "dev/ethertap.hh" - bufsz = Param.Int(10000, "tap buffer size") - dump = Param.EtherDump(NULL, "dump object") - port = Param.UInt16(3500, "tap port") - -class EtherDump(SimObject): - type = 'EtherDump' - cxx_header = "dev/etherdump.hh" - file = Param.String("dump file") - maxlen = Param.Int(96, "max portion of packet data to dump") - -class EtherDevice(PciDevice): - type = 'EtherDevice' - abstract = True - cxx_header = "dev/etherdevice.hh" - interface = MasterPort("Ethernet Interface") +from EtherDevice import * class IGbE(EtherDevice): # Base class for two IGbE adapters listed above @@ -125,30 +83,6 @@ phy_pid = 0x0141 phy_epid = 0x0CC0 -class EtherDevBase(EtherDevice): - type = 'EtherDevBase' - abstract = True - cxx_header = "dev/etherdevice.hh" - - hardware_address = Param.EthernetAddr(NextEthernetAddr, - "Ethernet Hardware Address") - - dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") - dma_read_factor = Param.Latency('0us', "multiplier for dma reads") - dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") - dma_write_factor = Param.Latency('0us', "multiplier for dma writes") - - rx_delay = Param.Latency('1us', "Receive Delay") - tx_delay = Param.Latency('1us', "Transmit Delay") - rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo") - tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo") - - rx_filter = Param.Bool(True, "Enable Receive Filter") - intr_delay = Param.Latency('10us', "Interrupt propagation delay") - rx_thread = Param.Bool(False, "dedicated kernel thread for transmit") - tx_thread = Param.Bool(False, "dedicated kernel threads for receive") - rss = Param.Bool(False, "Receive Side Scaling") - class NSGigE(EtherDevBase): type = 'NSGigE' cxx_header = "dev/ns_gige.hh" @@ -176,8 +110,6 @@ BAR0Size = '256B' BAR1Size = '4kB' - - class Sinic(EtherDevBase): type = 'Sinic' cxx_class = 'Sinic::Device' @@ -215,5 +147,3 @@ InterruptLine = 0x1e InterruptPin = 0x01 BAR0Size = '64kB' - -