diff -r 8bddb3879c16 src/mem/cache/prefetch/stride.cc
--- a/src/mem/cache/prefetch/stride.cc	Mon Oct 07 18:05:50 2013 -0500
+++ b/src/mem/cache/prefetch/stride.cc	Tue Oct 08 08:42:06 2013 -0500
@@ -47,7 +47,7 @@
         return;
     }
 
-    Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
+    Addr data_addr = pkt->getAddr();
     MasterID master_id = useMasterId ? pkt->req->masterId() : 0;
     Addr pc = pkt->req->getPC();
     assert(master_id < Max_Contexts);
@@ -63,7 +63,7 @@
     if (iter != tab.end()) {
         // Hit in table
 
-        int new_stride = blk_addr - (*iter)->missAddr;
+        int new_stride = data_addr - (*iter)->missAddr;
         bool stride_match = (new_stride == (*iter)->stride);
 
         if (stride_match && new_stride != 0) {
@@ -75,18 +75,18 @@
                 (*iter)->confidence = 0;
         }
 
-        DPRINTF(HWPrefetch, "hit: PC %x blk_addr %x stride %d (%s), conf %d\n",
-                pc, blk_addr, new_stride, stride_match ? "match" : "change",
+        DPRINTF(HWPrefetch, "hit: PC %x data_addr %x stride %d (%s), conf %d\n",
+                pc, data_addr, new_stride, stride_match ? "match" : "change",
                 (*iter)->confidence);
 
-        (*iter)->missAddr = blk_addr;
+        (*iter)->missAddr = data_addr;
 
         if ((*iter)->confidence <= 0)
             return;
 
         for (int d = 1; d <= degree; d++) {
-            Addr new_addr = blk_addr + d * new_stride;
-            if (pageStop && !samePage(blk_addr, new_addr)) {
+            Addr new_addr = data_addr + d * new_stride;
+            if (pageStop && !samePage(data_addr, new_addr)) {
                 // Spanned the page, so now stop
                 pfSpanPage += degree - d + 1;
                 return;
@@ -101,7 +101,7 @@
         // Miss in table
         // Find lowest confidence and replace
 
-        DPRINTF(HWPrefetch, "miss: PC %x blk_addr %x\n", pc, blk_addr);
+        DPRINTF(HWPrefetch, "miss: PC %x data_addr %x\n", pc, data_addr);
 
         if (tab.size() >= 256) { //set default table size is 256
             std::list<StrideEntry*>::iterator min_pos = tab.begin();
@@ -121,7 +121,7 @@
 
         StrideEntry *new_entry = new StrideEntry;
         new_entry->instAddr = pc;
-        new_entry->missAddr = blk_addr;
+        new_entry->missAddr = data_addr;
         new_entry->stride = 0;
         new_entry->confidence = 0;
         tab.push_back(new_entry);
diff -r 8bddb3879c16 src/mem/cache/prefetch/base.cc
--- a/src/mem/cache/prefetch/base.cc	Mon Oct 07 18:05:50 2013 -0500
+++ b/src/mem/cache/prefetch/base.cc	Tue Oct 08 08:42:06 2013 -0500
@@ -60,7 +60,9 @@
     : ClockedObject(p), size(p->size), latency(p->latency), degree(p->degree),
       useMasterId(p->use_master_id), pageStop(!p->cross_pages),
       serialSquash(p->serial_squash), onlyData(p->data_accesses_only),
-      system(p->sys), masterId(system->getMasterId(name()))
+      onMissOnly(p->on_miss_only), onReadOnly(p->on_read_only),
+      onPrefetch(p->on_prefetch), system(p->sys),
+      masterId(system->getMasterId(name()))
 {
 }
 
@@ -182,7 +184,14 @@
 Tick
 BasePrefetcher::notify(PacketPtr &pkt, Tick tick)
 {
-    if (!pkt->req->isUncacheable() && !(pkt->req->isInstFetch() && onlyData)) {
+    // Don't consult the prefetcher if any of the following conditons are true
+    // 1) The request is uncacheable
+    // 2) The request is a fetch, but we are only prefeching data
+    // 3) The request is a cache hit, but we are only training on misses
+    // 4) THe request is a write, but we are only training on reads
+    if (!pkt->req->isUncacheable() && !(pkt->req->isInstFetch() && onlyData) &&
+        !(onMissOnly && inCache(pkt->getAddr())) &&
+        !(onReadOnly && !pkt->isRead())) {
         // Calculate the blk address
         Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
 
@@ -253,6 +262,11 @@
             prefetch->req->setThreadContext(pkt->req->contextId(),
                                             pkt->req->threadId());
 
+            // Tag orefetch reqeuests with corresponding PC to train lower
+            // cache-level prefetchers
+            if (onPrefetch && pkt->req->hasPC())
+                prefetch->req->setPC(pkt->req->getPC());
+
             // We just remove the head if we are full
             if (pf.size() == size) {
                 pfRemovedFull++;
diff -r 8bddb3879c16 src/mem/cache/prefetch/base.hh
--- a/src/mem/cache/prefetch/base.hh	Mon Oct 07 18:05:50 2013 -0500
+++ b/src/mem/cache/prefetch/base.hh	Tue Oct 08 08:42:06 2013 -0500
@@ -89,18 +89,28 @@
     const Cycles latency;
 
     /** The number of prefetches to issue */
-    unsigned degree;
+    const unsigned degree;
 
     /** If patterns should be found per context id */
-    bool useMasterId;
+    const bool useMasterId;
     /** Do we prefetch across page boundaries. */
-    bool pageStop;
+    const bool pageStop;
 
     /** Do we remove prefetches with later times than a new miss.*/
-    bool serialSquash;
+    const bool serialSquash;
 
     /** Do we prefetch on only data reads, or on inst reads as well. */
-    bool onlyData;
+    const bool onlyData;
+
+    /** Do we trigger/train prefetch on cache misses only, or all accesses. */
+    const bool onMissOnly;
+
+    /** Do we trigger/train prefetch on reads only, or all accesses. */
+    const bool onReadOnly;
+
+    /** Do we tag prefetch's with PC addresses, allowing lower pc-based
+        prefetchers to prefetch on prefetch requests */
+    const bool onPrefetch;
 
     /** System we belong to */
     System* system;
diff -r 8bddb3879c16 src/mem/cache/prefetch/Prefetcher.py
--- a/src/mem/cache/prefetch/Prefetcher.py	Mon Oct 07 18:05:50 2013 -0500
+++ b/src/mem/cache/prefetch/Prefetcher.py	Tue Oct 08 08:42:06 2013 -0500
@@ -59,6 +59,12 @@
          "Use the master id to separate calculations of prefetches")
     data_accesses_only = Param.Bool(False,
          "Only prefetch on data not on instruction accesses")
+    on_miss_only = Param.Bool(False,
+         "Only prefetch on miss (as opposed to always)")
+    on_read_only = Param.Bool(False,
+         "Only prefetch on read requests (write requests ignored)")
+    on_prefetch = Param.Bool(True,
+         "Let lower cache prefetcher train on prefetch requests")
     sys = Param.System(Parent.any, "System this device belongs to")
 
 class GHBPrefetcher(BasePrefetcher):
# HG changeset patch
# Parent 8bddb3879c1671d5f21f828295bb9f2e84aee9b5

diff -r 8bddb3879c16 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh	Mon Oct 07 18:05:50 2013 -0500
+++ b/src/mem/cache/cache_impl.hh	Tue Oct 08 08:42:06 2013 -0500
@@ -551,6 +551,17 @@
                 // move it ahead of mshrs that are ready
                 // mshrQueue.moveToFront(mshr);
             }
+
+            // We should call the prefetcher reguardless if the request is
+            // satisfied or not, reguardless if the request is in the MSHR or
+            // not.  The request could be a ReadReq hit, but still not
+            // satisfied (potentially because of a prior write to the same
+            // cache line.  So, even when not satisfied, tehre is an MSHR
+            // already allocated for this, we need to let the prefetcher know
+            // about the request
+            if (prefetcher) {
+                next_pf_time = prefetcher->notify(pkt, time);
+            }
         } else {
             // no MSHR
             assert(pkt->req->masterId() < system->maxMasters());
diff -r 8bddb3879c16 src/mem/request.hh
--- a/src/mem/request.hh	Mon Oct 07 18:05:50 2013 -0500
+++ b/src/mem/request.hh	Tue Oct 08 08:42:06 2013 -0500
@@ -501,6 +501,13 @@
         return _threadId;
     }
 
+    void
+    setPC(Addr pc)
+    {
+        privateFlags.set(VALID_PC);
+        _pc = pc;
+    }
+
     bool
     hasPC() const
     {