# HG changeset patch # Parent 3eb46625223b96c84cc9e40bed21b86b6066d32d diff -r 3eb46625223b src/mem/cache/prefetch/Prefetcher.py --- a/src/mem/cache/prefetch/Prefetcher.py Thu Sep 05 19:16:37 2013 -0500 +++ b/src/mem/cache/prefetch/Prefetcher.py Thu Sep 05 20:15:57 2013 -0500 @@ -65,6 +65,8 @@ "Only prefetch on read requests (write requests ignored)") on_prefetch = Param.Bool(True, "Let lower cache prefetchers train on prefetch requests") + inst_tagged = Param.Bool(True, + "Perform a tagged prefetch for instruction fetches always") sys = Param.System(Parent.any, "System this device belongs to") class GHBPrefetcher(BasePrefetcher): diff -r 3eb46625223b src/mem/cache/prefetch/stride.hh --- a/src/mem/cache/prefetch/stride.hh Thu Sep 05 19:16:37 2013 -0500 +++ b/src/mem/cache/prefetch/stride.hh Thu Sep 05 20:15:57 2013 -0500 @@ -65,10 +65,12 @@ std::list table[Max_Contexts]; + bool instTagged; + public: StridePrefetcher(const Params *p) - : BasePrefetcher(p) + : BasePrefetcher(p), instTagged(p->inst_tagged) { } diff -r 3eb46625223b src/mem/cache/prefetch/stride.cc --- a/src/mem/cache/prefetch/stride.cc Thu Sep 05 19:16:37 2013 -0500 +++ b/src/mem/cache/prefetch/stride.cc Thu Sep 05 20:15:57 2013 -0500 @@ -54,6 +54,23 @@ assert(master_id < Max_Contexts); std::list &tab = table[master_id]; + // Revert to simple N-block ahead prefetch for instruction fetches + if (instTagged && pkt->req->isInstFetch()) { + for (int d = 1; d <= degree; d++) { + Addr new_addr = data_addr + d * blkSize; + if (pageStop && !samePage(data_addr, new_addr)) { + // Spanned the page, so now stop + pfSpanPage += degree - d + 1; + return; + } + DPRINTF(HWPrefetch, "queuing prefetch to %x @ %d\n", + new_addr, latency); + addresses.push_back(new_addr); + delays.push_back(latency); + } + return; + } + /* Scan Table for instAddr Match */ std::list::iterator iter; for (iter = tab.begin(); iter != tab.end(); iter++) {