diff -r e672a39fd426 -r 43b6cd6d74b1 src/arch/generic/mmapped_ipr.hh
--- a/src/arch/generic/mmapped_ipr.hh	Thu Oct 03 11:00:18 2013 +0200
+++ b/src/arch/generic/mmapped_ipr.hh	Mon Oct 07 13:22:33 2013 +0200
@@ -49,23 +49,12 @@
      * Memory requests with the MMAPPED_IPR flag are generally mapped
      * to registers. There is a class of these registers that are
      * internal to gem5, for example gem5 pseudo-ops in virtualized
-     * mode.
-     *
-     * In order to make the IPR space manageable we always set bit 63
-     * (IPR_GENERIC) for accesses that should be handled by the
-     * generic ISA code. Architectures may use the rest of the IPR
-     * space internally.
+     * mode. Such IPRs always have the flag GENERIC_IPR set and are
+     * handled by this code.
      */
 
-    /** Is this a generic IPR access? */
-    const Addr IPR_GENERIC = ULL(0x8000000000000000);
-
-    /** @{ */
-    /** Mask when extracting the class of a generic IPR */
-    const Addr IPR_CLASS_MASK = ULL(0x7FFF000000000000);
     /** Shift amount when extracting the class of a generic IPR */
     const int IPR_CLASS_SHIFT = 48;
-    /** @} */
 
     /** Mask to extract the offset in within a generic IPR class */
     const Addr IPR_IN_CLASS_MASK = ULL(0x0000FFFFFFFFFFFF);
@@ -94,7 +83,7 @@
     inline Addr
     iprAddressPseudoInst(uint8_t func, uint8_t subfunc)
     {
-        return IPR_GENERIC | (IPR_CLASS_PSEUDO_INST << IPR_CLASS_SHIFT)  |
+        return (IPR_CLASS_PSEUDO_INST << IPR_CLASS_SHIFT)  |
             (func << 8) | subfunc;
     }
 
@@ -113,7 +102,9 @@
     inline bool
     isGenericIprAccess(const Packet *pkt)
     {
-        return pkt->getAddr() & IPR_GENERIC;
+        Request::Flags flags(pkt->req->getFlags());
+        return (flags & Request::MMAPPED_IPR) &&
+            (flags & Request::GENERIC_IPR);
     }
 
     /**
diff -r e672a39fd426 -r 43b6cd6d74b1 src/arch/generic/mmapped_ipr.cc
--- a/src/arch/generic/mmapped_ipr.cc	Thu Oct 03 11:00:18 2013 +0200
+++ b/src/arch/generic/mmapped_ipr.cc	Mon Oct 07 13:22:33 2013 +0200
@@ -53,7 +53,7 @@
 GenericISA::handleGenericIprRead(ThreadContext *xc, Packet *pkt)
 {
     Addr va(pkt->getAddr());
-    Addr cls((va & IPR_CLASS_MASK) >> IPR_CLASS_SHIFT);
+    Addr cls(va >> IPR_CLASS_SHIFT);
 
     switch (cls) {
     case IPR_CLASS_PSEUDO_INST:
@@ -70,7 +70,7 @@
 GenericISA::handleGenericIprWrite(ThreadContext *xc, Packet *pkt)
 {
     Addr va(pkt->getAddr());
-    Addr cls((va & IPR_CLASS_MASK) >> IPR_CLASS_SHIFT);
+    Addr cls(va >> IPR_CLASS_SHIFT);
 
     switch (cls) {
     case IPR_CLASS_PSEUDO_INST:
diff -r e672a39fd426 -r 43b6cd6d74b1 src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc	Thu Oct 03 11:00:18 2013 +0200
+++ b/src/arch/x86/tlb.cc	Mon Oct 07 13:22:33 2013 +0200
@@ -257,7 +257,7 @@
             req->setPaddr(x86LocalAPICAddress(tc->contextId(),
                                               paddr - apicRange.start()));
         } else if (m5opRange.contains(paddr)) {
-            req->setFlags(Request::MMAPPED_IPR);
+            req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR);
             req->setPaddr(GenericISA::iprAddressPseudoInst(
                               (paddr >> 8) & 0xFF,
                               paddr & 0xFF));
diff -r e672a39fd426 -r 43b6cd6d74b1 src/mem/request.hh
--- a/src/mem/request.hh	Thu Oct 03 11:00:18 2013 +0200
+++ b/src/mem/request.hh	Mon Oct 07 13:22:33 2013 +0200
@@ -127,6 +127,10 @@
     /** The request should be marked as LRU. */
     static const FlagsType EVICT_NEXT                  = 0x04000000;
 
+    /** The request should be handled by the generic IPR code (only
+     * valid together with MMAPPED_IPR) */
+    static const FlagsType GENERIC_IPR                 = 0x08000000;
+
     /** These flags are *not* cleared when a Request object is reused
        (assigned a new address). */
     static const FlagsType STICKY_FLAGS = INST_FETCH;