diff -r 193b806c1eaf -r 34a337481b2e src/arch/x86/isa/formats/cpuid.isa
--- a/src/arch/x86/isa/formats/cpuid.isa	Sun Aug 22 18:27:35 2010 -0700
+++ b/src/arch/x86/isa/formats/cpuid.isa	Sun Aug 22 18:28:47 2010 -0700
@@ -45,6 +45,8 @@
                 OpClass __opClass) :
             X86ISA::X86StaticInst(_mnemonic, _machInst, __opClass)
         {
+            flags[IsSerializing] = 1;
+            flags[IsSerializeAfter] = 1;
         }
 
         std::string generateDisassembly(Addr pc,
diff -r 193b806c1eaf -r 34a337481b2e src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py	Sun Aug 22 18:27:35 2010 -0700
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py	Sun Aug 22 18:28:47 2010 -0700
@@ -37,10 +37,12 @@
 
 microcode = '''
 def macroop IRET_REAL {
+    .serializing
     panic "Real mode iret isn't implemented!"
 };
 
 def macroop IRET_PROT {
+    .serializing
     .adjust_env oszIn64Override
 
     # Check for a nested task. This isn't supported at the moment.
diff -r 193b806c1eaf -r 34a337481b2e src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py	Sun Aug 22 18:27:35 2010 -0700
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py	Sun Aug 22 18:28:47 2010 -0700
@@ -174,16 +174,19 @@
 };
 
 def macroop MOV_C_R {
+    .serializing
     .adjust_env maxOsz
     wrcr reg, regm
 };
 
 def macroop MOV_R_C {
+    .serializing
     .adjust_env maxOsz
     rdcr reg, regm
 };
 
 def macroop MOV_D_R {
+    .serializing
     .adjust_env maxOsz
     wrdr reg, regm
 };
diff -r 193b806c1eaf -r 34a337481b2e src/arch/x86/isa/insts/system/invlpg.py
--- a/src/arch/x86/isa/insts/system/invlpg.py	Sun Aug 22 18:27:35 2010 -0700
+++ b/src/arch/x86/isa/insts/system/invlpg.py	Sun Aug 22 18:28:47 2010 -0700
@@ -40,10 +40,12 @@
 
 microcode = '''
 def macroop INVLPG_M {
+    .serializing
     tia seg, sib, disp
 };
 
 def macroop INVLPG_P {
+    .serializing
     rdip t7
     tia seg, riprel, disp
 };
diff -r 193b806c1eaf -r 34a337481b2e src/arch/x86/isa/insts/system/msrs.py
--- a/src/arch/x86/isa/insts/system/msrs.py	Sun Aug 22 18:27:35 2010 -0700
+++ b/src/arch/x86/isa/insts/system/msrs.py	Sun Aug 22 18:28:47 2010 -0700
@@ -50,6 +50,7 @@
 
 def macroop WRMSR
 {
+    .serializing
     mov t2, t2, rax, dataSize=4
     slli t3, rdx, 32, dataSize=8
     or t2, t2, t3, dataSize=8
diff -r 193b806c1eaf -r 34a337481b2e src/arch/x86/isa/insts/system/segmentation.py
--- a/src/arch/x86/isa/insts/system/segmentation.py	Sun Aug 22 18:27:35 2010 -0700
+++ b/src/arch/x86/isa/insts/system/segmentation.py	Sun Aug 22 18:28:47 2010 -0700
@@ -38,6 +38,7 @@
 microcode = '''
 def macroop LGDT_M
 {
+    .serializing
     .adjust_env maxOsz
 
     # Get the limit
@@ -50,6 +51,7 @@
 
 def macroop LGDT_P
 {
+    .serializing
     .adjust_env maxOsz
 
     rdip t7
@@ -68,6 +70,7 @@
 
 def macroop LGDT_16_M
 {
+    .serializing
     .adjust_env maxOsz
 
     # Get the limit
@@ -81,6 +84,7 @@
 
 def macroop LGDT_16_P
 {
+    .serializing
     .adjust_env maxOsz
 
     rdip t7
@@ -95,6 +99,7 @@
 
 def macroop LIDT_M
 {
+    .serializing
     .adjust_env maxOsz
 
     # Get the limit
@@ -107,6 +112,7 @@
 
 def macroop LIDT_P
 {
+    .serializing
     .adjust_env maxOsz
 
     rdip t7
@@ -125,6 +131,7 @@
 
 def macroop LIDT_16_M
 {
+    .serializing
     .adjust_env maxOsz
 
     # Get the limit
@@ -138,6 +145,7 @@
 
 def macroop LIDT_16_P
 {
+    .serializing
     .adjust_env maxOsz
 
     rdip t7
@@ -152,6 +160,7 @@
 
 def macroop LTR_R
 {
+    .serializing
     chks reg, t0, TRCheck
     limm t4, 0, dataSize=8
     srli t4, reg, 3, dataSize=2
@@ -168,6 +177,7 @@
 
 def macroop LTR_M
 {
+    .serializing
     ld t5, seg, sib, disp, dataSize=2
     chks t5, t0, TRCheck
     limm t4, 0, dataSize=8
@@ -185,6 +195,7 @@
 
 def macroop LTR_P
 {
+    .serializing
     rdip t7
     ld t5, seg, riprel, disp, dataSize=2
     chks t5, t0, TRCheck
@@ -203,6 +214,7 @@
 
 def macroop LLDT_R
 {
+    .serializing
     chks reg, t0, InGDTCheck, flags=(EZF,)
     br label("end"), flags=(CEZF,)
     limm t4, 0, dataSize=8
@@ -219,6 +231,7 @@
 
 def macroop LLDT_M
 {
+    .serializing
     ld t5, seg, sib, disp, dataSize=2
     chks t5, t0, InGDTCheck, flags=(EZF,)
     br label("end"), flags=(CEZF,)
@@ -236,6 +249,7 @@
 
 def macroop LLDT_P
 {
+    .serializing
     rdip t7
     ld t5, seg, riprel, disp, dataSize=2
     chks t5, t0, InGDTCheck, flags=(EZF,)