diff -r 07352f119e48 src/mem/cache/BaseCache.py
--- a/src/mem/cache/BaseCache.py	Mon Apr 22 13:20:31 2013 -0400
+++ b/src/mem/cache/BaseCache.py	Tue Oct 29 14:22:49 2013 +0100
@@ -50,6 +50,7 @@
     assoc = Param.Int("associativity")
     block_size = Param.Int("block size in bytes")
     hit_latency = Param.Cycles("The hit latency for this cache")
+    write_latency = Param.Cycles("The write latency for this cache")
     response_latency = Param.Cycles(
             "Additional cache latency for the return path to core on a miss");
     max_miss_count = Param.Counter(0,
diff -r 07352f119e48 src/mem/cache/base.hh
--- a/src/mem/cache/base.hh	Mon Apr 22 13:20:31 2013 -0400
+++ b/src/mem/cache/base.hh	Tue Oct 29 14:22:49 2013 +0100
@@ -251,6 +251,11 @@
     const Cycles hitLatency;
 
     /**
+     * The latency of a write in this device.
+     */
+    const Cycles writeLatency;
+
+    /**
      * The latency of sending reponse to its upper level cache/core on a
      * linefill. In most contemporary processors, the return path on a cache
      * miss is much quicker that the hit latency. The responseLatency parameter
diff -r 07352f119e48 src/mem/cache/base.cc
--- a/src/mem/cache/base.cc	Mon Apr 22 13:20:31 2013 -0400
+++ b/src/mem/cache/base.cc	Tue Oct 29 14:22:49 2013 +0100
@@ -70,6 +70,7 @@
                   MSHRQueue_WriteBuffer),
       blkSize(p->block_size),
       hitLatency(p->hit_latency),
+      writeLatency(p->write_latency),
       responseLatency(p->response_latency),
       numTarget(p->tgts_per_mshr),
       forwardSnoops(p->forward_snoops),
diff -r 07352f119e48 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh	Mon Apr 22 13:20:31 2013 -0400
+++ b/src/mem/cache/cache_impl.hh	Tue Oct 29 14:22:49 2013 +0100
@@ -282,7 +282,16 @@
         uncacheableFlush(pkt);
         blk = NULL;
         lat = hitLatency;
-        return false;
+	// Update latency decided by if it is read or write
+	if(pkt->isWrite()) {
+		lat = writeLatency;
+	}
+	return false;
+    }
+
+    // Update latency decided by if it is read or write
+    if(pkt->isWrite()) {
+	lat = writeLatency;
     }
 
     int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
diff -r 07352f119e48 src/mem/cache/tags/lru.hh
--- a/src/mem/cache/tags/lru.hh	Mon Apr 22 13:20:31 2013 -0400
+++ b/src/mem/cache/tags/lru.hh	Tue Oct 29 14:22:49 2013 +0100
@@ -151,7 +151,7 @@
      * @param lat The access latency.
      * @return Pointer to the cache block if found.
      */
-    BlkType* accessBlock(Addr addr, Cycles &lat, int context_src);
+    BlkType* accessBlock(Addr addr, Cycles lat, int context_src);
 
     /**
      * Finds the given address in the cache, do not update replacement data.
diff -r 07352f119e48 src/mem/cache/tags/lru.cc
--- a/src/mem/cache/tags/lru.cc	Mon Apr 22 13:20:31 2013 -0400
+++ b/src/mem/cache/tags/lru.cc	Tue Oct 29 14:22:49 2013 +0100
@@ -115,20 +115,20 @@
     delete [] sets;
 }
 
+// Modification : "lat" passed by value (not by reference) to take in account the right access latency (read or write)
 LRU::BlkType*
-LRU::accessBlock(Addr addr, Cycles &lat, int master_id)
+LRU::accessBlock(Addr addr, Cycles lat, int master_id)
 {
     Addr tag = extractTag(addr);
     unsigned set = extractSet(addr);
     BlkType *blk = sets[set].findBlk(tag);
-    lat = hitLatency;
     if (blk != NULL) {
         // move this block to head of the MRU list
         sets[set].moveToHead(blk);
         DPRINTF(CacheRepl, "set %x: moving blk %x to MRU\n",
                 set, regenerateBlkAddr(tag, set));
         if (blk->whenReady > curTick()
-            && cache->ticksToCycles(blk->whenReady - curTick()) > hitLatency) {
+            && cache->ticksToCycles(blk->whenReady - curTick()) > lat) {
             lat = cache->ticksToCycles(blk->whenReady - curTick());
         }
         blk->refCount += 1;