diff -r 81d7551dd3be -r 4a46e9394667 src/cpu/checker/cpu_impl.hh
--- a/src/cpu/checker/cpu_impl.hh	Fri Nov 01 11:56:34 2013 -0400
+++ b/src/cpu/checker/cpu_impl.hh	Tue Nov 05 16:27:33 2013 +0000
@@ -607,10 +607,10 @@
             thread->setIntReg(idx, mismatch_val);
             break;
           case FloatRegClass:
-            thread->setFloatRegBits(idx, mismatch_val);
+            thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, mismatch_val);
             break;
           case CCRegClass:
-            thread->setCCReg(idx, mismatch_val);
+            thread->setCCReg(idx - TheISA::CC_Reg_Base, mismatch_val);
             break;
           case MiscRegClass:
             thread->setMiscReg(idx - TheISA::Misc_Reg_Base,
@@ -628,10 +628,10 @@
             thread->setIntReg(idx, res);
             break;
           case FloatRegClass:
-            thread->setFloatRegBits(idx, res);
+            thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, res);
             break;
           case CCRegClass:
-            thread->setCCReg(idx, res);
+            thread->setCCReg(idx - TheISA::CC_Reg_Base, res);
             break;
           case MiscRegClass:
             // Try to get the proper misc register index for ARM here...