diff -r 329b8a20958b src/mem/ruby/system/RubyMemoryControl.hh --- a/src/mem/ruby/system/RubyMemoryControl.hh Tue Nov 12 11:46:48 2013 -0500 +++ b/src/mem/ruby/system/RubyMemoryControl.hh Thu Nov 14 15:08:21 2013 +0530 @@ -45,6 +45,9 @@ #include "mem/ruby/system/System.hh" #include "params/RubyMemoryControl.hh" #include "sim/sim_object.hh" +#include "DRAM.hh" +#include +#include // This constant is part of the definition of tFAW; see // the comments in header to RubyMemoryControl.cc @@ -88,7 +91,9 @@ // not used in Ruby memory controller const int getChannel(const physical_address_t addr) const; - const int getRow(const physical_address_t addr) const; + //used + const int getRow(const physical_address_t addr) const; + //added by SS int getBanksPerRank() { return m_banks_per_rank; }; @@ -115,7 +120,8 @@ Consumer* m_consumer_ptr; // Consumer to signal a wakeup() std::string m_description; int m_msg_counter; - + int m_rows_per_bank; + int m_row_bit_0; int m_banks_per_rank; int m_ranks_per_dimm; int m_dimms_per_channel; @@ -124,6 +130,7 @@ int m_dimm_bit_0; unsigned int m_bank_queue_size; int m_bank_busy_time; + int d_bank_busy_time; int m_rank_rank_delay; int m_read_write_delay; int m_basic_bus_busy_time; @@ -165,6 +172,8 @@ int m_idleCount; // watchdog timer for shutting down MemCntrlProfiler* m_profiler_ptr; + DRAMProfiler* d_profiler_ptr; + std::ofstream p_out; }; std::ostream& operator<<(std::ostream& out, const RubyMemoryControl& obj); diff -r 329b8a20958b src/mem/ruby/system/RubyMemoryControl.cc --- a/src/mem/ruby/system/RubyMemoryControl.cc Tue Nov 12 11:46:48 2013 -0500 +++ b/src/mem/ruby/system/RubyMemoryControl.cc Thu Nov 14 15:08:21 2013 +0530 @@ -116,6 +116,7 @@ #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" #include "mem/ruby/system/RubyMemoryControl.hh" #include "mem/ruby/system/System.hh" +#include "DRAM.hh" using namespace std; @@ -152,6 +153,7 @@ m_banks_per_rank = p->banks_per_rank; m_ranks_per_dimm = p->ranks_per_dimm; m_dimms_per_channel = p->dimms_per_channel; + m_row_bit_0 = p->row_bit_0; m_bank_bit_0 = p->bank_bit_0; m_rank_bit_0 = p->rank_bit_0; m_dimm_bit_0 = p->dimm_bit_0; @@ -160,16 +162,23 @@ m_rank_rank_delay = p->rank_rank_delay; m_read_write_delay = p->read_write_delay; m_basic_bus_busy_time = p->basic_bus_busy_time; - m_mem_ctl_latency = p->mem_ctl_latency; + m_mem_ctl_latency = Cycles(p->mem_ctl_latency); m_refresh_period = p->refresh_period; m_tFaw = p->tFaw; m_mem_random_arbitrate = p->mem_random_arbitrate; - m_mem_fixed_delay = p->mem_fixed_delay; + m_mem_fixed_delay = Cycles(p->mem_fixed_delay); + m_rows_per_bank=int(pow(2,(m_bank_bit_0-m_row_bit_0))); m_profiler_ptr = new MemCntrlProfiler(name(), m_banks_per_rank, m_ranks_per_dimm, m_dimms_per_channel); + + d_profiler_ptr = new DRAMProfiler( m_banks_per_rank, + m_ranks_per_dimm, + m_dimms_per_channel); + + } void @@ -273,6 +282,7 @@ delete [] m_bankBusyCounter; delete [] m_oldRequest; delete m_profiler_ptr; + delete d_profiler_ptr; } // enqueue new request from directory @@ -417,13 +427,25 @@ } // Not used! +//const int +//RubyMemoryControl::getRow(const physical_address_t addr) const +//{ + // assert(false); + //return -1; +//} + + +// getRow returns an integer that is unique for each +// Row within a bank across this memory controller. const int RubyMemoryControl::getRow(const physical_address_t addr) const { - assert(false); - return -1; + int row = (addr >> m_row_bit_0) & (m_rows_per_bank - 1); + + return row; } + // queueReady determines if the head item in a bank queue // can be issued this cycle bool @@ -508,11 +530,16 @@ DPRINTF(RubyMemory, "Refresh bank %3x\n", bank); m_profiler_ptr->profileMemRefresh(); + + + d_bank_busy_time=d_profiler_ptr->dramRefresh(bank); + m_need_refresh--; m_refresh_bank++; if (m_refresh_bank >= m_total_banks) m_refresh_bank = 0; - m_bankBusyCounter[bank] = m_bank_busy_time; + //m_bankBusyCounter[bank] = m_bank_busy_time; + m_bankBusyCounter[bank] = d_bank_busy_time; m_busBusyCounter_Basic = m_basic_bus_busy_time; m_busBusyCounter_Write = m_basic_bus_busy_time; m_busBusyCounter_ReadNewRank = m_basic_bus_busy_time; @@ -546,11 +573,24 @@ bank, m_event.scheduled() ? 'Y':'N'); if (req.m_msgptr) { // don't enqueue L3 writebacks + + + + int row=getRow(req.m_addr); + if (req.m_is_mem_read){ + m_mem_ctl_latency=Cycles(d_profiler_ptr->dramRequest(bank,row,RD_CMD,d_bank_busy_time)); + + } + else{ + m_mem_ctl_latency=Cycles(d_profiler_ptr->dramRequest(bank,row,WR_CMD,d_bank_busy_time)); + } + enqueueToDirectory(req, Cycles(m_mem_ctl_latency + m_mem_fixed_delay)); } m_oldRequest[bank] = 0; markTfaw(rank); - m_bankBusyCounter[bank] = m_bank_busy_time; + // m_bankBusyCounter[bank] = m_bank_busy_time; + m_bankBusyCounter[bank] = d_bank_busy_time; m_busBusy_WhichRank = rank; if (req.m_is_mem_read) { m_profiler_ptr->profileMemRead(); @@ -668,6 +708,12 @@ } m_profiler_ptr->profileMemInputQ(m_input_queue.size()); } + + + + + d_profiler_ptr->dramCycle(); + } unsigned int @@ -689,6 +735,11 @@ executeCycle(); m_idleCount--; + + if(m_idleCount<3){ + m_idleCount=IDLECOUNT_MAX_VALUE; + } + if (m_idleCount > 0) { assert(!m_event.scheduled()); schedule(m_event, clockEdge(Cycles(1))); @@ -782,6 +833,10 @@ RubyMemoryControl::regStats() { m_profiler_ptr->regStats(); + + d_profiler_ptr->printStats(); + + } RubyMemoryControl * diff -r 329b8a20958b src/mem/ruby/system/RubyMemoryControl.py --- a/src/mem/ruby/system/RubyMemoryControl.py Tue Nov 12 11:46:48 2013 -0500 +++ b/src/mem/ruby/system/RubyMemoryControl.py Thu Nov 14 15:08:21 2013 +0530 @@ -37,19 +37,38 @@ cxx_header = "mem/ruby/system/RubyMemoryControl.hh" version = Param.Int(""); + # banks_per_rank = Param.Int(8, ""); + # ranks_per_dimm = Param.Int(2, ""); + # dimms_per_channel = Param.Int(2, ""); + #bank_bit_0 = Param.Int(8, ""); + #rank_bit_0 = Param.Int(11, ""); + #dimm_bit_0 = Param.Int(12, ""); + #bank_queue_size = Param.Int(12, ""); + #bank_busy_time = Param.Int(11, ""); + #rank_rank_delay = Param.Int(1, ""); + #read_write_delay = Param.Int(2, ""); + #basic_bus_busy_time = Param.Int(2, ""); + #mem_ctl_latency = Param.Cycles(12, ""); + #refresh_period = Param.Cycles(1560, ""); + #tFaw = Param.Int(0, ""); + #mem_random_arbitrate = Param.Int(0, ""); + #mem_fixed_delay = Param.Cycles(0, ""); + + banks_per_rank = Param.Int(8, ""); - ranks_per_dimm = Param.Int(2, ""); - dimms_per_channel = Param.Int(2, ""); - bank_bit_0 = Param.Int(8, ""); - rank_bit_0 = Param.Int(11, ""); - dimm_bit_0 = Param.Int(12, ""); + ranks_per_dimm = Param.Int(1, ""); + dimms_per_channel = Param.Int(1, ""); + row_bit_0=Param.Int(10,""); + bank_bit_0 = Param.Int(23, ""); + rank_bit_0 = Param.Int(26, "") + dimm_bit_0 = Param.Int(24, ""); bank_queue_size = Param.Int(12, ""); - bank_busy_time = Param.Int(11, ""); + bank_busy_time = Param.Int(44, ""); rank_rank_delay = Param.Int(1, ""); read_write_delay = Param.Int(2, ""); basic_bus_busy_time = Param.Int(2, ""); - mem_ctl_latency = Param.Cycles(12, ""); - refresh_period = Param.Cycles(1560, ""); + mem_ctl_latency = Param.Int(600, ""); + refresh_period = Param.Int(6240, ""); tFaw = Param.Int(0, ""); mem_random_arbitrate = Param.Int(0, ""); - mem_fixed_delay = Param.Cycles(0, ""); + mem_fixed_delay = Param.Int(0, ""); diff -r 329b8a20958b src/mem/ruby/system/SConscript --- a/src/mem/ruby/system/SConscript Tue Nov 12 11:46:48 2013 -0500 +++ b/src/mem/ruby/system/SConscript Thu Nov 14 15:08:21 2013 +0530 @@ -40,7 +40,7 @@ SimObject('WireBuffer.py') SimObject('RubySystem.py') SimObject('RubyMemoryControl.py') - +DebugFlag('DDR3mem') Source('DMASequencer.cc') Source('DirectoryMemory.cc') Source('SparseMemory.cc') @@ -56,3 +56,4 @@ Source('System.cc') Source('TimerTable.cc') Source('BankedArray.cc') +Source('DRAM.cc')