diff -r 99bd071911cf -r bf183de554f4 configs/ruby/MESI_CMP_directory.py --- a/configs/ruby/MESI_CMP_directory.py Sun Dec 29 19:29:45 2013 -0600 +++ b/configs/ruby/MESI_CMP_directory.py Wed Jan 01 12:47:01 2014 -0600 @@ -90,7 +90,6 @@ prefetcher = RubyPrefetcher.Prefetcher() l1_cntrl = L1Cache_Controller(version = i, - cntrl_id = cntrl_count, L1Icache = l1i_cache, L1Dcache = l1d_cache, l2_select_num_bits = l2_bits, @@ -132,7 +131,6 @@ start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, - cntrl_id = cntrl_count, L2cache = l2_cache, transitions_per_cycle=options.ports, ruby_system = ruby_system) @@ -167,14 +165,12 @@ dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, - cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, size = dir_size, use_map = options.use_map), memBuffer = mem_cntrl, - l2_select_num_bits = l2_bits, transitions_per_cycle = options.ports, ruby_system = ruby_system) @@ -191,7 +187,6 @@ ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, - cntrl_id = cntrl_count, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) diff -r 99bd071911cf -r bf183de554f4 configs/ruby/MI_example.py --- a/configs/ruby/MI_example.py Sun Dec 29 19:29:45 2013 -0600 +++ b/configs/ruby/MI_example.py Wed Jan 01 12:47:01 2014 -0600 @@ -80,7 +80,6 @@ # Only one unified L1 cache exists. Can cache instructions and data. # l1_cntrl = L1Cache_Controller(version = i, - cntrl_id = cntrl_count, cacheMemory = cache, send_evictions = ( options.cpu_type == "detailed"), @@ -131,7 +130,6 @@ dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, - cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory( \ version = i, @@ -156,7 +154,6 @@ ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, - cntrl_id = cntrl_count, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) diff -r 99bd071911cf -r bf183de554f4 configs/ruby/MOESI_CMP_directory.py --- a/configs/ruby/MOESI_CMP_directory.py Sun Dec 29 19:29:45 2013 -0600 +++ b/configs/ruby/MOESI_CMP_directory.py Wed Jan 01 12:47:01 2014 -0600 @@ -88,7 +88,6 @@ is_icache = False) l1_cntrl = L1Cache_Controller(version = i, - cntrl_id = cntrl_count, L1Icache = l1i_cache, L1Dcache = l1d_cache, l2_select_num_bits = l2_bits, @@ -127,7 +126,6 @@ start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, - cntrl_id = cntrl_count, L2cache = l2_cache, transitions_per_cycle = options.ports, ruby_system = ruby_system) @@ -162,7 +160,6 @@ dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, - cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, size = dir_size, @@ -184,7 +181,6 @@ ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, - cntrl_id = cntrl_count, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) diff -r 99bd071911cf -r bf183de554f4 configs/ruby/MOESI_CMP_token.py --- a/configs/ruby/MOESI_CMP_token.py Sun Dec 29 19:29:45 2013 -0600 +++ b/configs/ruby/MOESI_CMP_token.py Wed Jan 01 12:47:01 2014 -0600 @@ -99,7 +99,6 @@ start_index_bit = block_size_bits) l1_cntrl = L1Cache_Controller(version = i, - cntrl_id = cntrl_count, L1Icache = l1i_cache, L1Dcache = l1d_cache, l2_select_num_bits = l2_bits, @@ -147,7 +146,6 @@ start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, - cntrl_id = cntrl_count, L2cache = l2_cache, N_tokens = n_tokens, transitions_per_cycle = options.ports, @@ -183,7 +181,6 @@ dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, - cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, use_map = options.use_map, @@ -206,7 +203,6 @@ ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, - cntrl_id = cntrl_count, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) diff -r 99bd071911cf -r bf183de554f4 configs/ruby/MOESI_hammer.py --- a/configs/ruby/MOESI_hammer.py Sun Dec 29 19:29:45 2013 -0600 +++ b/configs/ruby/MOESI_hammer.py Wed Jan 01 12:47:01 2014 -0600 @@ -99,7 +99,6 @@ start_index_bit = block_size_bits) l1_cntrl = L1Cache_Controller(version = i, - cntrl_id = cntrl_count, L1Icache = l1i_cache, L1Dcache = l1d_cache, L2cache = l2_cache, @@ -183,7 +182,6 @@ start_index_bit = pf_start_bit) dir_cntrl = Directory_Controller(version = i, - cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory( \ version = i, @@ -216,7 +214,6 @@ ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, - cntrl_id = cntrl_count, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) diff -r 99bd071911cf -r bf183de554f4 configs/ruby/Network_test.py --- a/configs/ruby/Network_test.py Sun Dec 29 19:29:45 2013 -0600 +++ b/configs/ruby/Network_test.py Wed Jan 01 12:47:01 2014 -0600 @@ -83,7 +83,6 @@ # Only one unified L1 cache exists. Can cache instructions and data. # l1_cntrl = L1Cache_Controller(version = i, - cntrl_id = cntrl_count, cacheMemory = cache, ruby_system = ruby_system) @@ -128,7 +127,6 @@ dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, - cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, size = dir_size), diff -r 99bd071911cf -r bf183de554f4 configs/ruby/Ruby.py --- a/configs/ruby/Ruby.py Sun Dec 29 19:29:45 2013 -0600 +++ b/configs/ruby/Ruby.py Wed Jan 01 12:47:01 2014 -0600 @@ -71,6 +71,9 @@ parser.add_option("--numa-high-bit", type="int", default=0, help="high order address bit to use for numa mapping. " \ "0 = highest bit, not specified = lowest bit") + parser.add_option("--num-clusters", type="int", default=1, + help="number of clusters in a design in which there are shared\ + caches private to clusters") # ruby sparse memory options parser.add_option("--use-map", action="store_true", default=False) diff -r 99bd071911cf -r bf183de554f4 src/mem/protocol/MESI_CMP_directory-L1cache.sm --- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm Sun Dec 29 19:29:45 2013 -0600 +++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm Wed Jan 01 12:47:01 2014 -0600 @@ -500,7 +500,7 @@ out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); DPRINTF(RubySlicc, "address: %s, destination: %s\n", address, out_msg.Destination); out_msg.MessageSize := MessageSizeType:Control; @@ -518,7 +518,7 @@ out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); DPRINTF(RubySlicc, "address: %s, destination: %s\n", address, out_msg.Destination); out_msg.MessageSize := MessageSizeType:Control; @@ -535,7 +535,7 @@ out_msg.Type := CoherenceRequestType:GET_INSTR; out_msg.Requestor := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); DPRINTF(RubySlicc, "address: %s, destination: %s\n", address, out_msg.Destination); out_msg.MessageSize := MessageSizeType:Control; @@ -555,7 +555,7 @@ out_msg.Requestor := machineID; out_msg.Destination.add( mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); out_msg.MessageSize := MessageSizeType:Control; out_msg.Prefetch := in_msg.Prefetch; out_msg.AccessMode := in_msg.AccessMode; @@ -574,7 +574,7 @@ out_msg.Requestor := machineID; DPRINTF(RubySlicc, "%s\n", machineID); out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); DPRINTF(RubySlicc, "address: %s, destination: %s\n", address, out_msg.Destination); out_msg.MessageSize := MessageSizeType:Control; @@ -593,10 +593,8 @@ out_msg.Requestor := machineID; DPRINTF(RubySlicc, "%s\n", machineID); - out_msg.Destination.add(mapAddressToRange(address, - MachineType:L2Cache, - l2_select_low_bit, - l2_select_num_bits)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, + l2_select_low_bit, l2_select_num_bits, intToID(0))); DPRINTF(RubySlicc, "address: %s, destination: %s\n", address, out_msg.Destination); @@ -614,7 +612,7 @@ out_msg.Type := CoherenceRequestType:UPGRADE; out_msg.Requestor := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); DPRINTF(RubySlicc, "address: %s, destination: %s\n", address, out_msg.Destination); out_msg.MessageSize := MessageSizeType:Control; @@ -648,7 +646,7 @@ out_msg.Dirty := cache_entry.Dirty; out_msg.Sender := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); out_msg.MessageSize := MessageSizeType:Response_Data; } } @@ -677,7 +675,7 @@ out_msg.Dirty := tbe.Dirty; out_msg.Sender := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); out_msg.MessageSize := MessageSizeType:Response_Data; } } @@ -703,7 +701,7 @@ out_msg.Dirty := cache_entry.Dirty; out_msg.Sender := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); out_msg.MessageSize := MessageSizeType:Writeback_Data; } } @@ -717,7 +715,7 @@ out_msg.Dirty := tbe.Dirty; out_msg.Sender := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); out_msg.MessageSize := MessageSizeType:Writeback_Data; } } @@ -751,7 +749,7 @@ out_msg.Dirty := cache_entry.Dirty; out_msg.Requestor:= machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); if (cache_entry.Dirty) { out_msg.MessageSize := MessageSizeType:Writeback_Data; } else { @@ -766,7 +764,7 @@ out_msg.Type := CoherenceResponseType:UNBLOCK; out_msg.Sender := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); out_msg.MessageSize := MessageSizeType:Response_Control; DPRINTF(RubySlicc, "%s\n", address); } @@ -778,7 +776,7 @@ out_msg.Type := CoherenceResponseType:EXCLUSIVE_UNBLOCK; out_msg.Sender := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); + l2_select_low_bit, l2_select_num_bits, intToID(0))); out_msg.MessageSize := MessageSizeType:Response_Control; DPRINTF(RubySlicc, "%s\n", address); diff -r 99bd071911cf -r bf183de554f4 src/mem/protocol/MESI_CMP_directory-dir.sm --- a/src/mem/protocol/MESI_CMP_directory-dir.sm Sun Dec 29 19:29:45 2013 -0600 +++ b/src/mem/protocol/MESI_CMP_directory-dir.sm Wed Jan 01 12:47:01 2014 -0600 @@ -39,7 +39,6 @@ MemoryControl * memBuffer, Cycles to_mem_ctrl_latency = 1, Cycles directory_latency = 6, - int l2_select_num_bits { MessageBuffer requestToDir, network="From", virtual_network="0", ordered="false", vnet_type="request"; @@ -83,6 +82,7 @@ structure(Entry, desc="...", interface="AbstractEntry") { State DirectoryState, desc="Directory state"; DataBlock DataBlk, desc="data for the block"; + MachineID Owner; } // TBE entries for DMA requests @@ -102,8 +102,6 @@ // ** OBJECTS ** - - int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; TBETable TBEs, template="", constructor="m_number_of_TBEs"; void set_tbe(TBE tbe); @@ -262,6 +260,9 @@ out_msg.DataBlk := in_msg.DataBlk; out_msg.Dirty := false; out_msg.MessageSize := MessageSizeType:Response_Data; + + Entry e := getDirectoryEntry(in_msg.Addr); + e.Owner := in_msg.OriginalRequestorMachId; } } } @@ -409,12 +410,11 @@ action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") { peek(requestNetwork_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) { - out_msg.Addr := address; - out_msg.Type := CoherenceResponseType:INV; - out_msg.Sender := machineID; - out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, - l2_select_low_bit, l2_select_num_bits)); - out_msg.MessageSize := MessageSizeType:Response_Control; + out_msg.Addr := address; + out_msg.Type := CoherenceResponseType:INV; + out_msg.Sender := machineID; + out_msg.Destination.add(getDirectoryEntry(address).Owner); + out_msg.MessageSize := MessageSizeType:Response_Control; } } } @@ -483,6 +483,11 @@ j_popIncomingRequestQueue; } + transition(M, Fetch) { + inv_sendCacheInvalidate; + z_stallAndWaitRequest; + } + transition(IM, Memory_Data, M) { d_sendData; l_popMemQueue; @@ -492,6 +497,7 @@ transition(M, CleanReplacement, I) { a_sendAck; k_popIncomingResponseQueue; + kd_wakeUpDependents; } transition(M, Data, MI) { @@ -578,5 +584,4 @@ l_popMemQueue; kd_wakeUpDependents; } - } diff -r 99bd071911cf -r bf183de554f4 src/mem/protocol/RubySlicc_ComponentMapping.sm --- a/src/mem/protocol/RubySlicc_ComponentMapping.sm Sun Dec 29 19:29:45 2013 -0600 +++ b/src/mem/protocol/RubySlicc_ComponentMapping.sm Wed Jan 01 12:47:01 2014 -0600 @@ -30,7 +30,8 @@ // Mapping functions int machineCount(MachineType machType); -MachineID mapAddressToRange(Address addr, MachineType type, int low, int high); +MachineID mapAddressToRange(Address addr, MachineType type, + int low, int high, NodeID n); NetDest broadcast(MachineType type); MachineID map_Address_to_DMA(Address addr); MachineID map_Address_to_Directory(Address addr); diff -r 99bd071911cf -r bf183de554f4 src/mem/protocol/RubySlicc_Defines.sm --- a/src/mem/protocol/RubySlicc_Defines.sm Sun Dec 29 19:29:45 2013 -0600 +++ b/src/mem/protocol/RubySlicc_Defines.sm Wed Jan 01 12:47:01 2014 -0600 @@ -31,4 +31,4 @@ NodeID id; NodeID version; MachineID machineID; - +NodeID clusterID; diff -r 99bd071911cf -r bf183de554f4 src/mem/ruby/common/NetDest.cc --- a/src/mem/ruby/common/NetDest.cc Sun Dec 29 19:29:45 2013 -0600 +++ b/src/mem/ruby/common/NetDest.cc Wed Jan 01 12:47:01 2014 -0600 @@ -102,7 +102,7 @@ void NetDest::broadcast(MachineType machineType) { - for (int i = 0; i < MachineType_base_count(machineType); i++) { + for (NodeID i = 0; i < MachineType_base_count(machineType); i++) { MachineID mach = {machineType, i}; add(mach); } @@ -146,7 +146,7 @@ { assert(count() > 0); for (int i = 0; i < m_bits.size(); i++) { - for (int j = 0; j < m_bits[i].getSize(); j++) { + for (NodeID j = 0; j < m_bits[i].getSize(); j++) { if (m_bits[i].isElement(j)) { MachineID mach = {MachineType_from_base_level(i), j}; return mach; @@ -160,7 +160,7 @@ NetDest::smallestElement(MachineType machine) const { int size = m_bits[MachineType_base_level(machine)].getSize(); - for (int j = 0; j < size; j++) { + for (NodeID j = 0; j < size; j++) { if (m_bits[MachineType_base_level(machine)].isElement(j)) { MachineID mach = {machine, j}; return mach; diff -r 99bd071911cf -r bf183de554f4 src/mem/ruby/common/TypeDefines.hh --- a/src/mem/ruby/common/TypeDefines.hh Sun Dec 29 19:29:45 2013 -0600 +++ b/src/mem/ruby/common/TypeDefines.hh Wed Jan 01 12:47:01 2014 -0600 @@ -37,8 +37,8 @@ typedef uint64 physical_address_t; typedef int64 Index; // what the address bit ripper returns -typedef int LinkID; -typedef int NodeID; -typedef int SwitchID; +typedef unsigned int LinkID; +typedef unsigned int NodeID; +typedef unsigned int SwitchID; #endif diff -r 99bd071911cf -r bf183de554f4 src/mem/ruby/network/Topology.hh --- a/src/mem/ruby/network/Topology.hh Sun Dec 29 19:29:45 2013 -0600 +++ b/src/mem/ruby/network/Topology.hh Wed Jan 01 12:47:01 2014 -0600 @@ -59,7 +59,7 @@ LinkDirection direction; }; -typedef std::map, LinkEntry> LinkMap; +typedef std::map, LinkEntry> LinkMap; class Topology { diff -r 99bd071911cf -r bf183de554f4 src/mem/ruby/network/Topology.cc --- a/src/mem/ruby/network/Topology.cc Sun Dec 29 19:29:45 2013 -0600 +++ b/src/mem/ruby/network/Topology.cc Wed Jan 01 12:47:01 2014 -0600 @@ -129,7 +129,7 @@ SwitchID max_switch_id = 0; for (LinkMap::const_iterator i = m_link_map.begin(); i != m_link_map.end(); ++i) { - std::pair src_dest = (*i).first; + std::pair src_dest = (*i).first; max_switch_id = max(max_switch_id, src_dest.first); max_switch_id = max(max_switch_id, src_dest.second); } @@ -310,7 +310,7 @@ max_machines = MachineType_base_number(MachineType_NUM); for (int m = 0; m < machines; m++) { - for (int i = 0; i < MachineType_base_count((MachineType)m); i++) { + for (NodeID i = 0; i < MachineType_base_count((MachineType)m); i++) { // we use "d+max_machines" below since the "destination" // switches for the machines are numbered // [MachineType_base_number(MachineType_NUM)... diff -r 99bd071911cf -r bf183de554f4 src/mem/ruby/slicc_interface/AbstractController.hh --- a/src/mem/ruby/slicc_interface/AbstractController.hh Sun Dec 29 19:29:45 2013 -0600 +++ b/src/mem/ruby/slicc_interface/AbstractController.hh Wed Jan 01 12:47:01 2014 -0600 @@ -56,7 +56,7 @@ void init(); const Params *params() const { return (const Params *)_params; } - const int & getVersion() const { return m_version; } + const NodeID getVersion() const { return m_version; } void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; } // return instance name @@ -133,13 +133,12 @@ void wakeUpAllBuffers(); protected: - int m_transitions_per_cycle; - int m_buffer_size; - Cycles m_recycle_latency; std::string m_name; NodeID m_version; + MachineID m_machineID; + NodeID m_clusterID; + Network* m_net_ptr; - MachineID m_machineID; bool m_is_blocking; std::map m_block_map; typedef std::vector MsgVecType; @@ -148,6 +147,9 @@ unsigned int m_in_ports; unsigned int m_cur_in_port; int m_number_of_TBEs; + int m_transitions_per_cycle; + int m_buffer_size; + Cycles m_recycle_latency; //! Map from physical network number to the Message Buffer. std::map peerQueueMap; diff -r 99bd071911cf -r bf183de554f4 src/mem/ruby/slicc_interface/AbstractController.cc --- a/src/mem/ruby/slicc_interface/AbstractController.cc Sun Dec 29 19:29:45 2013 -0600 +++ b/src/mem/ruby/slicc_interface/AbstractController.cc Wed Jan 01 12:47:01 2014 -0600 @@ -35,6 +35,8 @@ m_request_count(0) { m_version = p->version; + m_clusterID = p->cluster_id; + m_transitions_per_cycle = p->transitions_per_cycle; m_buffer_size = p->buffer_size; m_recycle_latency = p->recycle_latency; diff -r 99bd071911cf -r bf183de554f4 src/mem/ruby/slicc_interface/Controller.py --- a/src/mem/ruby/slicc_interface/Controller.py Sun Dec 29 19:29:45 2013 -0600 +++ b/src/mem/ruby/slicc_interface/Controller.py Wed Jan 01 12:47:01 2014 -0600 @@ -36,7 +36,8 @@ cxx_header = "mem/ruby/slicc_interface/AbstractController.hh" abstract = True version = Param.Int("") - cntrl_id = Param.Int("") + cluster_id = Param.UInt32(0, "Id of this controller's cluster") + transitions_per_cycle = \ Param.Int(32, "no. of SLICC state machine transitions per cycle") buffer_size = Param.Int(0, "max buffer size 0 means infinite") diff -r 99bd071911cf -r bf183de554f4 src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh --- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh Sun Dec 29 19:29:45 2013 -0600 +++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh Wed Jan 01 12:47:01 2014 -0600 @@ -58,7 +58,7 @@ broadcast(MachineType type) { NetDest dest; - for (int i = 0; i < MachineType_base_count(type); i++) { + for (NodeID i = 0; i < MachineType_base_count(type); i++) { MachineID mach = {type, i}; dest.add(mach); } @@ -67,12 +67,14 @@ inline MachineID mapAddressToRange(const Address & addr, MachineType type, int low_bit, - int num_bits) + int num_bits, int cluster_id = 0) { MachineID mach = {type, 0}; if (num_bits == 0) - return mach; - mach.num = addr.bitSelect(low_bit, low_bit + num_bits - 1); + mach.num = cluster_id; + else + mach.num = addr.bitSelect(low_bit, low_bit + num_bits - 1) + + (1 << num_bits) * cluster_id; return mach; } diff -r 99bd071911cf -r bf183de554f4 src/mem/slicc/ast/ObjDeclAST.py --- a/src/mem/slicc/ast/ObjDeclAST.py Sun Dec 29 19:29:45 2013 -0600 +++ b/src/mem/slicc/ast/ObjDeclAST.py Wed Jan 01 12:47:01 2014 -0600 @@ -70,6 +70,8 @@ c_code = "m_version" elif self.ident == "machineID": c_code = "m_machineID" + elif self.ident == "clusterID": + c_code = "m_clusterID" elif machine: c_code = "(*m_%s_%s_ptr)" % (machine.ident, self.ident) else: