diff -r d12e9a8541c3 -r 6be85e163055 configs/ruby/MESI_Three_Level.py
--- a/configs/ruby/MESI_Three_Level.py	Thu Jan 23 15:51:46 2014 +0000
+++ b/configs/ruby/MESI_Three_Level.py	Thu Jan 23 15:55:50 2014 +0000
@@ -84,6 +84,9 @@
     block_size_bits = int(math.log(options.cacheline_size, 2))
     l2_index_start = block_size_bits + l2_bits
 
+    # We need somewhere to store the potential pio bridges
+    piobridges = []
+
     #
     # Must create the individual controllers before the network to ensure the
     # controller constructors are called before the network constructor
@@ -117,7 +120,12 @@
                           cluster_id = i, ruby_system = ruby_system)
 
             if piobus != None:
-                cpu_seq.pio_port = piobus.slave
+                # the sequencer is a multiplexing component, and to
+                # connect it to a pio bus we need to go through a bridge
+                bridge = Bridge()
+                cpu_seq.pio_port = bridge.slave
+                bridge.master = piobus.slave
+                piobridges.append(bridge)
 
             exec("ruby_system.l0_cntrl%d = l0_cntrl" % (
                         i*num_cpus_per_cluster+j))
@@ -147,6 +155,9 @@
                         i * num_l2caches_per_cluster + j))
             l2_cntrl_nodes.append(l2_cntrl)
 
+    if piobridges:
+        ruby_system.piobridges = piobridges
+
     phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
     assert(phys_mem_size % options.num_dirs == 0)
     mem_module_size = phys_mem_size / options.num_dirs
diff -r d12e9a8541c3 -r 6be85e163055 configs/ruby/MESI_Two_Level.py
--- a/configs/ruby/MESI_Two_Level.py	Thu Jan 23 15:51:46 2014 +0000
+++ b/configs/ruby/MESI_Two_Level.py	Thu Jan 23 15:55:50 2014 +0000
@@ -72,6 +72,9 @@
     l2_bits = int(math.log(options.num_l2caches, 2))
     block_size_bits = int(math.log(options.cacheline_size, 2))
 
+    # We need somewhere to store the potential pio bridges
+    piobridges = []
+
     for i in xrange(options.num_cpus):
         #
         # First create the Ruby objects associated with this cpu
@@ -106,7 +109,12 @@
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.slave
+            # the sequencer is a multiplexing component, and to
+            # connect it to a pio bus we need to go through a bridge
+            bridge = Bridge()
+            cpu_seq.pio_port = bridge.slave
+            bridge.master = piobus.slave
+            piobridges.append(bridge)
 
         exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
 
@@ -134,6 +142,9 @@
         exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
         l2_cntrl_nodes.append(l2_cntrl)
 
+    if piobridges:
+        ruby_system.piobridges = piobridges
+
     phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
     assert(phys_mem_size % options.num_dirs == 0)
     mem_module_size = phys_mem_size / options.num_dirs
diff -r d12e9a8541c3 -r 6be85e163055 configs/ruby/MI_example.py
--- a/configs/ruby/MI_example.py	Thu Jan 23 15:51:46 2014 +0000
+++ b/configs/ruby/MI_example.py	Thu Jan 23 15:55:50 2014 +0000
@@ -64,6 +64,9 @@
     #
     block_size_bits = int(math.log(options.cacheline_size, 2))
 
+    # We need somewhere to store the potential pio bridges
+    piobridges = []
+
     for i in xrange(options.num_cpus):
         #
         # First create the Ruby objects associated with this cpu
@@ -92,7 +95,12 @@
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.slave
+            # the sequencer is a multiplexing component, and to
+            # connect it to a pio bus we need to go through a bridge
+            bridge = Bridge()
+            cpu_seq.pio_port = bridge.slave
+            bridge.master = piobus.slave
+            piobridges.append(bridge)
 
         exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
         #
@@ -101,6 +109,9 @@
         cpu_sequencers.append(cpu_seq)
         l1_cntrl_nodes.append(l1_cntrl)
 
+    if piobridges:
+        ruby_system.piobridges = piobridges
+
     phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
     assert(phys_mem_size % options.num_dirs == 0)
     mem_module_size = phys_mem_size / options.num_dirs
diff -r d12e9a8541c3 -r 6be85e163055 configs/ruby/MOESI_CMP_directory.py
--- a/configs/ruby/MOESI_CMP_directory.py	Thu Jan 23 15:51:46 2014 +0000
+++ b/configs/ruby/MOESI_CMP_directory.py	Thu Jan 23 15:55:50 2014 +0000
@@ -72,6 +72,9 @@
     l2_bits = int(math.log(options.num_l2caches, 2))
     block_size_bits = int(math.log(options.cacheline_size, 2))
 
+    # We need somewhere to store the potential pio bridges
+    piobridges = []
+
     for i in xrange(options.num_cpus):
         #
         # First create the Ruby objects associated with this cpu
@@ -102,7 +105,12 @@
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.slave
+            # the sequencer is a multiplexing component, and to
+            # connect it to a pio bus we need to go through a bridge
+            bridge = Bridge()
+            cpu_seq.pio_port = bridge.slave
+            bridge.master = piobus.slave
+            piobridges.append(bridge)
 
         exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
         #
@@ -111,6 +119,9 @@
         cpu_sequencers.append(cpu_seq)
         l1_cntrl_nodes.append(l1_cntrl)
 
+    if piobridges:
+        ruby_system.piobridges = piobridges
+
     l2_index_start = block_size_bits + l2_bits
 
     for i in xrange(options.num_l2caches):
diff -r d12e9a8541c3 -r 6be85e163055 configs/ruby/MOESI_CMP_token.py
--- a/configs/ruby/MOESI_CMP_token.py	Thu Jan 23 15:51:46 2014 +0000
+++ b/configs/ruby/MOESI_CMP_token.py	Thu Jan 23 15:55:50 2014 +0000
@@ -84,7 +84,10 @@
     #
     l2_bits = int(math.log(options.num_l2caches, 2))
     block_size_bits = int(math.log(options.cacheline_size, 2))
-    
+
+    # We need somewhere to store the potential pio bridges
+    piobridges = []
+
     for i in xrange(options.num_cpus):
         #
         # First create the Ruby objects associated with this cpu
@@ -122,7 +125,12 @@
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.slave
+            # the sequencer is a multiplexing component, and to
+            # connect it to a pio bus we need to go through a bridge
+            bridge = Bridge()
+            cpu_seq.pio_port = bridge.slave
+            bridge.master = piobus.slave
+            piobridges.append(bridge)
 
         exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
         #
@@ -131,6 +139,9 @@
         cpu_sequencers.append(cpu_seq)
         l1_cntrl_nodes.append(l1_cntrl)
 
+    if piobridges:
+        ruby_system.piobridges = piobridges
+
     l2_index_start = block_size_bits + l2_bits
 
     for i in xrange(options.num_l2caches):
diff -r d12e9a8541c3 -r 6be85e163055 configs/ruby/MOESI_hammer.py
--- a/configs/ruby/MOESI_hammer.py	Thu Jan 23 15:51:46 2014 +0000
+++ b/configs/ruby/MOESI_hammer.py	Thu Jan 23 15:55:50 2014 +0000
@@ -81,6 +81,9 @@
     #
     block_size_bits = int(math.log(options.cacheline_size, 2))
 
+    # We need somewhere to store the potential pio bridges
+    piobridges = []
+
     for i in xrange(options.num_cpus):
         #
         # First create the Ruby objects associated with this cpu
@@ -115,7 +118,12 @@
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.slave
+            # the sequencer is a multiplexing component, and to
+            # connect it to a pio bus we need to go through a bridge
+            bridge = Bridge()
+            cpu_seq.pio_port = bridge.slave
+            bridge.master = piobus.slave
+            piobridges.append(bridge)
 
         if options.recycle_latency:
             l1_cntrl.recycle_latency = options.recycle_latency
@@ -127,6 +135,9 @@
         cpu_sequencers.append(cpu_seq)
         l1_cntrl_nodes.append(l1_cntrl)
 
+    if piobridges:
+        ruby_system.piobridges = piobridges
+
     phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
     assert(phys_mem_size % options.num_dirs == 0)
     mem_module_size = phys_mem_size / options.num_dirs
diff -r d12e9a8541c3 -r 6be85e163055 src/mem/ruby/system/RubyPort.cc
--- a/src/mem/ruby/system/RubyPort.cc	Thu Jan 23 15:51:46 2014 +0000
+++ b/src/mem/ruby/system/RubyPort.cc	Thu Jan 23 15:55:50 2014 +0000
@@ -171,6 +171,10 @@
     if (pkt->memInhibitAsserted())
         panic("RubyPort should never see an inhibited request\n");
 
+    // set a source to please the PIO bridge, even if we currently do
+    // not look at the field for routing of responses
+    pkt->setSrc(0);
+
     // Save the port in the sender state object to be used later to
     // route the response
     pkt->pushSenderState(new SenderState(this));