diff -r bc430ee79714 -r 0763ea34d0f8 configs/example/fs.py --- a/configs/example/fs.py Wed Sep 24 23:45:39 2014 -0500 +++ b/configs/example/fs.py Wed Sep 24 23:47:48 2014 -0500 @@ -136,6 +136,8 @@ sys.exit(1) Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports) + test_sys.physmem = [SimpleMemory(range = r, null = True) + for r in test_sys.mem_ranges] # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, @@ -162,11 +164,9 @@ test_sys.ruby._cpu_ports[i].access_phys_mem = True - # Create the appropriate memory controllers - # and connect them to the IO bus - test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges] - for i in xrange(len(test_sys.mem_ctrls)): - test_sys.mem_ctrls[i].port = test_sys.iobus.master + # Connect the ruby io port to the PIO bus, + # assuming that there is just one such port. + test_sys.iobus.master = test_sys.ruby._io_port.slave else: if options.caches or options.l2cache: diff -r bc430ee79714 -r 0763ea34d0f8 configs/example/ruby_mem_test.py --- a/configs/example/ruby_mem_test.py Wed Sep 24 23:45:39 2014 -0500 +++ b/configs/example/ruby_mem_test.py Wed Sep 24 23:47:48 2014 -0500 @@ -159,12 +159,6 @@ # system.ruby._cpu_ports[i].deadlock_threshold = 5000000 - # - # Ruby doesn't need the backing image of memory when running with - # the tester. - # - system.ruby._cpu_ports[i].access_phys_mem = False - for (i, dma) in enumerate(dmas): # # Tie the dma memtester ports to the correct functional port diff -r bc430ee79714 -r 0763ea34d0f8 configs/example/ruby_network_test.py --- a/configs/example/ruby_network_test.py Wed Sep 24 23:45:39 2014 -0500 +++ b/configs/example/ruby_network_test.py Wed Sep 24 23:47:48 2014 -0500 @@ -125,8 +125,6 @@ # Tie the cpu test ports to the ruby cpu port # cpus[i].test = ruby_port.slave - ruby_port.access_phys_mem = False - i += 1 # ----------------------- diff -r bc430ee79714 -r 0763ea34d0f8 configs/example/ruby_random_test.py --- a/configs/example/ruby_random_test.py Wed Sep 24 23:45:39 2014 -0500 +++ b/configs/example/ruby_random_test.py Wed Sep 24 23:47:48 2014 -0500 @@ -137,12 +137,6 @@ # ruby_port.using_ruby_tester = True - # - # Ruby doesn't need the backing image of memory when running with - # the tester. - # - ruby_port.access_phys_mem = False - # ----------------------- # run simulation # ----------------------- diff -r bc430ee79714 -r 0763ea34d0f8 configs/ruby/MESI_Two_Level.py --- a/configs/ruby/MESI_Two_Level.py Wed Sep 24 23:45:39 2014 -0500 +++ b/configs/ruby/MESI_Two_Level.py Wed Sep 24 23:47:48 2014 -0500 @@ -196,7 +196,8 @@ for i, dma_port in enumerate(dma_ports): # Create the Ruby objects associated with the dma controller dma_seq = DMASequencer(version = i, - ruby_system = ruby_system) + ruby_system = ruby_system, + slave = dma_port) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, @@ -204,7 +205,6 @@ ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) - exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) # Connect the dma controller to the network @@ -212,11 +212,24 @@ dma_cntrl.requestToDir = ruby_system.network.slave + # Create the io controller and the sequencer + io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) + ruby_system._io_port = io_seq + io_controller = DMA_Controller(version = len(dma_ports), + dma_sequencer = io_seq, + ruby_system = ruby_system) + ruby_system.io_controller = io_controller + + # Connect the dma controller to the network + io_controller.responseFromDir = ruby_system.network.master + io_controller.requestToDir = ruby_system.network.slave + + all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ - dma_cntrl_nodes + dma_cntrl_nodes + \ + [io_controller] topology = create_topology(all_cntrls, options) - return (cpu_sequencers, dir_cntrl_nodes, topology) diff -r bc430ee79714 -r 0763ea34d0f8 configs/ruby/MOESI_CMP_directory.py --- a/configs/ruby/MOESI_CMP_directory.py Wed Sep 24 23:45:39 2014 -0500 +++ b/configs/ruby/MOESI_CMP_directory.py Wed Sep 24 23:47:48 2014 -0500 @@ -192,7 +192,8 @@ # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, - ruby_system = ruby_system) + ruby_system = ruby_system, + slave = dma_port) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, @@ -200,14 +201,33 @@ ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) - exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) + # Connect the dma controller to the network + dma_cntrl.responseFromDir = ruby_system.network.master + dma_cntrl.reqToDir = ruby_system.network.slave + dma_cntrl.respToDir = ruby_system.network.slave + + + # Create the io controller and the sequencer + io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) + ruby_system._io_port = io_seq + io_controller = DMA_Controller(version = len(dma_ports), + dma_sequencer = io_seq, + ruby_system = ruby_system) + ruby_system.io_controller = io_controller + + # Connect the dma controller to the network + io_controller.responseFromDir = ruby_system.network.master + io_controller.reqToDir = ruby_system.network.slave + io_controller.respToDir = ruby_system.network.slave + all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ - dma_cntrl_nodes + dma_cntrl_nodes + \ + [io_controller] topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology) diff -r bc430ee79714 -r 0763ea34d0f8 configs/ruby/MOESI_CMP_token.py --- a/configs/ruby/MOESI_CMP_token.py Wed Sep 24 23:45:39 2014 -0500 +++ b/configs/ruby/MOESI_CMP_token.py Wed Sep 24 23:47:48 2014 -0500 @@ -222,7 +222,8 @@ # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, - ruby_system = ruby_system) + ruby_system = ruby_system, + slave = dma_port) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, @@ -230,13 +231,30 @@ ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) - exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) + # Connect the dma controller to the network + dma_cntrl.responseFromDir = ruby_system.network.master + dma_cntrl.reqToDirectory = ruby_system.network.slave + + + # Create the io controller and the sequencer + io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) + ruby_system._io_port = io_seq + io_controller = DMA_Controller(version = len(dma_ports), + dma_sequencer = io_seq, + ruby_system = ruby_system) + ruby_system.io_controller = io_controller + + # Connect the dma controller to the network + io_controller.responseFromDir = ruby_system.network.master + io_controller.reqToDirectory = ruby_system.network.slave + all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ - dma_cntrl_nodes + dma_cntrl_nodes + \ + [io_controller] topology = create_topology(all_cntrls, options) diff -r bc430ee79714 -r 0763ea34d0f8 configs/ruby/MOESI_hammer.py --- a/configs/ruby/MOESI_hammer.py Wed Sep 24 23:45:39 2014 -0500 +++ b/configs/ruby/MOESI_hammer.py Wed Sep 24 23:47:48 2014 -0500 @@ -224,7 +224,8 @@ # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, - ruby_system = ruby_system) + ruby_system = ruby_system, + slave = dma_port) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, @@ -232,7 +233,6 @@ ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) - exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) if options.recycle_latency: @@ -242,7 +242,20 @@ dma_cntrl.responseFromDir = ruby_system.network.master dma_cntrl.requestToDir = ruby_system.network.slave + # Create the io controller and the sequencer + io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) + ruby_system._io_port = io_seq + io_controller = DMA_Controller(version = len(dma_ports), + dma_sequencer = io_seq, + ruby_system = ruby_system) + ruby_system.io_controller = io_controller - all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes + # Connect the dma controller to the network + io_controller.responseFromDir = ruby_system.network.master + io_controller.requestToDir = ruby_system.network.slave + + + all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes + \ + [io_controller] topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology) diff -r bc430ee79714 -r 0763ea34d0f8 src/mem/protocol/MESI_Two_Level-dma.sm --- a/src/mem/protocol/MESI_Two_Level-dma.sm Wed Sep 24 23:45:39 2014 -0500 +++ b/src/mem/protocol/MESI_Two_Level-dma.sm Wed Sep 24 23:47:48 2014 -0500 @@ -49,11 +49,6 @@ Ack, desc="DMA write to memory completed"; } - structure(DMASequencer, external="yes") { - void ackCallback(); - void dataCallback(DataBlock); - } - MessageBuffer mandatoryQueue, ordered="false"; State cur_state; diff -r bc430ee79714 -r 0763ea34d0f8 src/mem/protocol/MOESI_CMP_directory-dma.sm --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm Wed Sep 24 23:45:39 2014 -0500 +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm Wed Sep 24 23:47:48 2014 -0500 @@ -62,11 +62,6 @@ DataBlock DataBlk, desc="Data"; } - structure(DMASequencer, external = "yes") { - void ackCallback(); - void dataCallback(DataBlock); - } - structure(TBETable, external = "yes") { TBE lookup(Address); void allocate(Address); diff -r bc430ee79714 -r 0763ea34d0f8 src/mem/protocol/MOESI_CMP_token-dma.sm --- a/src/mem/protocol/MOESI_CMP_token-dma.sm Wed Sep 24 23:45:39 2014 -0500 +++ b/src/mem/protocol/MOESI_CMP_token-dma.sm Wed Sep 24 23:47:48 2014 -0500 @@ -51,11 +51,6 @@ Ack, desc="DMA write to memory completed"; } - structure(DMASequencer, external="yes") { - void ackCallback(); - void dataCallback(DataBlock); - } - MessageBuffer mandatoryQueue, ordered="false"; State cur_state; diff -r bc430ee79714 -r 0763ea34d0f8 src/mem/ruby/system/DMASequencer.hh --- a/src/mem/ruby/system/DMASequencer.hh Wed Sep 24 23:45:39 2014 -0500 +++ b/src/mem/ruby/system/DMASequencer.hh Wed Sep 24 23:47:48 2014 -0500 @@ -65,11 +65,9 @@ { private: SlavePacketQueue queue; - bool access_phys_mem; public: - MemSlavePort(const std::string &_name, DMASequencer *_port, - bool _access_phys_mem, PortID id); + MemSlavePort(const std::string &_name, DMASequencer *_port, PortID id); void hitCallback(PacketPtr pkt); void evictionCallback(const Address& address); @@ -146,8 +144,6 @@ System* system; bool retry; - bool access_phys_mem; - bool m_is_busy; uint64_t m_data_block_mask; DMARequest active_request; diff -r bc430ee79714 -r 0763ea34d0f8 src/mem/ruby/system/DMASequencer.cc --- a/src/mem/ruby/system/DMASequencer.cc Wed Sep 24 23:45:39 2014 -0500 +++ b/src/mem/ruby/system/DMASequencer.cc Wed Sep 24 23:47:48 2014 -0500 @@ -38,12 +38,10 @@ DMASequencer::DMASequencer(const Params *p) : MemObject(p), m_version(p->version), m_controller(NULL), m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester), - drainManager(NULL), system(p->system), retry(false), - access_phys_mem(p->access_phys_mem) + drainManager(NULL), system(p->system), retry(false) { assert(m_version != -1); - slave_port = new MemSlavePort(csprintf("%s.slave", name()), this, - access_phys_mem, 0); + slave_port = new MemSlavePort(csprintf("%s.slave", name()), this, 0); } void @@ -71,9 +69,8 @@ } DMASequencer::MemSlavePort::MemSlavePort(const std::string &_name, - DMASequencer *_port, bool _access_phys_mem, PortID id) - : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this), - access_phys_mem(_access_phys_mem) + DMASequencer *_port, PortID id) + : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this) { DPRINTF(RubyDma, "Created slave memport on ruby sequencer %s\n", _name); } @@ -201,17 +198,12 @@ DMASequencer::MemSlavePort::hitCallback(PacketPtr pkt) { bool needsResponse = pkt->needsResponse(); - bool accessPhysMem = access_phys_mem; - assert(!pkt->isLLSC()); assert(!pkt->isFlush()); DPRINTF(RubyDma, "Hit callback needs response %d\n", needsResponse); - if (accessPhysMem) { - DMASequencer *seq = static_cast(&owner); - seq->system->getPhysMem().access(pkt); - } else if (needsResponse) { + if (needsResponse) { pkt->makeResponse(); } diff -r bc430ee79714 -r 0763ea34d0f8 src/mem/ruby/system/RubyPort.hh --- a/src/mem/ruby/system/RubyPort.hh Wed Sep 24 23:45:39 2014 -0500 +++ b/src/mem/ruby/system/RubyPort.hh Wed Sep 24 23:47:48 2014 -0500 @@ -73,14 +73,12 @@ class MemSlavePort : public QueuedSlavePort { private: - SlavePacketQueue queue; RubySystem* ruby_system; - bool access_phys_mem; public: MemSlavePort(const std::string &_name, RubyPort *_port, - RubySystem*_system, bool _access_phys_mem, PortID id); + RubySystem*_system, PortID id); void hitCallback(PacketPtr pkt); void evictionCallback(const Address& address); @@ -212,8 +210,6 @@ // that should be called when the Sequencer becomes available after a stall. // std::vector retryList; - - bool access_phys_mem; }; #endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__ diff -r bc430ee79714 -r 0763ea34d0f8 src/mem/ruby/system/RubyPort.cc --- a/src/mem/ruby/system/RubyPort.cc Wed Sep 24 23:45:39 2014 -0500 +++ b/src/mem/ruby/system/RubyPort.cc Wed Sep 24 23:47:48 2014 -0500 @@ -56,16 +56,15 @@ pioSlavePort(csprintf("%s.pio-slave-port", name()), this), memMasterPort(csprintf("%s.mem-master-port", name()), this), memSlavePort(csprintf("%s-mem-slave-port", name()), this, - p->ruby_system, p->access_phys_mem, -1), - gotAddrRanges(p->port_master_connection_count), drainManager(NULL), - system(p->system), access_phys_mem(p->access_phys_mem) + p->ruby_system, -1), gotAddrRanges(p->port_master_connection_count), + drainManager(NULL), system(p->system) { assert(m_version != -1); // create the slave ports based on the number of connected ports for (size_t i = 0; i < p->port_slave_connection_count; ++i) { slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(), - i), this, p->ruby_system, access_phys_mem, i)); + i), this, p->ruby_system, i)); } // create the master ports based on the number of connected ports @@ -154,9 +153,9 @@ } RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port, - RubySystem *_system, bool _access_phys_mem, PortID id) + RubySystem *_system, PortID id) : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this), - ruby_system(_system), access_phys_mem(_access_phys_mem) + ruby_system(_system) { DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name); } @@ -309,14 +308,6 @@ pkt->isWrite() ? "write" : "read", pkt->getAddr()); } - if (access_phys_mem) { - // The attached physmem contains the official version of data. - // The following command performs the real functional access. - // This line should be removed once Ruby supplies the official version - // of data. - ruby_port->system->getPhysMem().functionalAccess(pkt); - } - // turn packet around to go back to requester if response expected if (needsResponse) { pkt->setFunctionalResponseStatus(accessSucceeded); @@ -454,12 +445,8 @@ { bool needsResponse = pkt->needsResponse(); - // // Unless specified at configuraiton, all responses except failed SC // and Flush operations access M5 physical memory. - // - bool accessPhysMem = access_phys_mem; - if (pkt->isLLSC()) { if (pkt->isWrite()) { if (pkt->req->getExtraData() != 0) { @@ -467,12 +454,6 @@ // Successful SC packets convert to normal writes // pkt->convertScToWrite(); - } else { - // - // Failed SC packets don't access physical memory and thus - // the RubyPort itself must convert it to a response. - // - accessPhysMem = false; } } else { // @@ -483,19 +464,9 @@ } } - // - // Flush requests don't access physical memory - // - if (pkt->isFlush()) { - accessPhysMem = false; - } - DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); - if (accessPhysMem) { - RubyPort *ruby_port = static_cast(&owner); - ruby_port->system->getPhysMem().access(pkt); - } else if (needsResponse) { + if (needsResponse) { pkt->makeResponse(); } diff -r bc430ee79714 -r 0763ea34d0f8 src/mem/ruby/system/Sequencer.py --- a/src/mem/ruby/system/Sequencer.py Wed Sep 24 23:45:39 2014 -0500 +++ b/src/mem/ruby/system/Sequencer.py Wed Sep 24 23:47:48 2014 -0500 @@ -45,8 +45,6 @@ mem_slave_port = SlavePort("Ruby memory port") using_ruby_tester = Param.Bool(False, "") - access_phys_mem = Param.Bool(False, - "should the rubyport atomically update phys_mem") ruby_system = Param.RubySystem("") system = Param.System(Parent.any, "system object") support_data_reqs = Param.Bool(True, "data cache requests supported") @@ -55,7 +53,6 @@ class RubyPortProxy(RubyPort): type = 'RubyPortProxy' cxx_header = "mem/ruby/system/RubyPortProxy.hh" - access_phys_mem = True class RubySequencer(RubyPort): type = 'RubySequencer' @@ -78,7 +75,5 @@ slave = SlavePort("Device slave port") using_ruby_tester = Param.Bool(False, "") - access_phys_mem = Param.Bool(True, - "should the rubyport atomically update phys_mem") ruby_system = Param.RubySystem(Parent.any, "") system = Param.System(Parent.any, "system object") diff -r bc430ee79714 -r 0763ea34d0f8 tests/configs/pc-simple-timing-ruby.py --- a/tests/configs/pc-simple-timing-ruby.py Wed Sep 24 23:45:39 2014 -0500 +++ b/tests/configs/pc-simple-timing-ruby.py Wed Sep 24 23:47:48 2014 -0500 @@ -82,17 +82,13 @@ cpu.dcache_port = system.ruby._cpu_ports[i].slave cpu.itb.walker.port = system.ruby._cpu_ports[i].slave cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave + cpu.interrupts.pio = system.ruby._cpu_ports[i].master cpu.interrupts.int_master = system.ruby._cpu_ports[i].slave cpu.interrupts.int_slave = system.ruby._cpu_ports[i].master - # Set access_phys_mem to True for ruby port - system.ruby._cpu_ports[i].access_phys_mem = True - -system.physmem = [DDR3_1600_x64(range = r) +system.physmem = [SimpleMemory(range = r, null = True) for r in system.mem_ranges] -for i in xrange(len(system.physmem)): - system.physmem[i].port = system.iobus.master root = Root(full_system = True, system = system) m5.ticks.setGlobalFrequency('1THz')